KAF-6303E
Performance Specification
KAF- 6303E
3072 (H) x 2048 (V) Pixel
Enhanced Response
Full-Frame CCD Image Sensor
Performance Specification
Eastman Kodak Company
Image Sensor Solutions
Rochester, New York 14650-2010
Revision 3.0
December 18, 2003
Eastman Kodak Company - Image Sensor Solutions
www.kodak.com/go/imagers Phone: (585) 722-4385 E-mail: imagers@kodak.com
KAF-6303E
Performance Specification
TABLE OF CONTENTS
1.1 Features ..............................................................................................................................................3
1.2 Description .........................................................................................................................................3
1.3 Image Acquisition ..............................................................................................................................4
1.4 Charge Transport................................................................................................................................4
1.5 Output Structure ................................................................................................................................. 4
1.6 Dark Reference Pixels ....................................................................................................................... 4
1.7 Dummy Pixels. ................................................................................................................................... 4
2.1 Package Drawing................................................................................................................................5
2.2 Pin Description ...................................................................................................................................6
3.1 Absolute Maximum Ratings...............................................................................................................7
3.2 DC Operating Conditions...................................................................................................................8
3.3 AC Operating Conditions...................................................................................................................9
3.4 AC Timing Conditions .......................................................................................................................9
4.1 Performance Specifications..............................................................................................................11
4.2 Typical Performance Characteristics Spectral Response ................................................................12
4.3 Defect Classification ........................................................................................................................13
5.1 Quality Assurance and Reliability....................................................................................................14
5.2 Ordering Information .......................................................................................................................15
Revision Changes ..................................................................................................................................16
FIGURES
Figure 1 Functional Block Diagram
3
Figure 2 Package Diagram
5
Figure 3 Package Pin Designations
6
Figure 4 Recommended Output Structure Load Diagram
8
Figure 5 Timing Diagrams
10
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Revision No. 3.0
KAF-6303E
Performance Specification
1.1 Features
6M Pixel Area CCD
3072H x 2048V (9
m) Pixels
Transparent Gate True Two Phase Technology
(Enhanced Spectral Response)
27.65mm H x 18.48mm V Photosensitive Area
2-Phase Register Clocking
100% Fill Factor
Low Dark Current ( <10pA/cm2 @ 25oC)
1.2 Description
The KAF-6303E is a high performance monochrome
area CCD (charge-coupled device) image sensor with
3072H x 2048V photo active pixels designed for a wide
range of image sensing applications in the 0.3 nm to 1.0
nm wavelength band. Typical applications include
military, scientific, and industrial imaging. A 74dB
dynamic range is possible operating at room
temperature.
The sensor is built with a true two-phase CCD
technology. This technology simplifies the support
circuits that drive the sensor and reduces the dark
KAF - 6303E
Usable Active Image Area
3072(H) x 2048(V)
9 x 9
m pixels
3:2 aspect ratio
3072 Active Pixels/Line
6 Dark
10 Inactive
V rd
R
V dd
V out
V ss
Sub
V og
H1
H2
V 1
V 2
Guard
2 Inactive
10 Dark
4 Dark lines
4 Dark lines
current without compromising charge capacity. The
transparent gate results in spectral response increased
ten times at 400nm, compared to a front side
illuminated standard polysilicon gate technology. The
sensitivity is increased 50% over the rest of the visible
wavelengths.
Total chip size is 29.0 mm x 19.1 mm and is housed in
a 26-pin, 0.88" wide DIL ceramic package with 0.1"
pin spacing.
The sensor consists of 3088 parallel (vertical) CCD
shift registers each 2056 elements long. These registers
act as both the photosensitive elements and as the
transport circuits that allow the image to be sequentially
read out of the sensor. The elements of these registers
are arranged into a 3072 x 2048 photosensitive array
surrounded by a light shielded dark reference of 16
columns and 8 rows. The parallel (vertical) CCD
registers transfer the image one line at a time into a
single 3100 element (horizontal) CCD shift register.
The horizontal register transfers the charge to a single
output amplifier. The output amplifier is a two-stage
source follower that converts the photo-generated
charge to a voltage for each pixel
.
Figure 1 - Functional Block Diagram
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Revision No. 3.0
KAF-6303E
Performance Specification
1.3 Image
Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the sensor. These photon
induced electrons are collected locally by the formation of
potential wells at each photogate or pixel site. The
number of electrons collected is linearly dependent on
light level and exposure time and non-linearly dependent
on wavelength. When the pixel's capacity is reached,
excess electrons will leak into the adjacent pixels within
the same column. This is termed blooming. During the
integration period, the
V1 and
V2 register clocks are
held at a constant (low) level.
See Figure 5. - Timing Diagrams.
1.4 Charge
Transport
Referring again to Figure 5 - Timing Diagrams, the
integrated charge from each photogate is transported to
the output using a two step process. Each line (row) of
charge is first transported from the vertical CCD's to the
horizontal CCD register using the
V1 and
V2 register
clocks. The horizontal CCD is presented a new line on the
falling edge of
V2 while
H1 is held high. The
horizontal CCD's then transport each line, pixel by pixel,
to the output structure by alternately clocking the
H1
and
H2 pins in a complementary fashion. On each
falling edge of
H2 a new charge packet is transferred
onto a floating diffusion and sensed by the output
amplifier
1.5 Output
Structure
Charge presented to the floating diffusion (FD) is
converted into a voltage and current amplified in order
to drive off-chip loads. The resulting voltage change
seen at the output is linearly related to the amount of
charge placed on FD. Once the signal has been
sampled by the system electronics, the reset gate (
R) is
clocked to remove the signal and FD is reset to the
potential applied by Vrd. More signal at the floating
diffusion reduces the voltage seen at the output pin. In
order to activate the output structure, an off-chip load
must be added to the Vout pin of the device - see
Figure 4.
1.6
Dark Reference Pixels
Surrounding the peripheral of the device is a border of
light shielded pixels. This includes 6 leading and 10
trailing pixels on every line excluding dummy pixels.
There are also 4 full dark lines at the start of every
frame and 4 full dark lines at the end of each frame.
Under normal circumstances, these pixels do not
respond to light. However, dark reference pixels in
close proximity to an active pixel, or the outer bounds
of the chip (including the first two lines out), can
scavenge signal depending on light intensity and
wavelength and therefore will not represent the true
dark signal.
1.7 Dummy
Pixels
Within the horizontal shift register are 10 leading and 2
trailing additional shift phases which are not associated
with a column of pixels from the vertical register.
These pixels contain only horizontal shift register dark
current signal and do not respond to light. A few
leading dummy pixels may scavenge false signal
depending on operating conditions.
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Revision No. 3.0
KAF-6303E
Performance Specification
2.1 Package
Drawing
Figure 2 - Package Drawing
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Revision No. 3.0
KAF-6303E
Performance Specification
2.2 Pin
Description
Pin
Symbol
Description
Pin
Symbol
Description
1, 13, 14,
15, 26
Vsub
Substrate (Ground)
10
H1
Horizontal CCD Clock - Phase 1
2
Vout
Video Output
11
H2
Horizontal CCD Clock - Phase 2
3
Vdd
Amplifier Supply
16, 17,
22, 23
V1
Vertical CCD Clock - Phase 1
4
Vrd
Reset Drain
18, 19,
20, 21
V2
Vertical CCD Clock - Phase 2
5
R
Reset Clock
24
Vguard
Guard Ring
6
Vss
Amplifier Supply Return
25
Vog
Output Gate
7, 8, 9, 12
N/C
No connection (open pin)
Pin 1
2
3
4
5
6
7
8
9
10
11
12
13
Pixel 1,1
Vog
Vguard
V1
V1
V1
V2
V2
V2
V2
V1
Vsub
Vsub
Vsub
26
25
24
23
22
21
20
19
18
17
16
15
14
Vout
Vdd
Vrd
R
N/C
N/C
Vss
N/C
H1
H2
N/C
Vsub
Vsub
1
Figure 3 - Package Pin Designations
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Revision No. 3.0
KAF-6303E
Performance Specification
3.1
Absolute Maximum Ratings
Description Symbol
Min.
Max.
Units
Notes
Diode Pin Voltages
Vdiode
0
20
V
1, 2
Gate Pin Voltages - Type 1
Vgate1
-16
16
V
1, 3
Gate Pin Voltages - Type 2
Vgate2
0
16
V
1, 4
Inter-Gate Voltages
Vg-g 16 V 5
Output Bias Current
Iout
-10
mA
6
Output Load Capacitance
Cload
15
pF
6
Storage Temperature
T 0 70
o
C
Humidity
RH 5 90 % 7
Notes:
1. Referenced to pin Vsub.
2. Includes pins: Vrd, Vdd, Vss, Vout, Vguard.
3. Includes pins:
V1,
V2,
H1,
H2.
4. Includes pins:
R, Vog.
5. Voltage difference between overlapping gates. Includes:
V1 to
V2,
H1 to
H2,
V2 to
H1,
H2 to Vog.
6. Avoid shorting output pins to ground or any low impedance source during operation.
7. T=25
C. Excessive humidity will degrade MTTF.
CAUTION:
This device contains limited protection against Electrostatic Discharge (ESD). Devices should be handled
in accordance with strict ESD control procedures for Class 0 devices.
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Revision No. 3.0
KAF-6303E
Performance Specification
3.2
DC Operating Conditions
Description Symbol
Min.
Nom.
Max.
Units
Max DC Current
(mA)
Notes
Reset Drain
Vrd
10.5
11
11.5
V
0.01
Output Amplifier Return
Vss
1.5
2.0
2.5
V
0.45
Output Amplifier Supply
Vdd
14.5
15
15.5
V
Iout
Substrate Vsub
0
0
0
V
0.01
Output Gate
Vog
3.75
4.0
5.0
V
0.01
Guard Ring
Vguard
8.0
10.0
12.0
V
0.01
Video Output Current
Iout
-5
-10
mA
-
1
Notes:
1. An output load sink must be applied to Vout to activate output amplifier - see Figure below.
+15V
0.1uF
Vout
Buffered Output
1k
140
2N3904 or equivalent
~5ma
Figure 4 - Recommended Output Structure Load Diagram
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Revision No. 3.0
KAF-6303E
Performance Specification
3.3
AC Operating Condition
Description Symbol
Level
Min. Nom. Max. Units Effective
Capacitance
Notes
Vertical CCD Clock - Phase 1
V1
Low
High
-10.5
0.5
-10.0
1.0
-9.5
1.5
V
V
820 nF
(all
V1 pins)
Vertical CCD Clock - Phase 2
V2
Low
High
-10.5
0.5
-10.0
1.0
-9.5
1.5
V
V
820 nF
(all
V2 pins)
Horizontal CCD Clock - Phase 1
H1
Low
High
-6.0
4.0
-4.0
6.0
-3.5
6.5
V
V
400 pF
Horizontal CCD Clock - Phase 2
H2
Low
High
-6.0
4.0
-4.0
6.0
-3.5
6.5
V
V
400 pF
Reset Clock
R
Low
High
-4.0
3.5
-3.0
4.0
-2.0
5.0
V
V
10pF
Notes:
1. All pins draw less than 10uA DC current.
2. Capacitance values relative to VSUB.
3.4
AC Timing Conditions
Description Symbol
Min.
Nom.
Max.
Units
Notes
H1,
H2 Clock Frequency
f
H
4
15
MHz
1, 2, 3
V1,
V2 Clock Frequency
f
V
25
50
kHz
1, 2, 3
Pixel Period (1 Count)
t
e
67 250 ns
H1,
H2 Setup Time
t
HS
0.5 1 us
V1,
V2 Clock Pulse Width
t
V
10 20 us
2
Reset Clock Pulse Width
t
R
10 20 ns
4
Readout Time
t
readout
531 1719 ms
5
Integration Time
t
int
6
Line Time
tline
258.2 836
us
7
Notes:
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5-10% of clock period. Cross-over of register clocks should be between
40-60% of amplitude.
4.
R should be clocked continuously.
5.
t
readout
= ( 2056 * tline )
6. Integration time is user specified. Longer integration times will degrade noise performance.
7
. tline = ( 3* t
V
) + t
HS
+ ( 3100 * t
e
) + t
e
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Revision No. 3.0
KAF-6303E
Performance Specification
Frame Timing
tReadout
Line
1
2
2055
2056
1 Frame = 2056 Lines
V1
V2
H1
H2
tint
1 count
Pixel Timing Detail
R
H1
H2
Vout
t
R
Vsat
Vdark
Vsub
Vodc
te
Line Timing Detail
1 line
V1
V2
H1
H2
R
3100 counts
t
HS
te
t
V
t
V
Vpix
Line Content
Photoactive Pixels
Dark Reference Pixels
Dummy Pixels
1-10 11-16
16 - 3088
3089-3098 3099-3100
Vsat Saturated pixel video output signal
Vdark Video output signal in no light situation, not zero due to Jdark
Vpix Pixel video output signal level, more electrons =more negative*
Vodc Video level offset with respect to vsub
Vsub Analog Ground
* See Image Aquisition section (page 4)
Figure 5 - Timing Diagrams
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Revision No. 3.0
KAF-6303E
Performance Specification
4.1 Performance
Specifications
All values measured at 25
C, and nominal operating conditions. These parameters exclude defective pixels.
Description
Symbol
Min.
Nom.
Max.
Units
Notes
Saturation Signal
Vertical CCD capacity
Horizontal CCD capacity
Output Node capacity
Nsat
85000
170000
190000
100000
200000
220000
120000
240000
240000
electrons / pixel
1
Red Quantum Efficiency (
=650nm)
Green Quantum Efficiency (
=550nm)
Blue Quantum Efficiency (
=450nm)
Rr
Rg
Rb
52
42
32
65
52
40
75
62
48
%
%
%
Photoresponse Non-Linearity
PRNL
1
2
%
2
Photoresponse Non-Uniformity
PRNU
1
3
%
3
Dark Signal
Jdark
15
3.5
50
10
electrons / pixel / sec
pA/cm2
4
Dark Signal Doubling Temperature
5
6.3
7.5
o
C
Dark Signal Non-Uniformity
DSNU
15
50
electrons / pixel / sec
5
Dynamic Range
DR
70
74
dB
6
Charge Transfer Efficiency
CTE
0.99997
0.99999
Output Amplifier DC Offset
Vodc
9.5
10.5
11.5
V
7
Output Amplifier Bandwidth
f-3dB
45
Mhz
8
Output Amplifier Sensitivity
Vout/Ne~
9
10
11
uV/e~
Output Amplifier output Impedance
Zout
175
200
250
Ohms
Noise Floor
ne~
15
20
electrons
9
Notes:
1.
For pixel binning applications, electron capacity up to 330000 can be achieved with modified CCD inputs.
Each sensor may have to be optimized individually for these applications. Some performance parameters may be compromised
to achieve the largest signals.
2.
Worst case deviation from straight line fit, between 1% and 90% of Vsat.
3.
One Sigma deviation of a 128x128 sample when CCD illuminated uniformly.
4.
Average of all pixels with no illumination at 25
o
C.
5.
Average dark signal of any of 12 x 8 blocks within the sensor. (each block is 128 x 128 pixels)
6.
20log (Nsat / ne~) at nominal operating frequency and 25
o
C.
7.
Video level offset with respect to ground
8.
Last output amplifier stage only. Assumes 10pF off-chip load..
9.
Output noise at 25
o
C, nominal operating frequency, and tint = 0.
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Revision No. 3.0
KAF-6303E
Performance Specification
4.2
Typical Performance Characteristics
Spectral Response
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
400
500
600
700
800
900
1000
1100
Wavelength (nm)
Quantum Efficienc
y
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Revision No. 3.0
KAF-6303E
Performance Specification
4.3 Cosmetic
Classification
Defect tests performed at T=25
o
C
Class Point
Defects Cluster Defects Maximum
Cluster Size
Column Defects
Total
Zone A
Total
Zone A
Total
Zone A
C1
35
14
5
2
2 0
0
C2
90
45
36
18
5 0
0
3072,2048
1,1
3072,1
1,2048
1024,512
2048,512
2048,1536
1024,1536
Zone A
Center 1024 x 1024 Pixels
Point Defect
Dark: A pixel which deviates by more than 6% from
neighboring pixels when illuminated to 70% of saturation, OR
Bright: A Pixel with dark current > 10,000 e/pixel/sec at 25
C.
Cluster Defect
A grouping of not more than "Maximum Cluster Size" defects
Column Defect
A grouping of >5 contiguous point defects along a single
column, OR
A column containing a pixel with dark current >
30,000e/pixel/sec, OR A column that does not meet the CTE
specification for all exposures less than the specified Max sat.
signal level and greater than 2 Ke, OR
A pixel which loses more than 250 e under 2Ke illumination.
Neighboring pixels
The surrounding 128 x 128 pixels or
64 columns/rows.
Defect Separation
Column and cluster defects are separated by no less than two (2)
pixels in any direction (excluding single pixel defects).
Defect Region Exclusion Defect region excludes the outer two (2) rows and columns at
each side/end of the sensor.
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Revision No. 3.0
KAF-6303E
Performance Specification
5.1
Quality Assurance and Reliability
Quality Strategy: All image sensors will conform to the specifications stated in this document. This will be accomplished
through a combination of statistical process control and inspection at key points of the production process. Typical
specification limits are not guaranteed but provided as a design target. For further information refer to ISS Application Note
MTD/PS-0292, Quality and Reliability.
Replacement: All devices are warranted against failure in accordance with the terms of Terms of Sale. This does not include
failure due to mechanical and electrical causes defined as the liability of the customer below.
Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the specifications in this document
upon receipt by the customer.
Liability of the Customer: Damage from mechanical (scratches or breakage), electrostatic discharge (ESD) damage, or
other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor
by the customer, shall be the responsibility of the customer.
Cleanliness: Devices are shipped free of mobile contamination inside the package cavity. Immovable particles and scratches
that are within the imager pixel area and the corresponding cover glass region directly above the pixel sites are also not
allowed. The cover glass is highly susceptible to particles and other contamination. Touching the cover glass must be
avoided. See ISS Application Note MTD/PS-0237, Cover Glass Cleaning for Image Sensors, for further information.
ESD Precautions: Devices are shipped in static-safe containers and should only be handled at static-safe workstations. See
ISS Application Note MTD/PS-0224, Electrostatic Discharge Control, for handling recommendations.
Reliability: Information concerning the quality assurance and reliability testing procedures and results are available from the
Image Sensor Solutions and can be supplied upon request. For further information refer to ISS Application Note MTD/PS-
0292, Quality and Reliability.
Test Data Retention: Image sensors shall have an identifying number traceable to a test data file. Test data shall be kept for
a period of 2 years after date of delivery.
Mechanical: The device assembly drawing is provided as a reference. The device will conform to the published package
tolerances.
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Revision No. 3.0
KAF-6303E
Performance Specification
5.2 Ordering
Information
Address all inquiries and purchase orders to:
Image Sensor Solutions
Eastman Kodak Company
Rochester, New York 14650-2010
Phone: (585)
722-4385
Fax: (585)
477-4947
Web:
www.kodak.com/go/imagers
E-mail: ccd@kodak.com
Eastman Kodak reserves the right to change any information contained herein without notice. All information
furnished by Eastman Kodak is believed to be accurate.
WARNING: LIFE SUPPORT APPLICATIONS POLICY
Kodak image sensors are not authorized for and should not be used within Life Support Systems without
the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement of
defective components and does not cover injury or property or other consequential damages.
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Revision No. 3.0
KAF-6303E
Performance Specification
Revision Changes
Revision
Number
Description of Changes
0
Original formal version.
1
Added UV Enhancement class (Section 4.3).
Removed Appendix 1 Available Part Numbers.
Added Revision Changes.
2
Revised Class 1 cosmetic specification. (Page 13)
Removed UV Enhanced device. (Page 13)
Revised ESD classification to Class 0 HBM. This is not a change to the device, simply defining
more accurately using updated classifications. (Page 7)
3.0
Section 4.3 Cosmetic Specification:
Remove Class 3, Revise Class 2 as follows:
Point Defects: Total 90, Zone A 45
Clusters: Total 36, Zone A 18
Columns Total 0
Section 5.1, Quality and Reliability, updated.
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Revision No. 3.0
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