1
LT1124/LT1125
s
100% Tested Low Voltage Noise: 2.7nV/
Hz Typ
4.2nV/
Hz Max
s
Slew Rate: 4.5V/
s Typ
s
Gain Bandwidth Product: 12.5MHz Typ
s
Offset Voltage, Prime Grade: 70
V Max
Low Grade: 100
V Max
s
High Voltage Gain: 5 Million Min
s
Supply Current Per Amplifier: 2.75mA Max
s
Common Mode Rejection: 112dB Min
s
Power Supply Rejection: 116dB Min
s
Available in 8-Pin SO Package
Dual/Quad Low Noise,
High Speed Precision Op Amps
Instrumentation Amplifier with Shield Driver
Input Offset Voltage Distribution
(All Packages, LT1124 and LT1125)
The LT
1124 dual and LT1125 quad are high performance
op amps that offer higher gain, slew rate and bandwidth
than the industry standard OP-27 and competing OP-270/
OP-470 op amps. In addition, the LT1124/LT1125 have
lower I
B
and I
OS
than the OP-27; lower V
OS
and noise
than the OP-270/OP-470.
In the design, processing and testing of the device, par-
ticular attention has been paid to the optimization of the
entire distribution of several key parameters. Slew rate,
gain bandwidth and 1kHz noise are 100% tested for each
individual amplifier. Consequently, the specifications of
even the lowest cost grades (the LT1124C and the
LT1125C) have been spectacularly improved compared
to equivalent grades of competing amplifiers.
Power consumption of the LT1124 is one half of two
OP-27s. Low power and high performance in an 8-pin SO
package make the LT1124 a first choice for surface mounted
systems and where board space is restricted.
For a decompensated version of these devices, with three
times higher slew rate and bandwidth, please see the
LT1126/LT1127 data sheet.
s
Two and Three Op Amp Instrumentation Amplifiers
s
Low Noise Signal Processing
s
Active Filters
s
Microvolt Accuracy Threshold Detection
s
Strain Gauge Amplifiers
s
Direct Coupled Audio Gain Stages
s
Tape Head Preamplifiers
s
Infrared Detectors
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
Protected by U.S. patents 4,775,884 and 4,837,496.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
U
+
1/4
LT1125
1124/25 TA01
+
+
1/4
LT1125
1/4
LT1125
15V
15V
OUTPUT
1/4
LT1125
30k
1k
R
F
3.4k
R
G
100
R
F
3.4k
30k
1k
5
4
6
11
7
1
3
2
10
9
8
14
13
12
+
INPUT
GUARD
GUARD
= 30 (1 + R
F
/R
G
)
1000
= 170kHz
= 400kHz
= 3.8
V/ Hz AT OUTPUT
= 35
V
GAIN
POWER BW
SMALL-SIGNAL BW
NOISE
V
OS
R
G
100
+
INPUT OFFSET VOLTAGE (
V)
100
PERCENT OF UNITS
10
20
30
60
1124/25 TA02
60
20
V
S
=
15V
T
A
= 25
C
DUALS
QUADS
2316 UNITS
TESTED
758
200
100
20
0
2
LT1124/LT1125
LT1124AC/AI/AM
LT1124/C/I/M
LT1125AC/AM
LT1125/C/M
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
LT1124
20
70
25
100
V
LT1125
25
90
30
140
V
V
OS
Long Term Input Offset
0.3
0.3
V/Mo
Time
Voltage Stability
I
OS
Input Offset Current
LT1124
5
15
6
20
nA
LT1125
6
20
7
30
nA
LT1125CJ
LT1125ACN
LT1125CN
LT1125AMJ
LT1125MJ
Operating Temperature Range
LT1124AC/LT1124C
LT1125AC/LT1125C (Note 10) .......... 40
C to 85
C
LT1124AI/LT1124I ............................ 40
C to 85
C
LT1124AM/LT1124M
LT1125AM/LT1125M ...................... 55
C to 125
C
Supply Voltage .....................................................
22V
Input Voltages ......................... Equal to Supply Voltage
Output Short-Circuit Duration ......................... Indefinite
Differential Input Current (Note 6) .....................
25mA
Lead Temperature (Soldering, 10 sec)................. 300
C
Storage Temperature Range ................ 65
C to 150
C
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
LT1124CJ8
LT1124ACN8
LT1124CN8
LT1124AMJ8
LT1124MJ8
W
U
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
LT1125CS
ELECTRICAL C
C
HARA TERISTICS
ORDER PART
NUMBER
S8 PART MARKING
LT1124CS8
LT1124AIS8
LT1124IS8
1124
1124AI
1124I
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
IN A
OUT A
V
+
OUT B
+IN A
V
+IN B
IN B
S8 PACKAGE
8-LEAD PLASTIC SO
A
B
T
JMAX
= 140
C,
JA
= 190
C
NOTE: THIS PIN CONFIGURATION DIFFERS FROM THE
8-PIN PDIP CONFIGURATION. INSTEAD, IT FOLLOWS
THE INDUSTRY STANDARD LT1013DS8 SO PACKAGE
PIN LOCATIONS
T
JMAX
= 140
C,
JA
= 130
C
1
2
3
4
5
6
7
8
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC (WIDE) SO
16
15
14
13
12
11
10
9
OUT A
IN A
+IN A
V
+
+IN B
IN B
OUT B
NC
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
NC
B
A
C
D
1
2
3
4
8
7
6
5
TOP VIEW
OUT A
IN A
+IN A
V
V
+
OUT B
IN B
+IN B
N8 PACKAGE
8-LEAD PDIP
J8 PACKAGE
8-LEAD CERDIP
A
B
T
JMAX
= 160
C,
JA
= 100
C (J8)
T
JMAX
= 140
C,
JA
= 130
C (N8)
1
2
3
4
5
6
7
TOP VIEW
N PACKAGE
14-LEAD PDIP
J PACKAGE
14-LEAD CERDIP
14
13
12
11
10
9
8
OUT A
IN A
+IN A
V
+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
B
A
C
D
T
JMAX
= 160
C,
JA
= 80
C (J)
T
JMAX
= 140
C,
JA
= 110
C (N)
T
A
= 25
C, V
S
=
15V, unless otherwise noted.
3
LT1124/LT1125
The
q
denotes the specifications which apply over the 55
C
T
A
125
C temperature range, V
S
=
15V, unless otherwise noted.
LT1124AC/AI/AM
LT1124C/I/M
LT1125AC/AM
LT1125C/M
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
I
B
Input Bias Current
7
20
8
30
nA
e
n
Input Noise Voltage
0.1Hz to 10Hz (Notes 8, 9)
70
200
70
nV
P-P
Input Noise Voltage Density
f
O
= 10Hz (Note 4)
3.0
5.5
3.0
5.5
nV/
Hz
f
O
= 1000Hz (Note 3)
2.7
4.2
2.7
4.2
nV/
Hz
i
n
Input Noise Current Density
f
O
= 10Hz
1.3
1.3
pA/
Hz
f
O
= 1000Hz
0.3
0.3
pA/
Hz
V
CM
Input Voltage Range
12
12.8
12
12.8
V
CMRR
Common Mode Rejection Ratio
V
CM
=
12V
112
126
106
124
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4V to
18V
116
126
110
124
dB
A
VOL
Large-Signal Voltage Gain
R
L
10k, V
OUT
=
10V
5
17
3.0
15
V/
V
R
L
2k, V
OUT
=
10V
2
4
1.5
3
V/
V
V
OUT
Maximum Output Voltage Swing
R
L
2k
13
13.8
12.5
13.8
V
SR
Slew Rate
R
L
2k (Notes 3, 7)
3
4.5
2.7
4.5
V/
s
GBW
Gain Bandwidth Product
f
O
= 100kHz (Note 3)
9
12.5
8
12.5
MHz
Z
O
Open-Loop Output Resistance
V
OUT
= 0, I
OUT
= 0
75
75
I
S
Supply Current per Amplifier
2.3
2.75
2.3
2.75
mA
Channel Separation
f
10Hz (Note 9)
134
150
130
150
dB
V
OUT
=
10V, R
L
= 2k
ELECTRICAL C
C
HARA TERISTICS
T
A
= 25
C, V
S
=
15V, unless otherwise noted.
LT1124AM
LT1124M
LT1125AM
LT1125M
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
LT1124
q
50
170
60
250
V
LT1125
q
55
190
70
290
V
V
OS
Average Input Offset
(Note 5)
q
0.3
1.0
0.4
1.5
V/
C
Temp
Voltage Drift
I
OS
Input Offset Current
LT1124
q
18
45
20
60
nA
LT1125
q
18
55
20
70
nA
I
B
Input Bias Current
q
18
55
20
70
nA
V
CM
Input Voltage Range
q
11.3
12
11.3
12
V
CMRR
Common Mode Rejection Ratio
V
CM
=
11.3V
q
106
122
100
120
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4V to
18V
q
110
122
104
120
dB
A
VOL
Large-Signal Voltage Gain
R
L
10k, V
OUT
=
10V
q
3
10
2.0
10
V/
V
R
L
2k, V
OUT
=
10V
q
1
3
0.7
2
V/
V
V
OUT
Maximum Output Voltage Swing
R
L
2k
q
12.5
13.6
12
13.6
V
SR
Slew Rate
R
L
2k (Notes 3, 7)
q
2.3
3.8
2
3.8
V/
s
I
S
Supply Current per Amplifier
q
2.5
3.25
2.5
3.25
mA
4
LT1124/LT1125
Note 7: Slew rate is measured in A
V
= 1; input signal is
7.5V, output
measured at
2.5V.
Note 8: 0.1Hz to 10Hz noise can be inferred from the 10Hz noise voltage
density test. See the test circuit and frequency response curve for 0.1Hz to
10Hz tester in the Applications Information section of the LT1007 or
LT1028 data sheets.
Note 9: This parameter is guaranteed but not tested.
Note 10: The LT1124C/LT1125C and LT1124AC/LT1125AC are guaranteed
to meet specified performance from 0
C to 70
C and are designed,
characterized and expected to meet these extended temperature limits, but
are not tested at 40
C and 85
C. The LT1124AI and LT1124I are
guaranteed to meet the extended temperature limits.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers; i.e., out of 100 LT1125s (or 100
LT1124s) typically 240 op amps (or 120) will be better than the indicated
specification.
Note 3: This parameter is 100% tested for each individual amplifier.
Note 4: This parameter is sample tested only.
Note 5: This parameter is not 100% tested.
Note 6: The inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds
1.4V, the input current should be limited to 25mA.
ELECTRICAL C
C
HARA TERISTICS
The
q
denotes the specifications which apply over the 0
C
T
A
70
C
temperature range, V
S
=
15V, unless otherwise noted.
LT1124AC
LT1124C
LT1125AC
LT1125C
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
LT1124
q
35
120
45
170
V
LT1125
q
40
140
50
210
V
V
OS
Average Input Offset
(Note 5)
q
0.3
1
0.4
1.5
V/
C
Temp
Voltage Drift
I
OS
Input Offset Current
LT1124
q
6
25
7
35
nA
LT1125
q
7
35
8
45
nA
I
B
Input Bias Current
q
8
35
9
45
nA
V
CM
Input Voltage Range
q
11.5
12.4
11.5
12.4
V
CMRR
Common Mode Rejection Ratio
V
CM
=
11.5V
q
109
125
102
122
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4V to
18V
q
112
125
107
122
dB
A
VOL
Large-Signal Voltage Gain
R
L
10k, V
OUT
=
10V
q
4.0
15
2.5
14
V/
V
R
L
2k, V
OUT
=
10V
q
1.5
3.5
1.0
2.5
V/
V
V
OUT
Maximum Output Voltage Swing
R
L
2k
q
12.5
13.7
12
13.7
V
SR
Slew Rate
R
L
2k (Notes 3, 7)
q
2.6
4
2.4
4
V/
s
I
S
Supply Current per Amplifier
q
2.4
3
2.4
3
mA
The
q
denotes the specifications which apply over the 40
C
T
A
85
C temperature range, V
S
=
15V,
unless otherwise noted. (Note 10)
LT1124AC/AI
LT1124C/I
LT1125AC
LT1125C
SYMBOL
PARAMETER
CONDITIONS (Note 2)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
LT1124
q
40
140
50
200
V
LT1125
q
45
160
55
240
V
V
OS
Average Input Offset
(Note 5)
q
0.3
1
0.4
1.5
V/
C
Temp
Voltage Drift
I
OS
Input Offset Current
LT1124
q
15
40
17
55
nA
LT1125
q
15
50
17
65
nA
I
B
Input Bias Current
q
15
50
17
65
nA
V
CM
Input Voltage Range
q
11.4
12.2
11.4
12.2
V
CMRR
Common Mode Rejection Ratio
V
CM
=
11.4V
q
107
124
101
121
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4V to
18V
q
111
124
106
121
dB
A
VOL
Large-Signal Voltage Gain
R
L
10k, V
OUT
=
10V
q
3.5
12
2.2
12
V/
V
R
L
2k, V
OUT
=
10V
q
1.2
3.2
0.8
2.3
V/
V
V
OUT
Maximum Output Voltage Swing
R
L
2k
q
12.5
13.6
12
13.6
V
SR
Slew Rate
R
L
2k (Notes 3, 7)
q
2.4
3.9
2.1
3.9
V/
s
I
S
Supply Current per Amplifier
q
2.4
3.25
2.4
3.25
mA
5
LT1124/LT1125
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
0.1Hz to 10Hz Voltage Noise
0.01Hz to 1Hz Voltage Noise
Voltage Noise vs Frequency
Input Bias or Offset Current
Output Short-Circuit Current
Current Noise vs Frequency
vs Temperature
vs Time
Input Bias Current Over the
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Common Mode Range
vs Frequency
vs Frequency
TIME (SECONDS)
0
VOLTAGE NOISE (40nV/DIV)
2
6
8
10
1124/25 G01
4
TIME (SECONDS)
0
VOLTAGE NOISE (40nV/DIV)
20
60
80
100
1124/25 G02
40
FREQUENCY (Hz)
3
RMS VOL
T
AGE NOISE DENSITY (nV/ Hz)
10
30
100
0.1
10
100
1000
1124/25 G03
1
1.0
MAXIMUM
TYPICAL
V
S
=
15V
T
A
= 25
C
1/f CORNER
2.3Hz
FREQUENCY (Hz)
0.3
RMS CURRENT NOISE DENSITY (pA/ Hz)
1.0
3.0
10.0
10
1k
10k
1124 G04
0.1
100
V
S
=
15V
T
A
= 25
C
TYPICAL
MAXIMUM
1/f CORNER
100Hz
TEMPERATURE (
C)
75
0
INPUT BIAS OR OFFSET CURRENT (nA)
10
20
30
50
25
75
125
1124/25 G05
25
0
50
100
LT1124M/LT1125M
LT1124AM/LT1125AM
V
S
=
15V
TIME FROM OUTPUT SHORT TO GND (MINUTES)
0
0
20
40
50
2
3
4
LT1124 G06
1
V
S
=
15V
10
30
10
20
30
40
50
125
C
25
C
125
C
SHOR
T
-CIRCUIT CURRENT (mA)
SINKING
SOURCING
55
C
25
C
55
C
COMMON MODE INPUT VOLTAGE (V)
15
20
INPUT BIAS CURRENT (nA) 10
5
20
10
5
15
1124/25 G07
5
10
15
0
10
5
15
0
DEVICE WITH POSITIVE
INPUT CURRENT
DEVICE WITH NEGATIVE
INPUT CURRENT
V
S
=
15V
T
A
= 25
C
FREQUENCY (Hz)
80
COMMON MODE REJECTION RATIO (dB)
100
120
140
160
1k
100k
1M
10M
1124/25 G08
10k
60
40
20
0
T
A
= 25
C
V
S
=
15V
V
CM
=
10V
FREQUENCY (Hz)
1
0
POWER SUPPL
Y REJECTION RA
TIO (dB)
20
40
120
140
160
10
2
10
8
1124/25 G09
10
10
3
10
4
10
5
10
6
10
7
60
100
80
PSRR
+PSRR
T
A
= 25
C
6
LT1124/LT1125
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
Voltage Gain vs Frequency
Voltage Gain vs Temperature
Gain, Phase Shift vs Frequency
Offset Voltage Drift with
Input Offset Voltage Drift
Temperature of Representative
Distribution
Units
Supply Current vs Supply Voltage
Output Voltage Swing vs
Small-Signal Transient Response
Large-Signal Transient Response
Load Current
FREQUENCY (Hz)
0.01
20
VOL
T
AGE GAIN (dB)
20
140
180
1
100
10k
100M
1124/25 G10
60
100
1M
V
S
=
15V
T
A
= 25
C
TEMPERATURE (
C)
75
0
VOL
T
AGE GAIN (V/ V)
6
12
20
50
25
75
125
1124/25 G11
25
0
50
100
LT1124AM/LT1125AM
2
4
8
10
14
16
18
LT1124M/LT1125M
L
L
LT1124AM/LT1125AM
LT1124M/LT1125M
R = 10k
R = 2k
V = 15V
V = 10V
S
OUT
FREQUENCY (MHz)
0.1
10
VOL
T
AEG GAIN (dB)
0
30
40
50
1
10
100
1124/25 G12
10
20
GAIN
V
S
=
15V
T
A
= 25
C
C
L
= 10pF
PHASE SHIFT (DEGREES)
180
120
80
140
160
100
200
INPUT OFFSET VOLTAGE DRIFT (
V/
C)
0.8
PERCENT OF UNITS
10
20
30
0.4
0.8
1124/25 G13
0.4
0
N8
S8
J8
396 UNITS TESTED
200
100
96
V
S
=
15V
40
0
TEMPERATURE (
C)
50
50
OFFSET VOL
T
AGE ( V)
20
20
25
75
125
1124/25 G14
0
25
50
100
40
30
0
10
30
40
50
10
V
S
=
15V
SUPPLY VOLTAGE (V)
0
0
SUPPLY CURRENT PER AMPLIFIER (mA)
1
2
3
5
10
15
20
1124/25 G15
125
C
25
C
55
C
OUTPUT CURRENT (mA)
8
OUTPUT VOL
T
AGE SWING (V)
1.0
1.6
1.4
4
8
1124/25 G18
6
0
10
4 2
2
6
10
0.4
0.6
0.8
1.2
1.2
1.0
0.8
I
SINK
I
SOURCE
V
V
+
125
C
55
C
55
C
125
C
25
C
V
S
=
3V TO
18V
25
C
50mV
0
50mV
A
VCL
= +1
V
S
=
15V or
5V
C
L
= 15pF
1124/25 G16
10V
0
10V
A
VCL
= 1
V
S
=
15V
1124/25 G17
7
LT1124/LT1125
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
Common Mode Limit vs
Temperature
Channel Separation vs Frequency
Warm-Up Drift
Total Harmonic Distortion
Total Harmonic Distortion
Total Harmonic Distortion
and Noise vs Frequency for
and Noise vs Frequency for
and Noise vs Frequency for
Noninverting Gain
Inverting Gain
Competitive Devices
Total Harmonic Distortion and
Total Harmonic Distortion and
Intermodulation Distortion
Noise vs Output Amplitude for
Noise vs Output Amplitude for
(CCIF Method)* vs Frequency
Noninverting Gain
Inverting Gain
LT1124 and OP270
*See LT1115 data sheet for definition of CCIF testing
TEMPERATURE (
C)
60
0.5
COMMON MODE LIMIT (V)
REFERRED TO POWER SUPPL
Y
1.0
1.5
2.0
1.5
1.0
0.5
20
20
60
140
1124/25 G19
2.0
2.5
2.5
100
V
+
= 3V TO 18V
V
= 3V TO 18V
V
V
+
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE (%)
0.010
0.1
20
1k
10k
20k
1124/25 G22
100
0.001
0.0001
Z
L
= 2k/15pF
V
O
= 20V
P-P
A
V
= +1, +10, +100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
A
V
= +1
A
V
= +10
A
V
= +100
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE (%)
0.010
0.1
20
1k
10k
20k
1124/25 G23
100
0.001
0.0001
Z
L
= 2k/15pF
V
O
= 20Vp-p
A
V
= 1, 10, 100
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
A
V
= 1
A
V
= 10
A
V
= 100
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE (%)
0.010
0.1
20
1k
10k
20k
1124/25 G24
100
0.001
0.0001
Z
L
= 2k/15pF
V
O
= 20Vp-p
A
V
= 10
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
LT1124
OP270
OP27
OUTPUT SWING (V
P-P
)
TOTAL HARMONIC DISTORTION + NOISE (%)
0.1
1
0.3
10
30
1124/25 G25
1
0.010
0.0001
Z
L
= 2k/15pF
f
O
= 1kHz
A
V
= +1, +10, +100
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
A
V
= +1
A
V
= +10
A
V
= +100
0.001
OUTPUT SWING (Vp-p)
TOTAL HARMONIC DISTORTION + NOISE (%)
0.1
1
0.3
10
30
1124/25 G26
1
0.010
0.0001
Z
L
= 2k/15pF
f
O
= 1kHz
A
V
= 1, 10, 100
MEASUREMENT BANDWIDTH
= 10Hz TO 22kHz
A
V
= 1
A
V
= 10
A
V
= 100
0.001
FREQUENCY (Hz)
INTERMODULATION DISTORTION (IMD)(%)
3k
10k
20k
1124/25 G27
0.010
0.0001
Z
L
= 2k/15pF
f (IM) = 1kHz
f
O
= 13.5kHz
V
O
= 20Vp-p
A
V
= 10
MEASUREMENT BANDWIDTH
= 10Hz TO 80kHz
LT1124
0.001
OP270
FREQUENCY (Hz)
0
0
CHANNEL SEP
ARA
TION (dB)
20
60
80
120
160
180
100
10k
100k
10M
1124/25 G20
1k
1M
40
100
140
LIMITED BY
THERMAL INTERACTION
LIMITED BY PIN
TO PIN CAPACITANCE
V
S
=
15V
R
L
= 2k
V
OUT
= 7V
P-P
T
A
= 25
C
TIME AFTER POWER ON (MINUTES)
0
0
CHANGE IN OFFSET VOL
T
AGE (
V)
2
4
8
10
1
2
3
5
1124/25 G21
4
6
V
S
=
15V
T
A
= 25
C
SO PACKAGE
N, J PACKAGES
8
LT1124/LT1125
U
S
A
O
PPLICATI
W
U
U
I FOR ATIO
The LT1124 may be inserted directly into OP-270 sockets.
The LT1125 plugs into OP-470 sockets. Of course, all
standard dual and quad bipolar op amps can also be
replaced by these devices.
Matching Specifications
In many applications the performance of a system de-
pends on the matching between two op amps, rather than
the individual characteristics of the two devices. The three
op amp instrumentation amplifier configuration shown in
this data sheet is an example. Matching characteristics are
not 100% tested on the LT1124/LT1125.
Some specifications are guaranteed by definition. For
example, 70
V maximum offset voltage implies that mis-
match cannot be more than 140
V. 112dB (= 2.5
V/V)
CMRR means that worst case CMRR match is 106dB
Table 1. Expected Match
LT1124AC/AM
LT1124C/M
LT1125AC/AM
LT1125C/M
PARAMETER
50% YIELD
98% YIELD
50% YIELD
98% YIELD
UNITS
V
OS
Match,
V
OS
LT1124
20
110
30
130
V
LT1125
30
150
50
180
V
Temperature Coefficient Match
0.35
1.0
0.5
1.5
V/
C
Average Noninverting I
B
6
18
7
25
nA
Match of Noninverting I
B
7
22
8
30
nA
CMRR Match
126
115
123
112
dB
PSRR Match
127
118
127
114
dB
Figure 1. Test Circuit for Offset Voltage
and Offset Voltage Drift with Temperature
+
100
*
50k*
50k*
15V
15V
V
OUT
V
OUT
= 1000V
OS
*RESISTORS MUST HAVE LOW
THERMOELECTRIC POTENTIAL
1124/25 F01
(5
V/V). However, Table 1 can be used to estimate the
expected matching performance between the two sides of
the LT1124, and between amplifiers A and D, and between
amplifiers B and C of the LT1125.
Offset Voltage and Drift
Thermocouple effects, caused by temperature gradients
across dissimilar metals at the contacts to the input
terminals, can exceed the inherent drift of the amplifier
unless proper care is exercised. Air currents should be
minimized, package leads should be short, the two input
leads should be close together and maintained at the same
temperature.
The circuit shown in Figure 1 to measure offset voltage is
also used as the burn-in configuration for the LT1124/
LT1125, with the supply voltages increased to
16V.
9
LT1124/LT1125
High Speed Operation
When the feedback around the op amp is resistive (R
F
),
a pole will be created with R
F
, the source resistance and
capacitance (R
S
, C
S
), and the amplifier input capacitance
(C
IN
2pF). In low closed loop gain configurations and
with R
S
and R
F
in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(C
F
) in parallel with R
F
eliminates this problem (see
Figure 2). With R
S
(C
S
+ C
IN
) = R
F
C
F
, the effect of the
feedback pole is completely removed.
During the fast feedthrough-like portion of the output, the
input protection diodes effectively short the output to the
input and a current, limited only by the output short circuit
protection, will be drawn by the signal generator. With R
F
500
, the output is capable of handling the current
requirements (I
L
20mA at 10V) and the amplifier stays
in its active mode and a smooth transition will occur.
Noise Testing
Each individual amplifier is tested to 4.2nV/
Hz voltage
noise; i.e., for the LT1124 two tests, for the LT1125 four
tests are performed. Noise testing for competing multiple
op amps, if done at all, may be sample tested or tested
using the circuit shown in Figure 4.
e
n OUT
=
(e
nA
)
2
+ (e
nB
)
2
+ (e
nC
)
2
+ (e
nD
)
2
If the LT1125 were tested this way, the noise limit would
be
4 (4.2nV/
Hz)
2
= 8.4nV/
Hz. But is this an effective
screen? What if three of the four amplifiers are at a typical
2.7nV/
Hz, and the fourth one was contaminated and has
6.9nV/
Hz noise?
RMS Sum =
(2.7)
2
+ (2.7)
2
+ (2.7)
2
+ (6.9)
2
= 8.33nV/
Hz
This passes an 8.4nV/
Hz spec, yet one of the amplifiers
is 64% over the LT1125 spec limit. Clearly, for proper
noise measurement, the op amps have to be tested
individually.
U
S
A
O
PPLICATI
W
U
U
I FOR ATIO
+
1124/25 F03
OUTPUT
4.5V/
s
R
F
Figure 3. Unity-Gain Buffer Applications
1124/25 F04
+
A
+
B
+
C
+
D
OUT
Figure 4. Competing Quad Op Amp Noise Test Method
+
OUTPUT
1124/25 F02
R
S
C
S
R
F
C
F
C
IN
Figure 2. High Speed Operation
Unity Gain Buffer Applications
When R
F
100
and the input is driven with a fast, large
signal pulse (>1V), the output waveform will look as
shown in Figure 3.
10
LT1124/LT1125
U
S
A
O
PPLICATI
TYPICAL
Gain 1000 Amplifier with 0.01% Accuracy, DC to 1Hz
Gain Error vs Frequency Closed-Loop Gain = 1000
+
OUTPUT
1124/25 TA03
365
1%
INPUT
15k
5%
340k
1%
20k
TRIM
15V
1/2 LT1124
15V
RN60C FILM RESISTORS
THE HIGH GAIN AND WIDE BANDWIDTH OF THE LT1124/LT1125, IS USEFUL IN LOW
FREQUENCY HIGH CLOSED-LOOP GAIN AMPLIFIER APPLICATIONS. A TYPICAL
PRECISION OP AMP MAY HAVE AN OPEN-LOOP GAIN OF ONE MILLION WITH 500kHz
BANDWIDTH. AS THE GAIN ERROR PLOT SHOWS, THIS DEVICE IS CAPABLE OF 0.1%
AMPLIFYING ACCURACY UP TO 0.3Hz ONLY. EVEN INSTRUMENTATION RANGE
SIGNALS CAN VARY AT A FASTER RATE. THE LT1124/LT1125 "GAIN PRECISION --
BANDWIDTH PRODUCT" IS 75 TIMES HIGHER, AS SHOWN.
4
7 (SO-8)
1 (N8)
6 (S0-8)
8 (N8)
3
2
FREQUENCY (Hz)
GAIN ERROR (PERCENT)
0.01
0.1
1.0
0.1
10
100
1124/25 TA04
0.001
1
GAIN ERROR =
CLOSED-LOOP GAIN
OPEN-LOOP GAIN
TYPICAL
PRECISION
OP AMP
LT1124/LT1125
Table 2. Guaranteed Performance, V
S
=
15V, T
A
= 25
C, Low Cost Devices
LT1124CN8
PARAMETER/UNITS
LT1125CN
OP-27 GP
OP-270 GP
OP-470 GP
UNITS
Voltage Noise, 1kHz
4.2
4.5
5.0
nV/
Hz
100% Tested
Sample Tested
No Limit
Sample Tested
Slew Rate
2.7
1.7
1.7
1.4
V/
s
100% Tested
Not Tested
Gain Bandwidth Product
8.0
5.0
MHz
100% Tested
Not Tested
No Limit
No Limit
Offset Voltage
LT1124
100
100
250
V
LT1125
140
1000
V
Offset Current
LT1124
20
75
20
nA
LT1125
30
30
nA
Bias Current
30
80
60
60
nA
Supply Current/Amp
2.75
5.67
3.25
2.75
mA
Voltage Gain, R
L
= 2k
1.5
0.7
0.35
0.4
V/
V
Common Mode Rejection Ratio
106
100
90
100
dB
Power Supply Rejection Ratio
110
94
104
105
dB
SO-8 Package
Yes - LT1124
Yes
No
Table 2 summarizes the performance of the LT1124/
LT1125 compared to the low cost grades of alternate
approaches.
The comparison shows how the specs of the LT1124/
LT1125 not only stand up to the industry standard OP-27,
but in most cases are superior. Normally dual and quad
performance is degraded when compared to singles, for
the LT1124/LT1125 this is not the case.
PERFOR A CE CO PARISO
W
U
W
U
11
LT1124/LT1125
(1/2 LT1124, 1/4 LT1125)
S
W
A
W
CHE
TI
I
C D AGRA
1124/25 SS
200
A
100
A
200
6k
200
6k
50
200
A
V
100
A
V
+
OUTPUT
Q11
Q2B
Q1B
Q1A
INVERTING
INPUT ()
NONINVERTING
INPUT (+)
Q13
Q9
Q8
Q7
21k
21k
200pF
3.6k
3.6k
360
A
V
+
V
+
20pF
35pF
900
400
67pF
Q2A
570
A
Q25
20
20
V
Q12
Q3
Q15
Q16
Q22
Q23
Q24
Q17
Q19
Q20
Q18
Q26
Q30
Q28
Q27
Q29
Q10
12
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
J8 1197
0.014 0.026
(0.360 0.660)
0.200
(5.080)
MAX
0.015 0.060
(0.381 1.524)
0.125
3.175
MIN
0.100
0.010
(2.540
0.254)
0.300 BSC
(0.762 BSC)
0.008 0.018
(0.203 0.457)
0
15
0.005
(0.127)
MIN
0.405
(10.287)
MAX
0.220 0.310
(5.588 7.874)
1
2
3
4
8
7
6
5
0.025
(0.635)
RAD TYP
0.045 0.068
(1.143 1.727)
FULL LEAD
OPTION
0.023 0.045
(0.584 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
0.045 0.068
(1.143 1.727)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
N8 1197
0.100
0.010
(2.540
0.254)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130
0.005
(3.302
0.127)
0.020
(0.508)
MIN
0.018
0.003
(0.457
0.076)
0.125
(3.175)
MIN
1
2
3
4
8
7
6
5
0.255
0.015*
(6.477
0.381)
0.400*
(10.160)
MAX
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
13
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
1
2
3
4
0.150 0.157**
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
0.016 0.050
0.406 1.270
0.010 0.020
(0.254 0.508)
45
0
8
TYP
0.008 0.010
(0.203 0.254)
SO8 0996
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
0.004 0.010
(0.101 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
14
LT1124/LT1125
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
J14 1197
0.045 0.068
(1.143 1.727)
0.100
0.010
(2.540
0.254)
0.014 0.026
(0.360 0.660)
0.200
(5.080)
MAX
0.015 0.060
(0.381 1.524)
0.125
(3.175)
MIN
0.300 BSC
(0.762 BSC)
0.008 0.018
(0.203 0.457)
0
15
1
2
3
4
5
6
7
0.220 0.310
(5.588 7.874)
0.785
(19.939)
MAX
0.005
(0.127)
MIN
14
11
8
9
10
13
12
0.025
(0.635)
RAD TYP
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
N14 1197
0.020
(0.508)
MIN
0.125
(3.175)
MIN
0.130
0.005
(3.302
0.127)
0.045 0.065
(1.143 1.651)
0.065
(1.651)
TYP
0.018
0.003
(0.457
0.076)
0.100
0.010
(2.540
0.254)
0.005
(0.125)
MIN
0.255
0.015*
(6.477
0.381)
0.770*
(19.558)
MAX
3
1
2
4
5
6
7
8
9
10
11
12
13
14
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
15
LT1124/LT1125
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
S16 (WIDE) 0396
NOTE 1
0.398 0.413*
(10.109 10.490)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.394 0.419
(10.007 10.643)
0.037 0.045
(0.940 1.143)
0.004 0.012
(0.102 0.305)
0.093 0.104
(2.362 2.642)
0.050
(1.270)
TYP
0.014 0.019
(0.356 0.482)
TYP
0
8
TYP
NOTE 1
0.009 0.013
(0.229 0.330)
0.016 0.050
(0.406 1.270)
0.291 0.299**
(7.391 7.595)
45
0.010 0.029
(0.254 0.737)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
16
LT1124/LT1125
LINEAR TECHNOLOGY CORPORATION 1992
11245fas, sn11245 LT/TP 0699 REV A 2K PRINTED IN USA
Strain Gauge Signal Conditioner with Bridge Excitation
TYPICAL APPLICATIO
N
U
1124/25 TA05
+
+
+
LT1009
3
2
2.5V
5k
1/4
LT1125
1k
15V
15V
1
REFERENCE
OUTPUT
15V
15V
7
4
13
6
5
10k
ZERO
TRIM
301k*
350
BRIDGE
1
F
301k*
0V TO 10V
OUTPUT
499
*
GAIN
TRIM
50k
*RN60C FILM RESISTORS
1k
14
15V
15V
13
12
THE LT1124/LT1125 IS CAPABLE OF PROVIDING EXCITATION CURRENT DIRECTLY
TO BIAS THE 350
BRIDGE AT 5V WITH ONLY 5V ACROSS THE BRIDGE (AS OPPOSED
TO THE USUAL 10V) TOTAL POWER DISSIPATION AND BRIDGE WARM-UP DRIFT IS
REDUCED. THE BRIDGE OUTPUT SIGNAL IS HALVED, BUT THE LT1124/LT1125 CAN
AMPLIFY THE REDUCED SIGNAL ACCURATELY.
1/4
LT1125
1/4
LT1125
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1007
Single Low Noise, Precision Op Amp
2.5nV/
Hz 1kHz Voltage Noise
LT1028/LT1128
Single Low Noise, Precision Op Amps
0.85nV/
Hz Voltage Noise
LT1112/LT1114
Dual/Quad Precision Picoamp Input
250pA Max I
B
LT1113
Dual Low Noise JFET Op Amp
4.5nV/
Hz Voltage Noise, 10fA/
Hz Current Noise
LT1126/LT1127
Decompensated LT1124/LT1125
11V/
s Slew Rate
LT1169
Dual Low Noise JFET Op Amp
6nV/
Hz Voltage Noise, 1fA/
Hz Current Noise, 10pA Max I
B
LT1792
Single LT1113
4.2nV/
Hz Voltage Noise, 10fA/
Hz Current Noise
LT1793
Single LT1169
6nV/
Hz Voltage Noise, 1fA/
Hz Current Noise, 10pA Max I
B
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