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Электронный компонент: LT1169CN8

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1
LT1169
Dual Low Noise,
Picoampere Bias Current,
JFET Input Op Amp
D
U
ESCRIPTIO
S
FEATURE
The LT1169 achieves a new standard of excellence in noise
performance for a dual JFET op amp. For the first time low
voltage noise (6nV/
Hz) is simultaneously offered with
extremely low current noise (1fA/
Hz), providing the low-
est total noise for high impedance transducer applications.
Unlike most JFET op amps, the very low input bias current
(5pA Typ) is maintained over the entire common mode
range which results in an extremely high input resistance
(10
13
). When combined with a very low input capaci-
tance (1.5pF) an extremely high input impedance results,
making the LT1169 the first choice for amplifying low level
signals from high impedance transducers. The low input
capacitance also assures high gain linearity when buffering
AC signals from high impedance transducers.
The LT1169 is unconditionally stable for gains of 1 or more,
even with 1000pF capacitive loads. Other key features are
0.6mV V
OS
and a voltage gain over 4 million. Each indi-
vidual amplifier is 100% tested for voltage noise, slew rate
(4.2V/
s), and gain-bandwidth product (5.3MHz).
The LT1169 is offered in the S8 and N8 packages.
A full set of matching specifications are provided for
precision instrumentation amplifier front ends. Specifica-
tions at
5V supply operation are also provided. For an
even lower voltage noise please see the LT1113 data sheet.
s
Input Bias Current, Warmed Up: 20pA Max
s
100% Tested Low Voltage Noise: 8nV/
Hz Max
s
S8 and N8 Package Standard Pinout
s
Very Low Input Capacitance: 1.5pF
s
Voltage Gain: 1.2 Million Min
s
Offset Voltage: 2mV Max
s
Input Resistance: 10
13
s
Gain-Bandwidth Product: 5.3MHz Typ
s
Guaranteed Specifications with
5V Supplies
s
Guaranteed Matching Specifications
U
S
A
O
PPLICATI
s
Photocurrent Amplifiers
s
Hydrophone Amplifiers
s
High Sensitivity Piezoelectric Accelerometers
s
Low Voltage and Current Noise Instrumentation
Amplifier Front Ends
s
Two and Three Op Amp Instrumentation Amplifiers
s
Active Filters
U
A
O
PPLICATI
TYPICAL
, LTC and LT are registered trademarks of Linear Technology Corporation.
Low Noise Light Sensor with DC Servo
8
+V
V
4
LT1169 TA01
R1
1M
C1
2pF
7
5
6
+
1/2 LT1169
R2C2 > C1R1
C
D
= PARASITIC PHOTODIODE CAPACITANCE
V
OUT
= 100mV/
WATT FOR 200nm WAVE LENGTH
330mV/
WATT FOR 633nm WAVE LENGTH
R5
10k
D2
1N914
V
R4
1k
D1
1N914
R3
1k
1
3
2
+
1/2 LT1169
C2
0.022
F
HAMAMATSU
S1336-5BK
(908) 231-0960
V
OUT
R2
100k
C
D
2N3904
SOURCE RESISTANCE (
)
10k
1k
100
10
1
100
10k
100k
1M
1k
10M
LT1169 TA02
TOTAL 1kHz VOLTAGE NOISE DENSITY (nV/
Hz)
100M 1G
+
V
N
R
SOURCE
T
A
= 25C
V
S
= 15V
V
N
SOURCE
RESISTANCE
ONLY
V
N
=
(V
OP AMP
)
2
+ 4kTR
S
+ 2qI
B
R
S
2
1kHz Output Voltage Noise
Density vs Source Resistance
2
LT1169
ORDER PART
NUMBER
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
Supply Voltage
55
C to 105
C ...............................................
20V
105
C to 125
C ...............................................
16V
Differential Input Voltage ......................................
40V
Input Voltage (Equal to Supply Voltage) ...............
20V
Output Short-Circuit Duration......................... Indefinite
Operating Temperature Range ............... 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec) ................ 300
C
W
U
U
PACKAGE/ORDER I FOR ATIO
S8 PART MARKING
LT1169CN8
LT1169CS8
T
JMAX
= 150
C,
JA
= 80
C/W (N8)
T
JMAX
= 160
C,
JA
= 190
C/W (S8)
Consult factory for Industrial and Military grade parts.
V
S
=
15V, V
CM
= 0V, T
A
= 25
C, unless otherwise noted.
ELECTRICAL C
C
HARA TERISTICS
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
0.60
2.0
mV
V
S
=
5V
0.65
2.2
mV
I
OS
Input Offset Current
Warmed Up (Note 2)
2.5
15
pA
T
J
= 25
C (Note 5)
0.7
4
pA
I
B
Input Bias Current
Warmed Up (Note 2)
4.0
20
pA
T
J
= 25
C (Note 5)
1.5
5
pA
e
n
Input Noise Voltage
0.1Hz to 10Hz
2.4
V
P-P
Input Noise Voltage Density
f
O
= 10Hz
17
nV/
Hz
f
O
= 1000Hz
6
8
nV/
Hz
i
n
Input Noise Current Density
f
O
= 10Hz, f
O
= 1kHz (Note 3)
1
fA/
Hz
R
IN
Input Resistance
Differential Mode
10
14
Common Mode
V
CM
= 10V to 13V
10
13
C
IN
Input Capacitance
1.5
pF
V
S
=
5V
2.0
pF
V
CM
Input Voltage Range (Note 4)
13.0
13.5
V
10.5
11.0
V
CMRR
Common Mode Rejection Ratio
V
CM
= 10V to 13V
82
95
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4.5V to
20V
83
98
dB
A
VOL
Large-Signal Voltage Gain
V
O
=
12V, R
L
= 10k
1000
4500
V/mV
V
O
=
10V, R
L
= 1k
500
3000
V/mV
V
OUT
Output Voltage Swing
R
L
= 10k
13.0
13.8
V
R
L
= 1k
12.0
13.0
V
SR
Slew Rate
R
L
2k (Note 6)
2.4
4.2
V/
s
GBW
Gain-Bandwidth Product
f
O
= 100kHz
3.3
5.3
MHz
Channel Separation
f
O
= 10Hz, V
O
=
10V, R
L
= 1k
126
dB
I
S
Supply Current per Amplifier
5.3
6.50
mA
V
S
=
5V
5.3
6.45
mA
V
OS
Offset Voltage Match
0.8
3.5
mV
I
B
+
Noninverting Bias Current Match
Warmed Up (Note 2)
3
20
pA
CMRR
Common Mode Rejection Match
(Note 8)
78
94
dB
PSRR
Power Supply Rejection Match
(Note 8)
80
95
dB
1169
1
2
3
4
8
7
6
5
TOP VIEW
N8 PACKAGE
8-LEAD PDIP
B
A
OUT A
IN A
+IN A
V
V
+
OUT B
IN B
+IN B
S8 PACKAGE
8-LEAD PLASTIC SO
3
LT1169
ELECTRICAL C
C
HARA TERISTICS
V
S
=
15V, V
CM
= 0V, 0
C
T
A
70
C, (Note 9), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
q
0.7
3.2
mV
V
S
=
5V
q
0.8
3.4
mV
V
OS
Average Input Offset Voltage Drift
(Note 5)
q
20
50
V/
C
Temp
I
OS
Input Offset Current
q
10
50
pA
I
B
Input Bias Current
q
180
400
pA
V
CM
Input Voltage Range
q
12.9
13.4
V
q
10.0
10.8
V
CMRR
Common Mode Rejection Ratio
V
CM
= 10V to 12.9V
q
79
94
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4.5V to
20V
q
81
97
dB
A
VOL
Large-Signal Voltage Gain
V
O
=
12V, R
L
= 10k
q
800
3400
V/mV
V
O
=
10V, R
L
= 1k
q
400
2400
V/mV
V
OUT
Output Voltage Swing
R
L
= 10k
q
12.5
13.5
V
R
L
= 1k
q
11.5
12.7
V
SR
Slew Rate
R
L
2k
(Note 6)
q
1.9
4
V/
s
GBW
Gain-Bandwidth Product
f
O
= 100kHz
q
3
4.2
MHz
I
S
Supply Current per Amplifier
q
5.3
6.55
mA
V
S
=
5V
q
5.3
6.50
mA
V
OS
Offset Voltage Match
q
1.5
5
mV
I
B
+
Noninverting Bias Current Match
q
5.5
50
pA
CMRR
Common Mode Rejection Match
(Note 8)
q
74
93
dB
PSRR
Power Supply Rejection Match
(Note 8)
q
77
93
dB
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
q
0.8
3.8
mV
V
S
=
5V
q
0.9
4.0
mV
V
OS
Average Input Offset Voltage Drift
q
20
50
V/
C
Temp
I
OS
Input Offset Current
q
30
200
pA
I
B
Input Bias Current
q
320
1200
pA
V
CM
Input Voltage Range
q
12.6
13.0
V
q
10.0
10.5
V
CMRR
Common Mode Rejection Ratio
V
CM
= 10V to 12.6V
q
78
93
dB
PSRR
Power Supply Rejection Ratio
V
S
=
4.5V to
20V
q
79
96
dB
A
VOL
Large-Signal Voltage Gain
V
O
=
12V, R
L
= 10k
q
750
3000
V/mV
V
O
=
10V, R
L
= 1k
q
300
2000
V/mV
V
OUT
Output Voltage Swing
R
L
= 10k
q
12.5
12.5
V
R
L
= 1k
q
11.3
12.0
V
SR
Slew Rate
R
L
2k
q
1.8
3.8
V/
s
GBW
Gain-Bandwidth Product
f
O
= 100kHz
q
2.7
4
MHz
I
S
Supply Current per Amplifier
q
5.30
6.55
mA
V
S
=
5V
q
5.25
6.50
mA
V
S
=
15V, V
CM
= 0V, 40
C
T
A
85
C, (Note 7), unless otherwise noted.
4
LT1169
ELECTRICAL C
C
HARA TERISTICS
V
S
=
15V, V
CM
= 0V, 40
C
T
A
85
C, (Note 7), unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 1)
MIN
TYP
MAX
UNITS
V
OS
Offset Voltage Match
q
1.8
6
mV
I
B
+
Noninverting Bias Current Match
q
10
180
pA
CMRR
Common Mode Rejection Match
(Note 8)
q
73
93
dB
PSRR
Power Supply Rejection Match
(Note 8)
q
75
92
dB
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op
amps) typically 120 op amps will be better than the indicated specification.
Note 2: I
B
and I
OS
readings are extrapolated to a warmed-up temperature
from 25
C measurements and 45
C characterization data.
Note 3: Current noise is calculated from the formula:
i
n
= (2qI
B
)
1/2
where q = 1.6
10
19
coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 4: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.8mV.
Note 5: This parameter is not 100% tested.
Note 6: Slew rate is measured in A
V
= 1; input signal is
7.5V, output
measured at
2.5V.
Note 7: The LT1169 is designed, characterized and expected to meet these
extended temperature limits, but is not tested at 40
C and 85
C.
Guaranteed I grade parts are available; consult factory.
Note 8:
CMRR and
PSRR are defined as follows:
(1) CMRR and PSRR are measured in
V/V on the individual
amplifiers.
(2) The difference is calculated between the matching sides in
V/V.
(3) The result is converted to dB.
Note 9: The LT1169 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed-up chip
temperature can be 10
C to 50
C higher than the ambient temperature.
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
Voltage Noise vs Frequency
0.1Hz to 10Hz Voltage Noise
TIME (SEC)
VOLTAGE NOISE (1
V/DIV)
2
4
6
8
LT1169 TPC01
10
0
FREQUENCY (Hz)
1
10
1
10
100
100
1k
10k
LT1169 TPC03
RMS VOLTAGE NOISE (nV/
Hz)
T
A
= 25C
V
S
= 15V
1/f CORNER
60Hz
TYPICAL
INPUT VOLTAGE NOISE (nV/
Hz)
4.2
PERCENT OF UNITS (%)
30
40
50
7.4
LT1169 TPC02
20
10
0
5.0
5.8
6.6
4.6
7.8
5.4
6.2
7.0
8.2
T
A
= 25
C
V
S
=
15V
510 OP AMPS TESTED
1kHz Input Noise Voltage
Distribution
5
LT1169
C
C
HARA TERISTICS
U
W
A
TYPICAL PERFOR
CE
Input Bias and Offset Currents
Over the Common Mode Range
Input Bias and Offset Currents
vs Chip Temperature
TEMPERATURE (C)
75
VOLTAGE NOISE (AT 1kHz) (nV/
Hz)
6
7
8
LT1169 TPC04
5
4
2
0
50
100
3
10
9
50 25
25
75
125
V
S
= 15V
Voltage Noise vs Chip Temperature
TEMPERATURE (C)
0
INPUT BIAS AND OFFSET CURRENTS (A)
300p
100p
3n
1n
30n
10n
100
LT1169 TPC05*
30p
10p
3p
1p
0.3p
25
50
75
125
V
S
= 15V
V
CM
= 10 TO 13V
BIAS
CURRENT
OFFSET
CURRENT
FREQUENCY (Hz)
10
0
POWER SUPPLY REJECTION RATIO (dB)
20
40
60
80
120
100
1k
10k
100k
LT1169 TPC09
1M
10M
100
T
A
= 25C
+PSRR
PSRR
Voltage Gain vs Frequency
FREQUENCY (Hz)
0.01
VOLTAGE GAIN (dB)
100
140
180
1M
LT1169 TPC10
60
20
20
1
100
10k
100M
T
A
= 25C
V
S
= 15V
CHIP TEMPERATURE (C)
75
10
9
8
7
6
5
4
3
2
1
0
25
50
75
LT1169 TPC11
50
25
100 125
0
V
S
= 15V
V
O
= 10V, R
L
= 1k
V
O
= 12V, R
L
= 10k
VOLTAGE GAIN (V/
V)
R
L
=10k
R
L
= 1k
Voltage Gain vs Chip Temperature
FREQUENCY (MHz)
0.1
10
VOLTAGE GAIN (dB)
PHASE SHIFT (DEG)
30
40
50
1
10
100
LT1169 TPC12
20
10
0
180
100
80
60
120
140
160
T
A
= 25C
V
S
= 15V
C
L
= 10pF
PHASE
GAIN
Gain and Phase Shift
vs Frequency
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency
TEMPERATURE (
C)
60
COMMON MODE LIMIT (V)
REFERRED TO POWER SUPPLY
V
+
0
0.5
1.0
1.5
2.0
100
LT1169 TPC07
3.0
2.0
1.5
2.5
V
+1.0
20
20
60
140
V
+
= 5V TO 20V
V
= 5V TO 20V
FREQUENCY (Hz)
COMMON MODE REJECTION RATIO (dB)
120
100
80
60
40
20
0
1k
100k
1M
10M
LT1169 TPC08
10k
T
A
= 25
C
V
S
=
15V
Common Mode Limit
vs Temperature
COMMON MODE RANGE (V)
15
10
INPUT BIAS AND OFFSET CURRENTS (pA)
6
4
2
0
2
4
10
5
0
5
LT1169 TPC06
10
6
8
10
8
15
T
A
= 25
C
V
S
=
15V
BIAS CURRENT
OFFSET CURRENT