1
LTC1250
Very Low Noise
Zero-Drift Bridge Amplifier
s
Electronic Scales
s
Strain Gauge Amplifiers
s
Thermocouple Amplifiers
s
High Resolution Data Acquisition
s
Low Noise Transducers
s
Instrumentation Amplifiers
U
S
A
O
PPLICATI
s
Very Low Noise: 0.75
V
P-P
Typ, 0.1Hz to 10Hz
s
DC to 1Hz Noise Lower Than OP-07
s
Full Output Swing into 1k Load
s
Offset Voltage: 10
V Max
s
Offset Voltage Drift: 50nV/
C Max
s
Common-Mode Rejection Ratio: 110dB Min
s
Power Supply Rejection Ratio: 115dB Min
s
No External Components Required
s
Pin-Compatible with Standard 8-Pin Op Amps
S
FEATURE
D
U
ESCRIPTIO
The LTC
1250 is a high performance, very low noise zero-
drift operational amplifier. The LTC1250's combination of
low front-end noise and DC precision makes it ideal for use
with low impedance bridge transducers. The LTC1250
features typical input noise of 0.75
V
P-P
from 0.1Hz to
10Hz, and 0.2
V
P-P
from 0.1Hz to 1Hz. The LTC1250 has
DC to 1Hz noise of 0.35
V
P-P
, surpassing that of low noise
bipolar parts including the OP-07, OP-77, and LT1012.
The LTC1250 uses the industry-standard single op amp
pinout, and requires no external components or nulling
signals, allowing it to be a plug-in replacement for bipolar
op amps.
The LTC1250 incorporates an improved output stage
capable of driving 4.3V into a 1k load with a single 5V
supply; it will swing
4.9V into 5k with
5V supplies. The
input common mode range includes ground with single
power supply voltages above 12V. Supply current is 3mA
with a
5V supply, and overload recovery times from
positive and negative saturation are 0.5ms and 1.5ms,
respectively. The internal nulling clock is set at 5kHz for
optimum low frequency noise and offset drift; no external
connections are necessary.
The LTC1250 is available in standard 8-pin ceramic and
plastic DIPs, as well as an 8-pin SOIC package.
Input Referred Noise 0.1Hz to 10Hz
TIME (s)
0
V
1
2
8
LT1250 TA02
0
1
2
2
4
6
10
V
S
= 5V
A
V
= 10k
Differential Bridge Amplifier
+
5V
5V
1000pF
18.2k
1000pF
18.2k
7
6
4
3
2
5V
0.1
F
5V
A
V
= 100
1250 TA01
350
STRAIN
GAUGE
50
GAIN
TRIM
LTC1250
U
A
O
PPLICATI
TYPICAL
and LTC are registered trademarks and LT is a trademark of Linear Technology Corporation.
2
LTC1250
W
U
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PACKAGE/ORDER I FOR ATIO
A
U
G
W
A
W
U
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A
R
BSOLUTE
XI
TI
S
ORDER PART
NUMBER
1
2
3
4
8
7
6
5
TOP VIEW
NC
IN
+IN
V
NC
V
+
OUT
NC
N8 PACKAGE
8-LEAD PLASTIC DIP
J8 PACKAGE
8-LEAD CERAMIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
Total Supply Voltage (V
+
to V
) ............................. 18V
Input Voltage ........................ (V
+
+ 0.3V) to (V
0.3V)
Output Short Circuit Duration ......................... Indefinite
Operating Temperature Range
LTC1250M..................................... 55
C to 125
C
LTC1250C .......................................... 0
C TO 70
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec.) ................ 300
C
LTC1250MJ8
LTC1250CJ8
LTC1250CN8
LTC1250CS8
T
JMAX
= 150
C,
JA
= 100
CW (J8)
T
JMAX
= 110
C,
JA
= 130
CW (N8)
T
JMAX
= 110
C,
JA
= 200
CW (S8)
S8 PART MARKING
ELECTRICAL C
C
HARA TERISTICS
LTC1250M
LTC1250C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
T
A
= 25
C (Note 1)
5
10
5
10
V
V
OS
Average Input Offset Drift
(Note 1)
q
0.01
0.05
0.01
0.05
V/
C
Long Term Offset Drift
50
50
nV/
Mo
e
n
Input Noise Voltage (Note 2)
T
A
= 25
C, 0.1Hz to 10Hz
0.75
1.0
0.75
1.0
V
P-P
T
A
= 25
C, 0.1Hz to 1Hz
0.2
0.2
V
P-P
i
n
Input Noise Current
f = 10Hz
4.0
4.0
fA/
Hz
I
B
Input Bias Current
T
A
= 25
C (Note 3)
50
150
50
200
pA
q
950
450
pA
I
OS
Input Offset Current
T
A
= 25
C (Note 3)
100
300
100
400
pA
q
500
500
pA
CMRR
Common-Mode Rejection Ratio
V
CM
= 4V to 3V
q
110
130
110
130
dB
PSRR
Power Supply Rejection Ratio
V
S
=
2.375V to
8V
q
115
130
115
130
dB
A
VOL
Large-Signal Voltage Gain
R
L
= 10k, V
OUT
=
4V
q
125
170
125
170
dB
Maximum Output Voltage Swing
R
L
= 1k
q
4.0 4.3/4.7
4.0 4.3 /4.7
V
R
L
= 100k
4.92
4.95
V
SR
Slew Rate
R
L
= 10k, C
L
= 50pF
10
10
V/
s
GBW
Gain-Bandwidth Product
1.5
1.5
MHz
I
S
Supply Current
No Load, T
A
= 25
C
3.0
4.0
3.0
4.0
mA
q
7.0
5.0
mA
f
S
Internal Sampling Frequency
T
A
= 25
C
4.75
4.75
kHz
V
IN
=
5V, T
A
= Operating Temperature Range, unless otherwise noted.
LTC1250M
LTC1250C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage
T
A
= 25
C (Note 1)
2
5
2
5
V
V
OS
Average Input Offset Drift
(Note 1)
q
0.01
0.05
0.01
0.05
V/
C
e
n
Input Noise Voltage (Note 2)
T
A
= 25
C, 0.1Hz to 10Hz
1.0
1.0
V
P-P
T
A
= 25
C, 0.1Hz to 1Hz
0.3
0.3
V
P-P
I
B
Input Bias Current
T
A
= 25
C (Note 3)
20
100
20
100
pA
I
OS
Input Offset Current
T
A
= 25
C (Note 3)
40
200
40
200
pA
V
IN
= 5V, T
A
= Operating Temperature Range, unless otherwise noted.
1250
3
LTC1250
ELECTRICAL C
C
HARA TERISTICS
LTC1250M
LTC1250C
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Maximum Output Voltage Swing
R
L
= 1k
4.0
4.3
4.0
4.3
V
R
L
= 100k
4.95
4.95
V
I
S
Supply Current
T
A
= 25
C
1.8
2.5
1.8
2.5
mA
f
S
Sampling Frequency
T
A
= 25
C
3
3
kHz
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: These parametes are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels during automated testing.
Note 2: 0.1Hz to 10Hz noise is specified DC coupled in a 10s window;
0.1Hz to 1Hz noise is specified in a 100s window with an RC high-pass
V
IN
= 5V, T
A
= Operating Temperature Range, unless otherwise noted.
filter at 0.1Hz. The LTC1250 is sample tested for noise; for 100% tested
parts contact LTC Marketing Dept.
Note 3: At T
0
C these parameters are guaranteed by design and not
tested.
C
C
HARA TERISTICS
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TYPICAL PERFOR
CE
Sampling Frequency vs Supply
Voltage
TOTAL SUPPLY VOLTAGE, V
+
TO V
(V)
4
0
INPUT NOISE (
V
P-P
)
0.2
0.4
0.6
0.8
6
8
10
12
LTC1250 G01
1.0
1.2
1.4
1.6
14
16
T
A
= 25C
0.1Hz TO 10Hz
0.1Hz TO 1Hz
TOTAL SUPPLY VOLTAGE, V
+
TO V
(V)
4
0
SUPPLY CURRENT (mA)
0.5
1.0
1.5
2.0
6
8
10
12
LTC1250 G02
2.5
3.0
3.5
4.0
14
16
T
A
= 25C
Supply Current vs Supply Voltage
Input Noise vs Supply Voltage
TEMPERATURE (C)
50
SAMPLING FREQUENCY (kHz)
4
5
6
25
LTC1250 G06
3
2
25
0
50
1
0
8
7
75
100
150
V
S
= 5V
Sampling Frequency vs
Temperature
TEMPERATURE (C)
50
2.0
SUPPLY CURRENT (mA)
3.0
4.5
0
50
75
LTC1250 G05
2.5
4.0
3.5
25
25
100
125
V
S
= 5V
Supply Current vs Temperature
Input Noise vs Temperature
TEMPERATURE (C)
50
INPUT NOISE (
V
P-P
)
0.8
1.0
1.2
25
75
LTC1250 G04
0.6
0.4
25
0
50
100
125
0.2
0
V
S
= 5V
0.1Hz TO 10Hz
0.1Hz TO 1Hz
TOTAL SUPPLY VOLTAGE, V
+
TO V
(V)
4
2
SAMPLING FREQUENCY (kHz)
3
4
6
8
10
12
LTC1250 G03
5
6
14
16
T
A
= 25C
4
LTC1250
C
C
HARA TERISTICS
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TYPICAL PERFOR
CE
Voltage Noise vs Frequency
FREQUENCY (Hz)
20
VOLTAGE NOISE (nV/
Hz)
30
40
50
80
1
100
1k
10k
LTC1250 G11
0
10
70
60
10
V
S
= 5V
R
S
= 10
FREQUENCY (Hz)
0
GAIN (dB)
20
40
60
100
1k
100k
1M
10M
LTC1250 G10
20
10k
80
0
PHASE MARGIN (DEG)
20
40
60
100
20
80
GAIN
PHASE:
R
L
= 1k
PHASE:
R
L
= 100k
V
S
= 5V OR
SINGLE 5V
T
A
= 25C
C
L
= 100pF
TEMPERATURE (C)
25
10
100
1000
100
75
LTC1250 G14
50
125
BIAS CURRENT (
|
pA
|
)
50
0
25
V
S
= 5V
FREQUENCY (Hz)
20
CMRR (dB)
40
80
120
140
1
100
1k
100k
LTC1250 G12
0
10
10k
60
100
V
S
= 5V
V
CM
= 1V
RMS
Common-Mode Rejection Ratio
vs Frequency
SUPPLY VOLTAGE (V)
2
8
INPUT COMMON MODE RANGE (V)
6
4
2
0
3
4
5
6
LTC1250 G07
2
4
6
8
7
8
T
A
= 25C
0.2
0
0
5
INPUT (V)
500
s/DIV
A
V
= 100, R
L
= 100k, C
L
= 50pF, V
S
=
5V
OUTPUT (V)
Overload Recovery
2V/DIV
1
s/DIV
A
V
= 1, R
L
= 100k, C
L
= 50pF, V
S
=
5V
Transient Response
LOAD RESISTANCE (k
)
0
OUTPUT SWING (
V)
6
8
10
8
LTC1250 G08
4
2
0
2
4
6
10
1
3
5
7
9
1
3
5
7
9
R
L
TO GND
V
S
= 8V
V
S
= 5V
V
S
= 2.5V
NEGATIVE SWING
POSITIVE SWING
Gain/Phase vs Frequency
Common-Mode Input Range
vs Supply Voltage
Output Swing vs Load
Resistance, Dual Supplies
Output Voltage Swing vs Load
Resistance, Single Supply
LOAD RESISTANCE (k
)
0
0
OUTPUT SWING (V)
4
6
8
18
12
2
4
5
9
LTC1250 G09
2
14
16
10
1
3
6
7
8
V
S
= 16V
V
S
= 10V
V
S
= 5V
10
V
= GND
R
L
TO GND
Bias Current (Magnitude) vs
Temperature
5
LTC1250
C
C
HARA TERISTICS
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TYPICAL PERFOR
CE
Output Swing vs Output Current,
5V Supply
Short-Circuit Current
vs Temperature
Output Swing vs Output Current,
Single 5V Supply
TEST CIRCUITS
Offset Test Circuit
+
5V
100pF
100k
7
6
4
3
2
5V
OUTPUT
1250 TC01
LTC1250
10
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Input Noise
The LTC1250, like all CMOS amplifiers, exhibits two types
of low frequency noise: thermal noise and 1/f noise. The
LTC1250 uses several design modifications to minimize
these noise sources. Thermal noise is minimized by rais-
ing the g
M
of the front-end transistors by running them at
high bias levels and using large transistor geometries. 1/f
noise is combated by optimizing the zero-drift nulling loop
to run at twice the 1/f corner frequency, allowing it to
reduce the inherently high CMOS 1/f noise to near thermal
levels at low frequencies. The resultant noise spectrum is
quite low at frequencies below the internal 5kHz clock
Figure 1. Voltage Noise vs Frequency
FREQUENCY (Hz)
20
VOLTAGE NOISE (nV/
Hz)
30
40
50
80
0.01
1
LTC1250 F01
0
0.1
70
60
10
V
S
= 5V
R
S
= 10
LTC1250
OP-07
OP-27
OUTPUT CURRENT (mA)
0.01
1
OUTPUT VOLTAGE (V)
0
1
2
3
0.1
1
10
LTC1250 G16
2
3
4
5
4
5
V
S
= 5V
OUTPUT CURRENT (mA)
0.01
2
OUTPUT VOLTAGE (V)
3
4
5
0.1
1
10
LTC1250 G17
1
0
6
V
S
= SINGLE 5V
TEMPERATURE (C)
50
0
10
20
25
LTC1250 G18
10
20
25
0
50
30
40
40
75
100
125
SHORT-CIRCUIT CURRENT (mA)
30
V
S
= 15V
V
OUT
= V
V
OUT
= V
+
DC to 10Hz Noise Test Circuit
(for DC to 1Hz Multiply All Capacitor Values by 10)
100pF
100k
OUTPUT
1250 TC02
+
5V
7
6
4
3
2
5V
LTC1250
10
+
7
5
6
0.02
F
800k
+
3
2
800k
800k
0.04
F
0.01
F
1/2
LT1057
5V
8
1
4
5V
1/2
LT1057
6
LTC1250
where A
V
= closed-loop gain. Note that C
F
is not dependent
on the value of R
F
. Circuits with higher gain (A
V
> 50) or
low loop impedance should not require C
F
for stability.
frequency, approaching the best bipolar op amps at 10Hz
and surpassing them below 1Hz (Figure 1). All this is
accomplished in an industry-standard pinout; the LTC1250
requires no external capacitors, no nulling or clock sig-
nals, and conforms to industry-standard 8-pin DIP and 8-
pin SOIC packages.
Input Capacitance and Compensation
The large input transistors create a parasitic 55pF capaci-
tance from each input to V
+
. This input capacitance will
react with the external feedback resistors to form a pole
which can affect amplifier stability. In low gain, high
impedance configurations, the pole can land below the
unity-gain frequency of the feedback network and degrade
phase margin, causing ringing, oscillation, and other
unpleasantness. This is true of any op amp, however, the
55pF capacitance at the LTC1250's inputs can affect
stability with a feedback network impedance as low as
1.9k. This effect can be eliminated by adding a capacitor
across the feedback resistor, adding a zero which cancels
the input pole (Figure 2). The value of this capacitor should
be:
U
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PPLICATI
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fully cancel the 1/f noise spectrum and the low frequency
noise of the part will rise. If the loop is underdamped (large
R
F
, no C
F
) it will ring for more than 150
s and the noise
and offset will suffer.
The solution is to add C
F
as above but beware! Too large
a value of C
F
will overdamp the loop, again preventing it
from reaching a final value by the 150
s deadline. This
condition doesn't affect the LTC1250's offset or output
stability, but 1/f noise begins to rise. As a rule of thumb,
the R
F
C
F
feedback pole should be
7kHz (1/150
s, the
frequency at which the loop settles) for best 1/f perfor-
mance; values between 100pF and 500pF work well with
feedback resistors below 100k. This ensures adequate
gain at 7kHz for the LTC1250 to properly null. High value
feedback resistors (above 1M) may require experimenta-
tion to find the correct value because parasitics, both in
the LTC1250 and on the PC board, play an increasing role.
Low value resistors (below 5k) may not require a capaci-
tor at all.
Input Bias Current
The inputs of the LTC1250, like all zero-drift op amps,
draw only small switching spikes of AC bias current; DC
leakage current is negligible except at very high tempera-
tures. The large front-end transistors cause switching
spikes 3 to 4 times greater than standard zero-drift op
amps: the
50pA bias current spec is still many times
better than most bipolar parts. The spikes don't match
from one input pin to the other, and are sometimes (but
not always) of opposite polarity. As a result, matching the
impedances at the inputs (Figure 3) will not cancel the bias
current, and may cause additional errors. Don't do it.
+
C
F
R
IN
1250 F02
LTC1250
R
F
C
P
Figure 2. C
F
Cancels Phase Shift Due to Parasitic C
P
Larger values of C
F
, commonly used in band-limited DC
circuits, may actually increase low frequency noise. The
nulling circuitry in the LTC1250 closes a loop that includes
the external feedback network during part of its cycle. This
loop must settle to its final value within 150
s or it will not
C
pF
A
F
V
55
+
R
IN
1250 F03
LTC1250
R
F
Figure 3. Extra Resistor Will
Not Cancel Bias Current Errors
7
LTC1250
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Output Drive
The LTC1250 includes an enhanced output stage which
provides nearly symmetrical output source/sink currents.
This output is capable of swinging a minimum of
4V into a
1k load with
5V supplies, and can sink or source >20mA
into low impedance loads. Lightly loaded (R
L
100k), the
LTC1250 will swing to within millivolts of either rail. In single
supply applications, it will typically swing 4.3V into a 1k load
with a 5V supply.
Minimizing External Errors
The input noise, offset voltage, and bias current specs for the
LTC1250 are all well below the levels of circuit board
parasitics. Thermocouples between the copper pins of the
LTC1250 and the tin/lead solder used to connect them can
overwhelm the offset voltage of the LTC1250, especially if a
soldering iron has been around recently. Note also that when
the LTC1250's output is heavily loaded, the chip may
dissipate substantial power, raising the temperature of the
package and aggravating thermocouples at the inputs.
Although the LTC1250 will maintain its specified accuracy
under these conditions, care must be taken in the layout to
prevent or compensate circuit errors. Be especially careful
of air currents when measuring low frequency noise; nearby
moving objects (like people) can create very large noise
peaks with an unshielded circuit board. For more detailed
explanations and advice on how to avoid these errors, see
the LTC1051/LTC1053 data sheet.
Sampling Behavior
The LTC1250's zero-drift nulling loop samples the input at
5kHz, allowing it to process signals below 2kHz with no
aliasing. Signals above this frequency may show aliasing
behavior, although wideband internal circuitry generally
keeps errors to a minimum. The output of the LTC1250 will
have small spikes at the clock frequency and its harmonics;
these will vary in amplitude with different feedback configu-
rations. Low frequency or band-limited systems should not
be affected, but systems with higher bandwidth
(oversampling A/Ds, for example) may need to filter out
these clock artifacts. Output spikes can be minimized with a
large feedback capacitor, but this will adversely affect noise
performance (see Input Capacitance and Compensation on
the previous page). Applications which require spike-free
output in addition to minimum noise will need a low-pass
filter after the LTC1250; a simple RC will usually do the job
(Figure 4). The LTC1051/LTC1053 data sheet includes more
information about zero-drift amplifier sampling behavior.
Single Supply Operation
The LTC1250 will operate with single supply voltages as low
as 4.5V, and the output swings to within millivolts of either
supply when lightly loaded. The input stage will common
mode to within 250mV of ground with a single 5V supply,
and will common mode to ground with single supplies
above 11V. Most bridge transducers bias their inputs above
ground when powered from single supplies, allowing them
to interface directly to the LTC1250 in single supply applica-
tions. Single-ended, ground-referenced signals will need to
be level shifted slightly to interface to the LTC1250's inputs.
Fault Conditions
The LTC1250 is designed to withstand most external fault
conditions without latch-up or damage. However, unusually
severe fault conditions can destroy the part. All pins are
protected against faults of
25mA or 5V beyond either
supply, whichever comes first. If the external circuitry can
exceed these limits, series resistors or voltage clamp diodes
should be included to prevent damage.
The LTC1250 includes internal protection against ESD dam-
age. All data sheet parameters are maintained to 1kV ESD on
any pin; beyond 1kV, the input bias and offset currents will
increase, but the remaining specs are unaffected and the
part remains functional to 5kV at the input pins and 8kV at the
output pin. Extreme ESD conditions should be guarded
against by using standard anti-static precautions.
+
LTC1250
47k
R
F
C
F
0.01
1250 F04
Figure 4. RC Output Pole Limits Bandwidth to 330Hz
8
LTC1250
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
q
FAX
: (408) 434-0507
q
TELEX
: 499-3977
LINEAR TECHNOLOGY CORPORATION 1994
U
S
A
O
PPLICATI
TYPICAL
Reference Buffer
Differential Thermocouple Ampliifer
0.016 0.050
0.406 1.270
0.010 0.020
(0.254 0.508)
45
0 8 TYP
0.008 0.010
(0.203 0.254)
SO8 0294
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
0.004 0.010
(0.101 0.254)
0.050
(1.270)
BSC
1
2
3
4
0.150 0.157*
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
S8 Package 8-Lead Plastic SOIC
N8 0694
0.045 0.015
(1.143 0.381)
0.100 0.010
(2.540 0.254)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130 0.005
(3.302 0.127)
0.015
(0.380)
MIN
0.018 0.003
(0.457 0.076)
0.125
(3.175)
MIN
1
2
3
4
8
7
6
5
0.255 0.015*
(6.477 0.381)
0.400*
(10.160)
MAX
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.025
0.015
+0.635
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
J8 0694
0.014 0.026
(0.360 0.660)
0.200
(5.080)
MAX
0.015 0.060
(0.381 1.524)
0.125
3.175
MIN
0.100 0.010
(2.540 0.254)
0.300 BSC
(0.762 BSC)
0.008 0.018
(0.203 0.457)
0 15
0.385 0.025
(9.779 0.635)
0.005
(0.127)
MIN
0.405
(10.287)
MAX
0.220 0.310
(5.588 7.874)
1
2
3
4
8
7
6
5
0.025
(0.635)
RAD TYP
0.045 0.068
(1.143 1.727)
FULL LEAD
OPTION
0.023 0.045
(0.584 1.143)
HALF LEAD
OPTION
CORNER LEADS OPTION
(4 PLCS)
0.045 0.068
(1.143 1.727)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.
J8 Package 8-Lead Ceramic DIP
N8 Package 8-Lead Plastic DIP
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
+
5V
TYPE K
R4
1M
0.1%
C1
100pF
7
6
4
3
2
5V
V
OUT
100mV/C
1250 TA04
LTC1250
R5
3k
R6
7.5k
1%
R7
500
FULL-SCALE TRIM
R9
33k
5V
C2
100pF
+
R3
1M
0.1%
R8
5k
1%
5V
GND
V
IN
V
OUT
LT1025
10mV/C
R1
10k
0.1%
R2
10k
0.1%
V
CM
FOR BEST ACCURACY, THERMOCOUPLE
RESISTANCE SHOULD BE LESS THAN 100
+
15V
7
6
4
3
2
10ppm ERROR AT 15mA
1
V
P-P
OUTPUT NOISE
2.5
V/C DRIFT (DUE TO LM399)
1250 TA03
LTC1250
7.5k
LM399
3
1
2
4
LT/GP 0894 2K REV A PRINTED IN USA
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