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Электронный компонент: LT1381IS

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1
LT1381
Low Power 5V RS232 Dual
Driver/Receiver with
0.1
F Capacitors
R
Output Waveforms
DRIVER
OUTPUT
R
L
= 3k
C
L
= 2500pF
RECEIVER
OUTPUT
C
L
= 50pF
INPUT
U
S
A
O
PPLICATI
s
Portable Computers
s
Battery-Powered Systems
s
Power Supply Generator
s
Terminals
s
Modems
U
A
O
PPLICATI
TYPICAL
D
U
ESCRIPTIO
S
FEATURE
s
ESD Protection over
10kV
s
Low Cost
s
Uses Small Capacitors: 0.1
F
s
CMOS Comparable Low Power: 40mW
s
Operates from a Single 5V Supply
s
120kBaud Operation for R
L
= 3k, C
L
= 2500pF
s
250kBaud Operation for R
L
= 3k, C
L
= 1000pF
s
Rugged Bipolar Design
s
Outputs Assume a High Impedance State When
Powered Down
s
Absolutely No Latchup
s
Available in Narrow SO Package
5k
5k
0.1
F
LOGIC
INPUTS
LOGIC
OUTPUTS
9
12
10
11
5
4
3
1
15
8
13
7
14
6
2
16
5V INPUT
V
+
OUT
V
OUT
RS232 OUTPUT
RS232 OUTPUT
RS232 INPUT
RS232 INPUT
LT1381 TA01
LT1381
0.1
F
0.1
F
0.1
F
+
+
+
+
S
, LTC and LT are registered trademarks of Linear Technology Corporation.
TransZorb
is a registered trademark of General Instruments, GSI
The LT
1381 is a dual RS232 driver/receiver pair with
integral charge pump to generate RS232 voltage levels
from a single 5V supply. The circuit features rugged
bipolar design to provide operating fault tolerance and
ESD protection unmatched by competing CMOS designs.
Using only 0.1
F external capacitors, the circuit con-
sumes only 40mW of power and can operate to 120kbaud
even while driving heavy capacitive loads. New ESD struc-
tures on the chip allow the LT1381 to survive multiple
10kV strikes, eliminating the need for costly TransZorbs
on the RS232 line pins. Driver outputs are protected from
overload and can be shorted to ground or up to
25V
without damage. During power-off conditions, driver and
receiver outputs are in a high impedance state, allowing
line sharing.
LT1381 TA02
2
LT1381
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
W
U
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (V
CC
) ................................................ 6V
V
+
........................................................................ 13.2V
V
...................................................................... 13.2V
Input Voltage
Driver ........................................................... V
to V
+
Receiver ............................................... 30V to 30V
Output Voltage
Driver ................................. (V
+
30V) to (V
+ 30V)
Receiver ................................. 0.3V to (V
CC
+ 0.3V)
Short-Circuit Duration
V
+
................................................................... 30 sec
V
................................................................... 30 sec
Driver Output .............................................. Indefinite
Receiver Output .......................................... Indefinite
Operating Temperature Range
LT1381C ................................................. 0
C to 70
C
LT1381I .............................................. 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
ORDER PART
NUMBER
LT1381CN
LT1381CS
LT1381IS
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
C1
+
V
+
C1
C2
+
C2
V
TR2 OUT
REC2 IN
V
CC
GND
TR1 OUT
REC1 IN
REC1 OUT
TR1 IN
TR2 IN
REC2 OUT
N PACKAGE
16-LEAD PLASTIC DIP
S PACKAGE
16-LEAD PLASTIC SOIC
T
JMAX
= 125
C,
JA
= 90
C/ W,
JC
= 46
C/W (N)
T
JMAX
= 125
C,
JA
= 110
C/ W,
JC
= 34
C/W (S)
Consult factory for Military grade parts.
(Note 2)
ELECTRICAL C
C
HARA TERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Generator
V
+
Output
7.9
V
V
Output
7.0
V
Supply Current (V
CC
)
(Note 3), T
A
= 25
C
8
14
mA
q
16
mA
Supply Rise Time
C1 = C2 = C3 = C4 = 0.1
F
0.2
ms
Oscillator Frequency
130
kHz
Driver
Output Voltage Swing
Load = 3k to GND
Positive
q
5.0
7.5
V
Negative
q
6.3
5.0
V
Logic Input Voltage Level
Input Low Level (V
OUT
= High)
q
1.4
0.8
V
Input High Level (V
OUT
= Low)
q
2.0
1.4
V
Logic Input Current
0.8V
V
IN
2.0V
q
5
20
A
Output Short-Circuit Current
V
OUT
= 0V
9
17
mA
Output Leakage Current
Power Off V
OUT
=
15V
q
10
100
A
Data Rate
R
L
= 3k, C
L
= 2500pF
120
kBaud
R
L
= 3k, C
L
= 1000pF
250
kBaud
Slew Rate
R
L
= 3k, C
L
= 51pF
15
30
V/
s
R
L
= 3k, C
L
= 2500pF
4
6
V/
s
Propagation Delay
Output Transition t
HL
High to Low (Note 4)
0.6
1.3
s
Output Transition t
LH
Low to High
0.5
1.3
s
3
LT1381
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Receiver
Input Voltage Thresholds
Input Low Threshold (V
OUT
= High)
0.8
1.3
V
Input High Threshold (V
OUT
= Low)
1.7
2.4
V
Hysteresis
q
0.1
0.4
1.0
V
Input Resistance
(Note 6)
3
5
7
k
Output Voltage
Output Low, I
OUT
= 1.6mA
q
0.2
0.4
V
Output High, I
OUT
= 160
A (V
CC
= 5V)
q
3.5
4.2
V
Output Short-Circuit Current
Sinking Current, V
OUT
= V
CC
10
mA
Sourcing Current, V
OUT
= 0V
10
20
mA
Propagation Delay
Output Transition t
HL
High-to-Low (Note 5)
250
600
ns
Output Transition t
LH
Low-to-High
350
600
ns
ELECTRICAL C
C
HARA TERISTICS
(Note 2)
TYPICAL PERFOR A CE CHARACTERISTICS
W U
Driver Maximum Output Voltage
vs Load Capacitance
TEMPERATURE (C)
55
10
DRIVER OUTPUT VOLTAGE (V)
8
4
2
0
10
4
0
50
75
LT1381 TPC03
6
6
8
2
25
25
100
125
R
L
= 3k
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 5V
V
CC
= 5.5V
OUTPUT HIGH
OUTPUT LOW
Driver Minimum Output Voltage
vs Load Capacitance
Driver Output Voltage
Note 4: For driver delay measurements, R
L
= 3k and C
L
= 51pF. Trigger
points are set between the driver's input logic threshold and the output
transition to the zero crossing (t
HL
= 1.4V to 0V and t
LH
= 1.4V to 0V).
Note 5: For receiver delay measurements, C
L
= 51pF. Trigger points are
set between the receiver's input logic threshold and the output transition
to standard TTL/CMOS logic threshold (t
HL
= 1.3V to 2.4V and t
LH
= 1.7V
to 0.8V).
Note 6: Tested at V
IN
=
10V.
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: Testing done at V
CC
= 5V, unless otherwise specified.
Note 3: Supply current is measured as the average over several charge
pump cycles. C
+
= C
= C1 = C2 = 0.1
F. All outputs are open, with all
driver inputs tied high.
20
LOAD CAPACITANCE (nF)
7.0
PEAK OUTPUT VOLTAGE (V)
6.0
5.0
4.0
2
4
6
8
LT1381 TPC02
10
1
3
5
7
9
5.5
4.5
6.5
0
2 DRIVERS LOADED
120k BAUD
60k BAUD
20k BAUD
LOAD CAPACITANCE (nF)
0
PEAK OUTPUT VOLTAGE (V)
8.0
9.0
8
LT1381 TPC01
7.0
6.0
5.0
2
4
6
10
7.5
8.5
6.5
5.5
7
1
3
5
9
2 DRIVERS LOADED
20k BAUD
60k BAUD
120k BAUD
4
LT1381
TYPICAL PERFOR A CE CHARACTERISTICS
W U
TEMPERATURE (C)
55
0.50
THRESHOLD VOLTAGE (V)
0.75
1.25
1.50
1.75
3.00
2.25
0
50
75
LT1381 TPC04
1.00
2.50
2.75
2.00
25
25
100
125
INPUT HIGH
INPUT LOW
Receiver Input Threshold
Supply Current vs Data Rate
DATA RATE (kBaud)
0
0
SUPPLY CURRENT (mA)
10
20
30
40
50
25
50
75
100
LT1381 TPC05
125
150
2 DRIVERS ACTIVE
R
L
= 3k
C
L
= 2500pF
Driver Leakage in Shutdown
TEMPERATURE (C)
0.1
LEAKAGE CURRENT
(
A)
10
100
LT1381 TPC06
1
55
0
50
75
25
25
100
125
V
OUT
= 30V
V
OUT
= 30V
Receiver Short-Circuit Current
TEMPERATURE (C)
55
0
SHORT-CIRCUIT CURRENT (mA)
20
50
0
50
75
LTLT1381 TPC07
10
40
30
25
25
100
125
ISC
ISC
+
Driver Short-Circuit Current
Slew Rate vs Load Capacitance
V
+
Compliance Curve
LOAD CURRENT
+
(mA)
0
0
V
+
(V)
2
4
6
8
10
5
10
LT1381 TPC10
15
V
+
(0.1
F)
V
+
(1
F)
TEMPERATURE (C)
55
SHORT-CIRCUIT CURRENT (mA)
20
25
30
25
75
LT1381 TPC08
15
10
25
0
50
100
125
5
0
ISC
+
ISC
CAPACITANCE (nF)
0
SLEW RATE (V/
s)
12
16
20
4
LT1381 TPC09
8
4
0
1
2
3
5
10
14
18
6
2
+SLEW RATE
SLEW RATE
V
Compliance Curve
LOAD CURRENT
(mA)
0
0
V
(V)
2
4
6
8
10
5
10
LT1381 TPC11
15
V
(0.1
F)
V
(1
F)
5
LT1381
PI FU CTIO S
U
U
U
C1
+
, C1
, C2
+
, C2
(Pins 1, 3, 4, 5): Commutating
Capacitor Inputs. These pins require two external capaci-
tors C
0.1
F: one from C1
+
to C1
and another from C2
+
to C2
. C1 may be deleted if a separate 12V supply is
available and connected to pin C1
+
.
V
+
(Pin 2): Positive Supply Output (RS232 Drivers).
V
+
2V
CC
2.1V. This pin requires an external charge
storage capacitor C
0.1
F, tied to ground or V
CC
. Larger
value capacitors may be used to reduce supply ripple. With
multiple transceivers, the V
+
and V
pins may be paralleled
into common capacitors.
V
(Pin 6): Negative Supply Output (RS232 Drivers).
V
(2V
CC
3V). This pin requires an external charge
storage capacitor C
0.1
F. Larger value capacitors may
be used to reduce supply ripple. With multiple transceiv-
ers, the V
+
and V
pins may be paralleled into common
capacitors.
TR2 OUT, TR1 OUT (Pin 7, 14): Driver Outputs at RS232
Voltage Levels. Driver output swing meets RS232 levels
for loads up to 3k. Slew rates are controlled for lightly
loaded lines. Output current capability is sufficient for
load conditions up to 2500pF. Outputs are in a high
impedance state when V
CC
= 0V. Outputs are fully short-
circuit protected from V
+ 25V to V
+
25V. Applying
higher voltages will not damage the device if the over-
drive is moderately current limited. Short circuits on one
output can load the power supply generator and may
disrupt the signal levels of the other outputs. The driver
outputs are protected against ESD to
10kV for human
body model discharges.
REC2 IN, REC1 IN (Pins 8, 13): Receiver Inputs. These
pins accept RS232 level signals (
30V) into a protected 5k
terminating resistor. The receiver inputs are protected
against ESD to
10kV for human body model discharges.
Each receiver provides 0.4V of hysteresis for noise immu-
nity. Open receiver inputs assume a logic low state.
REC2 OUT, REC1 OUT (Pins 9, 12): Receiver Outputs with
TTL/CMOS Voltage Levels. Outputs are fully short-circuit
protected to ground or V
CC
with the power ON or OFF.
TR2 IN, TR1 IN (Pins 10, 11): RS232 Driver Input Pins.
These inputs are TTL/CMOS compatible. Inputs should
not be allowed to float. Tie unused inputs to V
CC
.
GND (Pin 15): Ground Pin.
V
CC
(Pin 16): 5V Input Supply Pin. This pin should be
decoupled with a 0.1
F ceramic capacitor close to the
package pin. Insufficient supply bypassing can result in
low output drive levels and erratic charge pump operation.
ESD PROTECTIO
U
The RS232 line inputs of the LT1381 have on-chip protec-
tion from ESD transients up to
10kV. The protection
structures act to divert the static discharge safely to
system ground. In order for the ESD protection to function
effectively, the power supply and ground pins of the circuit
must be connected to ground through low impedances.
The power supply decoupling capacitors and charge pump
storage capacitors provide this low impedance in normal
application of the circuit. The only constraint is that low
ESR capacitors must be used for bypassing and charge
storage. ESD testing must be done with pins V
CC
, V
+
, V
and GND shorted to ground or connected with low ESR
capacitors.
ESD Test Circuit
LT1381 ESD TC
0.1
F
RS232
LINE PINS
PROTECTED
TO
10kV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0.1
F
0.1
F
0.1
F
C1
+
V
+
C1
C2
+
C2
V
TR2 OUT
LT1381
0.1
F
5V V
CC
GND
TR1 OUT
REC1 IN
REC1 OUT
TR1 IN
TR2 IN
RS232
LINE PINS
PROTECTED
TO
10kV
REC2 IN
REC2 OUT
+
+
+
+
+