1
LTC1403/LTC1403A
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APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
s
2.8Msps Conversion Rate
s
Low Power Dissipation: 14mW
s
3V Single Supply Operation
s
2.5V Internal Bandgap Reference can be Overdriven
s
3-Wire Serial Interface
s
Sleep (10
W) Shutdown Mode
s
Nap (3mW) Shutdown Mode
s
80dB Common Mode Rejection
s
0V to 2.5V Unipolar Input Range
s
Tiny 10-Lead MS Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Communications
s
Data Acquisition Systems
s
Uninterrupted Power Supplies
s
Multiphase Motor Control
s
Multiplexed Data Acquisition
2nd, 3rd and SFDR
vs Input Frequency
The LTC
1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-
rial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MS package. A Sleep shutdown feature lowers power
consumption to 10
W. The combination of speed, low
power and tiny package makes the LTC1403/LTC1403A
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differen-
tially. The absolute voltage swing for +A
IN
and A
IN
extends from ground to the supply voltage.
The serial interface sends out the conversion results
during the 16 clock cycles following CONV
for compat-
ibility with standard serial interfaces. If two additional
clock cycles for acquisition time are allowed after the data
stream in between conversions, the full sampling rate of
2.8Msps can be achieved with a 50.4MHz clock.
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC1403A
V
REF
10
F
A
IN
A
IN
+
14-BIT ADC
3V
10
F
14
14-BIT LA
TCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
V
DD
SDO
CONV
SCK
1403A TA01
5
6
11
FREQUENCY (MHz)
0.1
80
THD, 2nd, SFDR, 3rd (dB)
74
68
62
56
1
10
100
1403A TA02
86
92
98
104
50
44
THD
3rd
2nd, SFDR
2
LTC1403/LTC1403A
1403af
T
JMAX
= 125
C,
JA
= 150
C/ W
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
1
2
3
4
5
A
IN
+
A
IN
V
REF
GND
GND
10
9
8
7
6
CONV
SCK
SDO
V
DD
GND
TOP VIEW
11
MSE PACKAGE
10-LEAD PLASTIC MSOP
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Analog Input Voltage
(Note 3) ....................................0.3V to (V
DD
+ 0.3V)
Digital Input Voltage ................... 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1403C/LTC1403AC ............................ 0
C to 70
C
LTC1403I/LTC1403AI ......................... 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
MSE PART MARKING
LTBDN
LTBDP
LTADF
LTAFD
LTC1403CMSE
LTC1403IMSE
LTC1403ACMSE
LTC1403AIMSE
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With internal reference. V
DD
= 3V
LTC1403
LTC1403A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
12
14
Bits
Integral Linearity Error
(Notes 4, 5, 18)
q
2
0.25
2
4
0.5
4
LSB
Offset Error
(Notes 4, 18)
q
10
1
10
20
2
20
LSB
Gain Error
(Note 4, 18)
q
30
5
30
60
10
60
LSB
Gain Tempco
Internal Reference (Note 4)
15
15
ppm/
C
External Reference
1
1
ppm/
C
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. V
DD
= 3V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Differential Input Range (Notes 3, 9)
2.7V
V
DD
3.3V
q
0 to 2.5
V
V
CM
Analog Common Mode + Differential
0 to V
DD
V
Input Range (Note 10)
I
IN
Analog Input Leakage Current
q
1
A
C
IN
Analog Input Capacitance
13
pF
t
ACQ
Sample-and-Hold Acquisition Time
(Note 6)
q
39
ns
t
AP
Sample-and-Hold Aperture Delay Time
1
ns
t
JITTER
Sample-and-Hold Aperture Delay Time Jitter
0.3
ps
CMRR
Analog Input Common Mode Rejection Ratio
f
IN
= 1MHz, V
IN
= 0V to 3V
60
dB
f
IN
= 100MHz, V
IN
= 0V to 3V
15
dB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
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CO VERTER CHARACTERISTICS
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A ALOG I PUT
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LTC1403/LTC1403A
1403af
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. V
DD
= 3V
LTC1403
LTC1403A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
SINAD
Signal-to-Noise Plus
100kHz Input Signal
70.5
73.5
dB
Distortion Ratio
1.4MHz Input Signal
q
68
70.5
70
73.5
dB
100kHz Input Signal, External V
REF
= 3.3V,
72
76.3
dB
V
DD
3.3V
750kHz Input Signal, External V
REF
= 3.3V,
72
76.3
dB
V
DD
3.3V
THD
Total Harmonic
100kHz First 5 Harmonics
87
90
dB
Distortion
1.4MHz First 5 Harmonics
q
83
76
86
78
dB
SFDR
Spurious Free
100kHz Input Signal
87
90
dB
Dynamic Range
1.4MHz Input Signal
83
86
dB
IMD
Intermodulation
1.25V to 2.5V 1.25MHz into A
IN
+
, 0V to 1.25V,
82
82
dB
Distortion
1.2MHz into A
IN
Code-to-Code
V
REF
= 2.5V (Note 18)
0.25
1
LSB
RMS
Transition Noise
Full Power Bandwidth
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(Note 15)
50
50
MHz
Full Linear Bandwidth
S/(N + D)
68dB
5
5
MHz
The
q
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25
C. V
DD
= 3V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
2.5
V
V
REF
Output Tempco
15
ppm/
C
V
REF
Line Regulation
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
600
V/V
V
REF
Output Resistance
Load Current = 0.5mA
0.2
V
REF
Settling Time
2
ms
The
q
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25
C. V
DD
= 3V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 3.3V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 2.7V
q
0.6
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
10
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 3V, I
OUT
= 200
A
q
2.5
2.9
V
V
OL
Low Level Output Voltage
V
DD
= 2.7V, I
OUT
= 160
A
0.05
V
V
DD
= 2.7V, I
OUT
= 1.6mA
q
0.10
0.4
V
I
OZ
Hi-Z Output Leakage D
OUT
V
OUT
= 0V to V
DD
q
10
A
C
OZ
Hi-Z Output Capacitance D
OUT
1
pF
I
SOURCE
Output Short-Circuit Source Current
V
OUT
= 0V, V
DD
= 3V
20
mA
I
SINK
Output Short-Circuit Sink Current
V
OUT
= V
DD
= 3V
15
mA
DY
A
IC ACCURACY
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I TER AL REFERE CE CHARACTERISTICS
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DIGITAL I PUTS A D DIGITAL OUTPUTS
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LTC1403/LTC1403A
1403af
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency per Channel
q
2.8
MHz
(Conversion Rate)
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
q
357
ns
t
SCK
Clock Period
(Note 16)
q
19.8
10000
ns
t
CONV
Conversion Time
(Note 6)
16
18
SCLK cycles
t
1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
ns
t
2
CONV to SCK
Setup Time
(Notes 6, 10)
3
ns
t
3
Nearest SCK Edge Before CONV
(Note 6)
0
ns
t
4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t
5
SCK
to Sample Mode
(Note 6)
4
ns
t
6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t
7
16th SCK
to CONV
Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t
8
Minimum Delay from SCK
to Valid Bits 0 Through 13
(Notes 6, 12)
8
ns
t
9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t
10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t
12
V
REF
Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
TI I G CHARACTERISTICS
W
U
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. V
DD
= 3V
POWER REQUIRE E TS
W
U
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 17)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Supply Voltage
2.7
3.6
V
I
DD
Positive Supply Voltage
Active Mode
q
4.7
7
mA
Nap Mode
q
1.1
1.5
mA
Sleep Mode (LTC1403)
2
15
A
Sleep Mode (LTC1403A)
2
10
A
P
D
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
12
mW
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and full-scale specifications are measured for a single-
ended A
IN
+
input with A
IN
grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between A
IN
+
and A
IN
.
Note 9: The absolute voltage at A
IN
+
and A
IN
must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10
F capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read without an arbitrarily long clock.
Note 17: V
DD
= 3V, f
SAMPLE
= 2.8Msps.
Note 18: The LTC1403A is measured and specified with 14-bit Resolution
(1LSB = 152
V) and the LTC1403 is measured and specified with 12-bit
Resolution (1LSB = 610
V).
5
LTC1403/LTC1403A
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ENOBs and SINAD
vs Input Frequency
SFDR vs Input Frequency
T
A
= 25
C, V
DD
= 3V (LTC1403A)
THD, 2nd and 3rd vs Input
Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
1.3MHz Sine Wave 4096 Point
FFT Plot
1.4MHz Input Summed with
1.56MHz Input IMD 4096 Point
FFT Plot
98kHz Sine Wave 4096 Point
FFT Plot
FREQUENCY (MHz)
0.1
10.0
ENOBs (BITS)
SINAD (dB)
11.0
12.0
1
10
100
1403A G01
9.0
9.5
10.5
11.5
8.5
8.0
62
68
74
56
59
65
71
53
50
FREQUENCY (MHz)
0.1
80
THD, 2nd, 3rd (dB)
74
68
62
56
1
10
100
1403A G02
86
92
98
104
50
44
THD
3rd
2nd
FREQUENCY (Hz)
0
350k
700k
1.05M
1.4M
MAGNITUDE (dB)
1403A G04
0
10
20
30
40
50
60
70
80
90
100
110
120
2.8Msps
FREQUENCY (Hz)
MAGNITUDE (dB)
1403A G05
0
10
20
30
40
50
60
70
80
90
100
110
120
0
350k
700k
1.05M
1.4M
2.8Msps
FREQUENCY (Hz)
MAGNITUDE (dB)
1403A G06
0
10
20
30
40
50
60
70
80
90
100
110
120
0
350k
700k
1.05M
1.4M
2.8Msps
Differential Linearity
vs Output Code
Integral Linearity
vs Output Code
OUTPUT CODE
0
8192
4096
12288
16383
DIFFERENTIAL LINEARITY (LSB)
1403A G13
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
OUTPUT CODE
0
8192
4096
12288
16383
INTEGRAL LINEARITY (LSB)
1403A G14
4
3
2
1
0
1
2
3
4
SNR vs Input Frequency
FREQUENCY (MHz)
0.1
62
SNR (dB)
56
50
1
10
100
1403A G03
68
65
59
53
71
74
FREQUENCY (MHz)
0.1
68
SFDR (dB)
56
44
1
10
100
1403A G17
80
74
62
50
86
92
98
104
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