LTC1531

Self-Powered Isolated

Comparator

UL Recognized File E151738 to UL1577

Self-Powered Across Isolation Barrier

2500V

RMS

Isolation

2.5V Isolated Reference, I

LOAD

= 5mA

MAX

Zero-Cross Output for Line Power

Dual Differential Input Comparator

High Input Impedance Comparator

The LTC

1531 is an isolated self-powered dual differential

comparator. An internal capacitive isolation barrier pro-
vides 2500V

RMS

of isolation between the comparator and

its output. The part provides UL-rated isolated compari-
sons without the need for an isolated supply since both
comparator power and output data are transmitted across
the capacitive barrier. The comparator data is transferred
differentially across the isolation barrier to provide high
common mode voltage and noise immunity.

The isolated side can supply a 2.5V reference output to
power external sensor circuits such as a thermistor bridge.
The dual differential comparator inputs allow for compari-
son of two differential voltages as well as single-ended
voltages. The powered side provides a latched data output
as well as a pulsed zero-cross comparator output for
controlling a triac. The part is available in a 28-lead SO
package.

Isolated Thermistor Temperature Controller

, LTC and LT are registered trademarks of Linear Technology Corporation.

Self-Powered Isolated Sensing

Isolated Temperature Control

Isolated Voltage Monitor

Isolated Switch Control

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

5.6V

120V

NEUTRAL

2N2222

LOAD
25

TECCOR

Q4008L4

OR EQUIVALENT

ISOGND

ISOLATION
BARRIER

1531 TA01

VALID

GND

390

R5*1M

THERM

O · e

B (1/T 1/T

)

B = 3807
T

= 297

2.5V

50V

LTC1531

R2
47k

680k

150

750

0.5W

THERM
30k
YSI 44008

R4
50k

SHDN

CMPOUT

REG

ZCDATA

ZCPOS

ZCNEG

DATA

LED

Q D

C1
0.01

3k
3W

1N4004

100

*HYSTERESIS = 1

C AT T

= ISOLATED GROUND

R6
22k

DANGER!

LETHAL VOLTAGES

IN THIS SECTION!

LTC1531

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

ORDER PART

NUMBER

LTC1531CSW

SHDN

ZCNEG

ZCPOS

CMPOUT

REG

ISOGND

GND

ZCDATA

DATA

VALID

SW PACKAGE

28-LEAD PLASTIC SO (ISO)

TOP VIEW

JMAX

= 125

C/ W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VCC

Supply Current

SHDN = V

, No Load

SHDN = 0V

0.2

ZCOS

Zero-Cross Offset

= V

120

HYS

Zero-Cross Hysteresis

= V

(Note 7)

200

800

SAMPLE

Isolated Comparator Sample Rate

REG

Not Loaded (Note 2)

300

Isolated Comparator Offset

V1 = V2, V3 = V4

2.0

4.0

V1 V3 = 2V, V4 V2 = 2V

2.0

4.0

VIN

Isolated Comparator

V1 = V3 = 2.5V, V2 = V4 = 0V

Input Impedance

V1 = V2 = 1.25V, V3 = V4 = 0V

300

VIN

Isolated Comparator Input Current

V1 = V3 2.5V, V2 = V4 = 0V

SAMPLE

= 700Hz (Note 4)

REG

2mA Load V

= 3.3V (Note 5)

2.40

2.50

2.55

VREG

REG

Output Impedance

2mA to 5mA Load

CMPOUT

CMPOUT High Impedance Leakage Current

CMPOUT

= 2.5V

VREG

REG

On-Time

108

130

PWH

, Power Detect Enable Voltage

3.3

VPW

Current Transfer to V

= 0V

= 3.3V

ISO

Isolation Voltage

1 Minute (Note 6)

2500

RMS

1 Second

4500

Total Supply Voltage (V

to GND) ............................ 7V

Input Voltages

Isolated Comparator
(V1 to V4) .............................. 0.3V to (V

+ 0.3V)

SHDN, ZCPOS, ZCNEG ......................... 0.3V to 12V

Current

Input Pins .......................................................

10mA

ZCDATA, VALID, DATA ..................................

10mA

Operating Temperature Range ..................... 0

C to 70

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

(Note 1)

The

denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25

C, V

= 5V.

LTC1531

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SHDN Input High Voltage

= 4.5V

2.4

SHDN Input Low Voltage

= 5.5V

0.8

DATA, VALID, ZCDATA Output High Voltage

= 4.5V, I

= 400

3.0

4.3

DATA, VALID, ZCDATA Output Low Voltage

= 4.5V, I

= 1.6mA

0.2

0.4

INL

, I

INH

SHDN Low or High Level Input Current

= 5V, 0V

dV/dt

Continuous dV/dt Rejection

(Note 8)

ISO

Note 4: The sample rate, f

SAMPLE

, varies with loading on V

and V

REG

Note 5: Load on CMPOUT pulls current from V

REG

when CMPOUT is high.

Note 6: Value derived from 1 second test.

Note 7: Zero-cross hysteresis is the minimum amount of signal amplitude
above or below 0V differential to retrigger the zero-cross comparator.

Note 8: Parameter not tested but guaranteed by design.

TYPICAL PERFOR

CE CHARACTERISTICS

TIME (ms)

REG

(V)

2.5

3.3

1531 F02

= 5V, C

VPW

= 1

VREG

= 100

A, T

= 25

NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE
ON V

> 3.3V AND THE POWER-LISTEN CYCLE

SAMPLING

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The sample rate is not continuous, but depends on V

charging

rate. See Applications Information.

Note 3: See Applications Information for further description of the
comparator switched-capacitor input circuit.

Figure 2. V

REG

and V

vs Time

VREG

= 100

Figure 1. V

Power-Up and

REG

Samples vs Time

The

denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25

C, V

= 5V.

TIME (ms)

(V)

3.3

2.5

1531 F01

100

200

300

NOTES: V

RIPPLE

DEPENDS ON C

VPW

AND I

VPW

+ I

VREG

SAMPLE

DEPENDS ON I

VPW

+ I

VREG

SAMPLE

REG

= 5V

VPW

= 1

VREG

= 5mA

= 25

RIPPLE

LTC1531

CTIO

(Pin 1): Powered Side Power Supply.

SHDN (Pin 2): Active Low Chip Shutdown. A low signal
causes the circuitry to power down. DATA logic output
level will be reset to zero during power-down.

ZCNEG (Pin 3): Zero-Cross Comparator Negative Input.

ZCPOS (Pin 4): Zero-Cross Comparator Positive Input.

(Pin 11): Isolated Power Supply. Connect to an

external storage capacitor.

CMPOUT (Pin 12): Isolated Latched Comparator Data.
CMPOUT is active when V

REG

is on. The CMPOUT output

can be used on the isolated side for hysteresis (see
applications). The output will contain the result of the
previous comparison. When V

REG

is low, the CMPOUT pin

is Hi-Z.

REG

(Pin 13): Isolated 2.5V Regulated Output. Pulsed on

for 100

s with a maximum load current of 5mA. V

REG

also

supplies power to the CMPOUT output (Pin 12).

ISOGND (Pin 14): Isolated Side Power Ground.

V4 (Pin 15): Comparator Negative Input. The comparator
inputs are summed together with the comparison output

equal to (V1 + V2)/2 > (V3 + V4)/2 or equivalently (V1 V3)
> (V4 V2).

V3 (Pin 16): Comparator Negative Input.

V2 (Pin 17): Comparator Positive Input.

V1 (Pin 18): Comparator Positive Input.

VALID (Pin 25): Pulsed Output. Indicates when valid data
was received from the comparator. May be used to clock
DATA to external circuitry.

DATA (Pin 26): Latched Comparator Result. DATA holds
the value of the last valid comparison result. DATA changes
only when a valid comparison was received from the
isolated side.

ZCDATA (Pin 27): A 24

s to 30

s Pulsed Output. The

pulse occurs when the DATA output is high and the zero-
cross comparator inputs (ZCPLS-ZCNEG) cross zero volts
differential. Typically the zero-cross input signal is an RC
phase shifted AC sine wave. This output is a TTL level pulse
that can be used for firing an external triac.

GND (Pin 28): Power Supply Low Impedance Ground
Connection.

VREG

(mA)

SAMPLE

(ms)

1531 F03

= 4.5V

= 25

= 5.5V

= 5V

Figure 3. Average t

SAMPLE

vs I

VREG

TYPICAL PERFOR

CE CHARACTERISTICS

Figure 4. V

RMS

vs Frequency

FREQUENCY (Hz)

RMS

4500V

BREAKDOWN

LIMIT

100k

100M

1531 F04

10k

10M

2500V

RMS

450mV

4.5V

45V

450V

SLEW RATE = (

)(f)(V

P-P

)

= (1.11)(f)(V

RMS)

= V

RMS

50V/

(1.11)(f)

LTC1531

APPLICATIO

S I

FOR

ATIO

The LTC1531 is an isolated self-powered dual differential
comparator. It contains a switched-capacitor comparator
that is self-powered through a capacitive isolation barrier.
The capacitive isolation barrier provides 2500V

RMS

isolation. The isolated comparator cycles between storing
power and performing sampled comparisons. During the
power delivery cycle, the nonisolated powered side deliv-
ers power through the internal isolation capacitors and
rectifier onto an external storage capacitor. Periodically
the isolated comparator makes a comparison if sufficient
voltage has been stored on the external supply capacitor.
See Timing and Block Diagrams.

During a comparison, the isolated side uses the energy
stored on the external capacitor to deliver a regulated 2.5V
power source for 108

s followed by a sampled compari-

son. The result is transmitted back to the nonisolated
powered side and latched as the logic level DATA output.
A comparison will occur during the listen cycle if sufficient
voltage (3.3V) has been stored on the isolated external
capacitor. New DATA is latched only if a comparison was
actually done. A zero-crossing trigger pulse output for
firing a triac, ZCDATA, is available to trigger a triac when
the latched DATA output is high. A VALID data output pulse
is provided after each power-listen cycle in which a com-
parison was done to indicate that DATA has been updated.
The VALID output can be used to clock external circuitry
when a new comparator DATA value occurs.

POWER-LISTEN CYCLE

Self-Powering Through the Isolation Barrier

The LTC1531 comparator powered side toggles between
delivering power to the isolated side and listening for a
comparison result (see Timing Diagram). During the power
cycle, AC power is delivered through the isolation capaci-
tors, formed in the lead frame, to the isolated side. During
the listen cycle, the powered side receives pulses from the
isolated side and determines if a valid comparison
occurred.

The isolated side of the LTC1531 requires an external
capacitor connected to V

whose value must be large

enough to sustain less than a 300mV drop for 108

s with

the internal + external V

REG

load current. Power is deliv-

ered to this external capacitor through the internal isola-
tion capacitors and rectifiers during the power cycle.
When this voltage reaches approximately 3.3V, the com-
pare circuitry is enabled and a comparison will occur
during the next listen cycle. With V

= 5V, this capacitive

coupled isolated power source can be modeled as an
equivalent 5.3V to 6.5V source with a 100k

source

impedance. The V

pin will tend to self-regulate at 3.3V

with a ripple determined by the discharge current supplied
during the 108

s V

REG

output pulse and the external

capacitor value. The value of the capacitor affects the initial
start-up time and the ripple voltage on V

, but it does not

influence the sample rate of the comparator. This is
because the sample rate is determined by the rate of power
delivered through the isolation barrier and the rate it is
consumed in the internal plus external isolated circuits.

Any excessive external DC loading on V

may prevent the

capacitor voltage from reaching the required 3.3V enable
voltage. Up to 20

A of continuous loading on V

can be

tolerated based on the 100k, 5.3V model of the power
source (see Typical Applications for examples). The qui-
escent current of the isolated side is approximately 2

to 3

SAMPLE RATE

The comparator sample rate depends on the charging rate
through the isolated capacitors and the external + internal
load current . The power-listen cycles at 700Hz to 900Hz,
however, a comparison will only occur when V

exceeds

the 3.3V enable voltage. Typical sample rate for light
loading is 200Hz to 300Hz. The actual sampling is not
uniform, but occurs during the listen period of the power
cycle and when V

3.3V. Typical sample rates for

various supply and load conditions are plotted in Figure 3.
Continuous micropower loads will also decrease the sample
rate.

REG

Reference Output

The V

REG

reference output pulses on for approximately

108

s at 2.5V. During the off time, V

REG

does not go high

impedance. The V

REG

output stage is shown in Figure 5.

Large capacitance should not be attached to V

REG

in order

to avoid power loss. Charging of the V

REG

output capaci-

LTC1531

APPLICATIO

S I

FOR

ATIO

tance, which will subsequently be discharged between
samples, will consume power from V

ISOLATED COMPARATOR INPUTS AND CMPOUT

The LTC1531 isolated comparator has a 4-input
summing comparator that performs the following
comparison:

(V1 + V2)/2 > (V3 + V4)/2

By rearranging the equation, for example, a dual differen-
tial comparison is performed:

(V1 V4) > (V3 V2) or (V1 V3) > (V4 V2)

The input has a rail-to-rail input and common mode
voltage range of V

-ISOGND. The summing nature of the

inputs allows midsupply referencing. For example, con-
necting V3 to V

REG

and V4 to ISOGND sums together to

provide V

REG

/2 for the negative comparator input. See for

example, the Isolated Switch Control.

Charge injection and leakage currents occur at the com-
parator inputs. The amount depends on how the compara-
tor is used. Minimum leakage currents occur with V1 = V2
and V3 = V4 where the input impedance is from charge
injection and is nominally 300M

. When V1

V2 or

V4, the input impedance due to leakage currents is

about 15M

to 20M

. Since the comparator is turned on

only for the last 10

s of the 108

s V

REG

period, the charge

injection occurs at about the 98

s point with a coupling

capacitance of 2pF per input.

The CMPOUT signal is typically used to provide hyster-
esis, as in the Isolated Temperature Control application.
CMPOUT is the latched result of the previous comparison
and is active during the following V

REG

ON period. CMPOUT

is powered by V

REG

, the internal 2.5V regulated output,

and is in high impedance except during the 108

REG

ON time. When active, CMPOUT is switched low to

ISOGND or high to V

REG

depending on the stored result of

the previous comparison. The stored CMPOUT data is
reset during power-up. CMPOUT is not necessarily reset
by the powered side SHDN pin, except when shutdown
results in V

drooping low enough to trigger a power-on

reset on the isolated side between 1.5V to 2.5V.

DATA, VALID, ZCDATA

During a power cycle, the VALID signal goes high if a valid
comparison was made during the previous listen cycle.
VALID goes low at the beginning of the next listen cycle.
The low-to-high transition of VALID can be used to clock
DATA into external circuitry. VALID is delayed 200ns after
the DATA output. In order for a comparison to occur,
sufficient power must be stored on the isolated side
storage capacitor.

The DATA output holds the last received compare result.
DATA is reset to zero on power-up and shutdown. The
VALID output is held high for one power cycle following a
correctly received compare result. The received DATA
value from the isolated side contains redundancy to im-
prove noise immunity.

The ZCDATA is a 25

s output pulse triggered by the zero-

cross comparator. In order for a pulse to occur, the DATA
output must be at logic 1 and the ZCPOS-ZCNEG zero-
cross comparator input crosses 0V after the input has
exceeded the

150mV to 800mV of hysteresis. The zero-

cross comparator output is typically used to trigger a triac
from a 60Hz RC phase shifted AC line signal. See Typical
Applications.

Figure 5. V

REG

Output Stage

REG

1531 F05

23k

16k

ISOGND

21k

16k

ISOGND

LTC1531

The zero-cross comparator inputs, ZCPOS and ZCNEG,
have an input common mode range that allows signal
swings near the positive supply rails. The ZCPOS and
ZCNEG inputs contain ESD diode protection devices which
will clamp input signals that go below GND. The current
into the diode should be limited to less than 5mA. The
Isolated Thermistor Temperature Controller shows an
example phase shift network with attenuation that satis-
fies these conditions. The positive input voltage should
not exceed the 12V maximum rating or the 5mA input
current to the ESD diode clamp.

ISOLATION dV/dt

The maximum continuous dV/dt across the isolation bar-
rier that will still allow the isolated comparator to operate
is 50V/

s. Continuous rates of dV/dt greater than this

cause the isolated side to not detect when its power cycle
has stopped and a comparison should begin. Figure 4
shows the maximum continuous rate trade-off of fre-
quency vs voltage of a sine wave:

SR = (

)(f)(V

P-P

)

where SR = slew rate, V

P-P

= the peak-to-peak voltage and

f = frequency. Noise immunity to intermittent dV/dt rates
greater than 50V/

s can be rejected by the LTC1531.

AC Noise Rejection and Things to Avoid

Minimizing AC noise pickup at the isolated comparator
should follow the following guidelines.

1. Allow the isolated side ground to float. The isolated side

should only be common with the isolated circuit.

2. Use hysteresis to decrease sensitivity by using CMPOUT.

3. Use lower impedance circuits if powered by V

REG

Avoid large capacitance tied directly to V

REG

output,

since this output does not go Hi-Z (high impedance)
during the off time.

PC Board Layout

The PC board layout should not have copper near the lead
frame isolation capacitors. The copper reduces the power
coupling and power delivery to the isolated side (see
Figure 6).

APPLICATIO

S I

FOR

ATIO

TYPICAL APPLICATIONS DESCRIPTION

The Isolated Thermistor Temperature Controller (front
page) uses a simple AC power rectifier and Zener to
provide 5.6V of DC power to the LTC1531. To avoid power
dissipation in the 3k, 3W resistor, DC power can be
provided with a charge pump circuit similar to the Isolated
Switch Control. In this circuit, a thermistor half bridge is
used with the 4-input comparator connected to provide
the other half of the bridge, V4 = 2.5V, V3 = 0V, giving
(V4 + V3)/2 = 1.25V. With the 50k pot set to about 30k, the
trip point is 25

C with a hysteresis of

0.5

C. Here, V

REG

turns on and powers the half-bridge while the comparator
samples the result. The zero-cross comparator, ZCPOS
and ZCNEG, is used to trigger a triac at the 10

phase point.

The circuit, R1, R2 and C1, provides the phase shift,

, as

determined by:

R2C1

tan(

)/2

60Hz

and where the attenuation

R2/R1. In this example,

R1 = 680k, R2 = 47k and C1 = 0.01

F, provide a 7V peak

input signal with 10

of phase lag.

Figure 6. PC Board Layout Consideration

SHDN

ZCNEG

ZCPOS

CMPOUT

REG

ISOGND

GND

ZCDATA

DATA

VALID

ETCH COPPER
FROM THE
SHADED AREA

SW PACKAGE

28-LEAD PLASTIC SO (ISO)

TOP VIEW

1531 F06

LTC1531

APPLICATIO

S I

FOR

ATIO

The Remote Light-Controlled Switch (Figure 7) is similar
to the Isolated Thermistor Temperature Controller. The
thermistor is replaced with a Cadmium Light Sensor.

The Isolated Switch Control (Figure 8) is also similar,
where a low voltage switch is isolated from the AC power
control. Here, a charge pump using the 1

F nonpolar

capacitor and diodes are used for powering the LTC1531.

The Isolated Voltage Sense circuit (Figure 9) uses the
three-state CMPOUT pin in a delta-sigma configuration.
Here, the time constant of R1C1 is increased by the
effective duty cycle of CMPOUT ON to OFF time. At a 300Hz
sample rate and a typical ON time of 108

s, the time

constant is:

(1M · 0.22

F)/(300Hz · 108

6.6sec

The input range is 0V to 2.5V set by the V

REG

output

voltage. The output is recovered using a rail-to-rail op
amp, LT1490, averaging circuit with a 10sec time con-
stant. The output range is 0V to V

output for a 0V to V

REG

input range.

The Isolated Potentiometer Transducer Sense circuit
(Figure 10) uses the same principle as the Isolated Voltage
Sense circuit to provide a 0V to V

output proportional to

the potentiometer sensor input.

The Isolated Thermocouple Voltage circuit (Figure 11)
again uses the delta-sigma approach to translate a ther-
mocouple temperature into a 0V to V

output. Addition-

ally, a micropower op amp, the LT1495, is used to provide
a continuous voltage amplification of the thermocouple.
The LT1389 with the thermistor bridge provides cold
junction compensation over a 0

C to 60

C temperature

range within

0.5

C. The op amp gain is set to give the K-

type thermocouple a 0

C to 200

C range which translates

to a 0V to V

output signal. Reducing R3 will increase the

temperature sensing range.

The Over Temperature Detect circuit (Figure 12) uses the
same continuous micropower cold junction compensa-
tion circuit as in the Isolated Thermocouple Voltage cir-
cuit. In this case, the comparator's minus input is set to
1.25V, which corresponds to 100

C as set by the LT1495

op amp gain. When the thermocouple exceeds 100

TRIP

goes high.

The Isolated Battery Cell Monitor circuit (Figure 13) uses
LTC1531 isolation to both float the individual grounds on
the isolated comparator and isolate the battery from the
logic outputs, CELL1, CELL2, ... In this application, R1 and
R2 (R3 and R4) divide the 2.5V reference down to 0.89V,
while the cell voltage is divided in half by connecting V1 to
the cell and V2 to 0V. Hence, when the cell voltage drops
below 1.786V, CELL1 goes high. Likewise for additional
cells with additional LTC1531s.

The Isolated Window Comparator circuit (Figure 14) uses
two LTC1531s and a logic gate to provide isolated window
comparisons. In this circuit, the first LTC1531, V

HIGH

does the comparison:

V1 V3 > V4 V2

(0V X · V

REG

) > (V

)

X · V

REG

< (V

)

where X = R2/(R2 + R1).

The second LTC1531, V

LOW

, does the comparison:

(X · V

REG

) > (V

)

When (V

) is less than X · V

REG

, V

LOW

goes high

and when (V

) is greater than X · V

REG

, V

HIGH

goes high. In between X · V

REG

and +X · V

REG

, V

WINDOW

is high. Therefore, the window width is 2 · X · V

REG

The AC Line Overcurrent Detect circuit (Figure 15) uses
the micropower op amps, the quad LTC1496, to peak
detect the voltage across a sense resistor in series with an
AC load. The two amplifiers connected to R

SENSE

act as

half-wave rectifiers because their outputs cannot swing
below ground. The gain is set to trip when the voltage on
R

SENSE

exceeds 125mV and the minus comparator input

is set to 1.25V. The peak detector has a discharge resistor
of 1M plus the op amp input bias current.

LTC1531

TYPICAL APPLICATIO

Figure 7. Remote Light-Controlled Switch

Figure 8. Isolated Switch Control

5.6V

120V

NEUTRAL

ISOGND

ISOLATION
BARRIER

1531 F07

VALID

GND

3k
3W

HYSTERESIS

560k

TRIAC FIRING:

= DESIRED PHASE LAG

R2 · C1 = Tan(

)/(2

60Hz)

R2/(R1 + R2) = ATTENUATION

2.5V

100

2.2

LTC1531

R2
47k

150

2N2222

CADMIUM
LIGHT
SENSOR
100k

100k

SHDN

CMPOUT

REG

ZCDATA

ZCPOS ZCNEG

DATA

680k

C1
0.01

TECCOR

Q4008L4

OR EQUIVALENT

1N4004

LOAD
25

= ISOLATED GROUND

50V

750

0.5W

Q D

DANGER!

LETHAL VOLTAGES

IN THIS SECTION!

5.6V

120V

NEUTRAL

LOAD
25

ISOGND

ISOLATION
BARRIER

1531 F08

VALID

GND

390

2.5V

100

LOW
VOLTAGE
SWITCH

LTC1531

R2
47k

470

150

2N2222

SHDN

CMPOUT

REG

ZCDATA

ZCPOS ZCNEG

DATA

LED

680k

C1
0.01

275V

50V

TECCOR

Q4008L4

OR EQUIVALENT

= ISOLATED GROUND

TRIAC FIRING:

= DESIRED PHASE LAG

R2 · C1 = Tan(

)/(2

60Hz)

R2/(R1 + R2) = ATTENUATION

1N4004

Q D

DANGER!

LETHAL VOLTAGES

IN THIS SECTION!

LTC1531

Figure 10. Isolated Potentiometer Transducer Sense

Figure 9. Isolated Voltage Sense

TYPICAL APPLICATIO

OUT

0V TO V

FULL-SCALE

OUTPUT

ISOGND

1531 F09

VALID

10k

GND

R1, 1M

ISOLATION

BARRIER

DELTA-SIGMA TYPE MODULATION:
CMPOUT IS ON 108

s AT ~300Hz RATE

THEREFORE: 108

s · 300Hz = 1/30TH

TIME CONSTANT = 1M · 30 · 0.22

F = 6.6sec

2.5V

2.2

C1
0.22

LTC1531

0V TO 2.5V
FULL-SCALE
INPUT

SHDN

CMPOUT

REG

ZCDATA

ZCPOS

ZCNEG

DATA

10k

10M

Q D

10M

C2, 1

LT1490

= ISOLATED GROUND

= EQUIPMENT GROUND

RESOLUTION = 4mV
SETTLING TIME = 10sec

OUT

0V TO V

FULL-SCALE

OUTPUT

ISOGND

1531 TA05

VALID

10k

GND

R1, 1M

ISOLATION

BARRIER

DELTA-SIGMA TYPE MODULATION:
CMPOUT IS ON 108

s AT ~300Hz RATE

THEREFORE: 108

s · 300Hz = 1/30TH

TIME CONSTANT = 1M · 30 · 0.22

F = 6.6sec

2.5V

2.2

100k

C1
0.22

LTC1531

SHDN

CMPOUT

REG

ZCDATA

ZCPOS

ZCNEG

DATA

10k

10M

Q D

10M

C2, 1

LT1490

= ISOLATED GROUND

= EQUIPMENT GROUND

RESOLUTION = 4mV
SETTLING TIME = 10sec

LTC1531

Figure 12. Over Temperature Detect

Figure 11. Isolated Thermocouple Voltage

TYPICAL APPLICATIO

TEMP

ISOGND

1531 F11

VALID

10k

GND

ISOLATION

BARRIER

33k

R3, 10M

10.2k

2.5V

2.2

LT1389

C1
0.22

LTC1531

SHDN

CMPOUT

REG

ZCDATA

ZCPOS ZCNEG

DATA

10k

10M

Q D

10M

0.1

LT1490

LT1495

1.74M

1.21k

COLD JUNCTION COMPENSATES 0

C TO 60

11.8k

THERM
30k
YSI44008

UNUSED OP AMP
TIED FOR MIN
CURRENT DRAIN

LT1495

TEMP

OUTPUT = 0V TO V

= 0

C TO 200

RESOLUTION = 0.4mV OR 0.5

RESPONSE TIME CONSTANT = 10sec

= ISOLATED GROUND

= EQUIPMENT GROUND

C2, 1

TRIP

ISOGND

1531 F12

VALID

GND

ISOLATION

BARRIER

33k

10M

10.2k

2.5V

2.2

LT1389

LTC1531

SHDN

CMPOUT

REG

ZCDATA

ZCPOS ZCNEG

DATA

Q D

0.1

LT1495

1.74M

1.21k

COLD JUNCTION COMPENSATES 0

C TO 60

VTRIP SWITCHES AT 100

C, SET BY OP AMP GAIN

11.8k

THERM
30k
YSI44008

= ISOLATED GROUND

= EQUIPMENT GROUND

UNUSED OP AMP
TIED FOR MIN
CURRENT DRAIN

LT1495

LTC1531

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

SW28 (ISO) 1098

TYP

NOTE 1

0.009 0.013

(0.229 0.330)

0.016 0.050

(0.406 1.270)

0.291 0.299**

(7.391 7.595)

0.010 0.029

(0.254 0.737)

0.005

(0.127)

RAD MIN

0.037 0.045

(0.940 1.143)

0.004 0.012

(0.102 0.305)

0.093 0.104

(2.362 2.642)

0.050

(1.270)

BSC

0.014 0.019

(0.356 0.482)

TYP

NOTE 1

0.697 0.712*

(17.70 18.08)

0.394 0.419

(10.007 10.643)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

SW Package

28-Lead Plastic Small Outline Isolation Barrier (Wide 0.300)

(LTC DWG # 05-08-1690)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1531

1531f, sn1531 LT/TP 0899 4K · PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1998

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1177

Isolated MOSFET Driver

No Secondary Power Supply, 2500V

RMS

Isolation

LT1389

Nanopower Reference

800nA, 0.05% Accuracy, 10ppm/

C Max Drift

LTC1440/LTC1441

Ultralow Power Single/Dual Comparators with Reference

2.1

A Typ, 2V to 11V Supply, Adjustable Hysteresis

LTC1442

LT1495/LT1496

1.5

A Max, Dual/Quad Precision Rail-to-Rail Input and Output Op Amps

Low Offset 375

MAX

, 2.2V to 36V Supply

LTC1540

Nanopower Comparator with Reference

0.3

A Typ, Adjustable Hysteresis, 2V to 11V Supply

Figure 15. AC Line Overcurrent Detect

TYPICAL APPLICATIO

ISOGND

1531 F15

VALID

GND

ISOLATION

BARRIER

NEGATIVE COMPARATOR
INPUT SET TO 1.25V
R

SENSE

IN SERIES WITH AC LINE

SENSE

TRIP VOLTAGE = 125mV

51k

2.5V

2.2

0.22

1N4148

LTC1531

TRIP

SHDN

CMPOUT

REG

ZCDATA

ZCPOS ZCNEG

DATA

10k

51k

SENSE

UNUSED OP AMP
TIED FOR MIN
CURRENT DRAIN

LT1496

= LIVE AC-CONNECTED
LOCAL CIRCUIT COMMON
= EQUIPMENT GROUND

LT1496

DANGER!

LETHAL VOLTAGES

IN THIS SECTION!

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1531

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1531