LTC1553

5-Bit Programmable

Synchronous Switching

Regulator Controller for

Pentium

II Processor

FEATURES

DESCRIPTIO

5-Bit Digitally Programmable 1.8V to 3.5V Fixed
Output Voltage

Provides All Features Required by the

Intel

Pentium

II Processor VRM 8.2 DC/DC

Converter Specification

Flags for Power Good, Over-Temperature and
Overvoltage Fault

19A Output Current Capability from a 5V or 12V Supply

Dual N-Channel MOSFET Synchronous Driver

Initial Output Accuracy:

1.5%

Excellent Output Accuracy:

2% Typ Over Line,

Load and Temperature Variations

High Efficiency: Over 95% Possible

Adjustable Current Limit Without External Sense
Resistors

Fast Transient Response

Available in 20-Lead SSOP and SW Packages

The LTC

1553 is a high power, high efficiency switching

regulator controller optimized for 5V or 12V input to 1.8V-
3.5V output applications. It features a digitally programmable
output voltage, a precision internal reference and an internal
feedback system that provides output accuracy of

1.5% at

room temperature and typically

2% over-temperature, load

current and line voltage shifts. The LTC1553 uses a synchro-
nous switching architecture with two external N-channel
output devices, providing high efficiency and eliminating the
need for a high power, high cost P-channel device. Addition-
ally, it senses the output current across the on-resistance of
the upper N-channel FET, providing an adjustable current
limit without an external low value sense resistor.

The LTC1553 free-runs at 300kHz and can be synchronized
to a faster external clock if desired. It includes all the inputs
and outputs required to implement a power supply conform-
ing to the

Intel Pentium

II Processor VRM 8.2 DC/DC

Converter Specification.

APPLICATIO

Power Supply for Pentium II, SPARC, ALPHA and
PA-RISC Microprocessors

High Power 5V or 12V to 1.8V-3.5V Regulators

TYPICAL APPLICATIO

Figure 1. 5V to 1.8V-3.5V Supply Application

PWRGD

FAULT

VID0 TO VID4

OUTEN

COMP

SGND

GND

SENSE

Q1*

Q2*

0.1

MAX

12V

18A

LTC1553

0.1

1553 F01

0.01

8.2k

5.6k

2.7k

5.6k

0.1

1200

OUT

1.8V TO
3.5V
14A

OUT

330

C1
150pF

PENTIUM

SYSTEM

*SILICONIX SUD50N03-10

**SANYO 10MV1200GX

COILTRONICS CTX02-13198 OR

PANASONIC 12TS-2R5SP

AVX TPSE337M006R0100

, LTC and LT are registered trademarks of Linear Technology Corporation.

Pentium is a registered trademark of Intel Corporation.

LTC1553

ABSOLUTE

AXI

RATINGS

ORDER PART

NUMBER

(Note 1)

Supply Voltage

........................................................................ 9V

................................................................... 20V

Input Voltage

(Note 2) ............................................ PV

+ 0.3V

MAX

...................................................... 0.3V to 13V

All Other Inputs ......................... 0.3V to V

+ 0.3V

Digital Output Voltage ............................... 0.3V to 13V
I

Input Current (Notes 2, 3) .......................... 100mA

Operating Temperature Range ..................... 0

C to 70

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec.)................. 300

PACKAGE/ORDER I

FOR

ATIO

= 5V, PV

= 12V, T

= 25

C, unless otherwise noted. (Note 3)

ELECTRICAL CHARACTERISTICS

Consult factory for Industrial and Military grade parts.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

4.5

Supply Voltage for G1, G2

Internal Feedback Voltage

(Note 4)

1.265

OUT

1.8V Initial Output Voltage

With Respect to Rated Output Voltage (Figure 2)

27 ( 1.5%)

27 (+ 1.5%)

2.8V Initial Output Voltage

42 ( 1.5%)

42 (+ 1.5%)

3.5V Initial Output Voltage

52 ( 1.5%)

52 (+ 1.5%)

1.8V Initial Output Voltage

36 ( 2%)

36 (+ 2%)

2.8V Initial Output Voltage

56 ( 2%)

56 (+ 2%)

3.5V Initial Output Voltage

70 ( 2%)

70 (+ 2%)

OUT

Output Load Regulation

OUT

= 0 to 14A (Note 4) (Figure 2)

Output Line Regulation

= 4.75V to 5.25V, I

OUT

= 0 (Note 4)(Figure 2)

PWRGD

Positive Power Good Trip Point

% Above Output Voltage (Figure 2)

Negative Power Good Trip Point

% Below Output Voltage (Figure 2)

FAULT

FAULT Trip Point

% Above Output Voltage (Figure 2)

Operating Supply Current

OUTEN = V

= 5V (Note 5) (Figure 3)

800

1200

Shutdown Supply Current

OUTEN = 0, VID0 to VID4 Floating (Figure 3)

130

250

PVCC

Supply Current

= 12V, OUTEN = V

(Note 6) (Figure 3)

= 12V, OUTEN = 0, VID0 to VID4 Floating

OSC

Internal Oscillator Frequency

(Figure 4)

250

300

350

kHz

SAWL

COMP

at Minimum Duty Cycle

(Note 4)

1.8

SAWH

COMP

at Maximum Duty Cycle

(Note 4)

2.8

ERR

Error Amplifier Open-Loop DC Gain

(Note 7)

mERR

Error Amplifier Transconductance

(Note 7)

0.9

1.6

2.3

millimho

ERR

Error Amplifier 3dB Bandwidth

COMP = Open (Note 4)

400

kHz

JMAX

= 125

= 100

C/ W (G)

JMAX

= 125

= 100

C/ W (SW)

TOP VIEW

G PACKAGE

20-LEAD PLASTIC SSOP

SW PACKAGE

20-LEAD PLASTIC SO

GND

SGND

SENSE

MAX

COMP

OUTEN

VID0

VID1

VID2

VID3

VID4

PWRGD

FAULT

LTC1553CG
LTC1553CSW

LTC1553

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

IMAX

MAX

Sink Current

IMAX

= V

150

180

220

Soft Start Source Current

= 0V, V

IMAX

= 0V, V

IFB

= V

SSIL

Maximum Soft Start Sink Current

SENSE

= V

OUT

, V

IMAX

= V

, V

IFB

= 0V

150

Under Current Limit

(Notes 8, 9), V

= V

SSHIL

Soft Start Sink Current Under Hard

SENSE

= 0V, V

IMAX

= V

, V

IFB

= 0V

Current Limit

SSHIL

Hard Current Limit Hold Time

SENSE

= 0V, V

IMAX

= 4V, V

IFB

from 5V (Note 4)

500

PWRGD

Power Good Response Time

SENSE

from 0V to Rated V

OUT

0.5

PWRBAD

Power Good Response Time

SENSE

from Rated V

OUT

to 0V

200

500

1000

FAULT

FAULT Response Time

SENSE

from Rated V

OUT

to V

200

500

1000

OT Response Time

OUTEN

, VID0 to VID4 = 0 (Note 10) (Figure 3)

Over-Temperature Trip Point

OUTEN

, VID0 to VID4 = 0 (Note 10) (Figure 3)

1.9

2.12

OTDD

Over-Temperature Driver Disable

OUTEN

, VID0 to VID4 = 0 (Note 10) (Figure 3)

1.6

1.7

1.8

SHDN

Shutdown

OUTEN

, VID0 to VID4 = 0 (Note 10) (Figure 3)

0.8

, t

Driver Rise and Fall Time

(Figure 4)

150

NOL

Driver Nonoverlap Time

(Figure 4)

100

MAX

Maximum G1 Duty Cycle

(Figure 4)

VID0 to VID4 Input High Voltage

VID0 to VID4 Input Low Voltage

0.8

VID0 to VID4 Internal Pull-Up

Resistance

SINK

Digital Output Sink Current

ELECTRICAL CHARACTERISTICS

= 5V, PV

= 12V, T

= 25

C, unless otherwise noted. (Note 3)

The

denotes specifications which apply over the full operating

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: When I

is taken below GND, it will be clamped by an internal

diode. This pin can handle input currents greater than 100mA below GND
without latchup. In the positive direction, it is not clamped to V

or PV

Note 3: All currents into device pins are positive; all currents out of the
device pins are negative. All voltages are referenced to ground unless
otherwise specified.

Note 4: This parameter is guaranteed by correlation and is not tested
directly.

Note 5: The LTC1553 goes into the shutdown mode if VID0 to VID4 are
floating. Due to the internal pull-up resistors, there will be an additional
0.25mA/pin if any of the VID0 to VID4 pins are pulled low.

Note 6: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC1553 operating frequency, supply voltage and the external FETs
used.

Note 7: The open-loop DC gain and transconductance from the SENSE pin to
COMP pin will be (G

ERR

)(1.265/3.3) and (g

mERR

)(1.265/3.3) respectively.

Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be zero.

Note 9: Under typical soft current limit, the net soft start discharge current
will be 60

A (I

SSIL

) + [ 10

A(I

)] = 50

A. The soft start sink-to-source

current ratio is designed to be 6:1.

Note 10: When VID0 to VID4 are all HIGH, the LTC1553 will be forced to
shut down internally. The OUTEN trip voltages are guaranteed by design for
all other input codes.

LTC1553

TYPICAL PERFOR

CE CHARACTERISTICS

OUTPUT VOLTAGE (V)

2.775

NUMBER OF UNITS

100

140

1553 G01

120

2.795

2.825

2.785

2.805

2.815

TOTAL SAMPLE SIZE = 1500

100

Typical 2.8V V

OUT

Distribution

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

2.825

1533 G03

2.820

2.815

2.810

2.805

2.800

2.795

2.790

2.785

2.780

2.775

1 2 3

5 6 7 8 9 10 11 12 13 14

REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
V

= 5V, PV

= 12V, T

= 25

Load Regulation

LOAD CURRENT (A)

EFFICIENCY (%)

100

1533 G02

0.3

REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
V

= 5V, PV

= 12V, V

OUT

= 2.8V,

OUT

= 330

7, L

= 2

A: Q1 = 1

SUD50N03-10

Q2 = 1

SUD50N03-10

B: Q1 = 2

SUD50N03-10

Q2 = 1

SUD50N03-10

NO FAN
Q1 IS MOUNTED ON 1IN

COPPER AREA

Over-Temperature Trip Point
vs Temperature

Efficiency vs Load Current

TEMPERATURE (

OVER-TEMPERATURE TRIP POINT (V)

1.96

2.08

2.10

2.12

1553 G06

1.92

2.04

2.00

1.94

2.06

1.90

2.02

1.98

100

125

INPUT VOLTAGE (V)

4.75

OUTPUT VOLTAGE (V)

2.825

2.820

2.815

2.810

2.805

2.800

2.795

2.790

2.785

2.780

2.775

5.15

1553 G04

4.85

4.95

5.05

5.25

REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
OUTPUT = NO LOAD
T

= 25

Line Regulation

Output Temperature Drift

TEMPERATURE (

OUTPUT VOLTAGE (V)

2.860

2.850

2.840

2.830

2.820

2.810

2.800

2.790

2.780

2.770

2.750

2.660

2.740

1553 G05

100

125

Error Amplifier Open-Loop
DC Gain vs Temperature

Over-Temperature Driver Disable
vs Temperature

TEMPERATURE (

1.60

OVER-TEMPERATURE DRIVER DISABLE (V)

1.62

1.66

1.68

1.70

1.80

1.74

1553 G07

1.64

1.76

1.78

1.72

100

125

Error Amplifier Transconductance
vs Temperature

TEMPERATURE (

1.7

1.9

2.3

1553 G08

1.5

1.3

100

125

1.1

0.9

2.1

ERROR AMPLIFIER TRANSCONDUCTANCE (millimho)

TEMPERATURE (

ERROR AMPLIFIER OPEN-LOOP DC GAIN (dB)

1553 G09

100

125

LTC1553

TYPICAL PERFOR

CE CHARACTERISTICS

Soft Start Source Current
vs Temperature

TEMPERATURE (

250

OSCILLATOR FREQUENCY (kHz)

260

280

290

300

350

320

1553 G10

270

330

340

310

100

125

Oscillator Frequency
vs Temperature

TEMPERATURE (

SOFT START SOURCE CURRENT (

1553 G12

100

125

MAX

Sink Current

vs Temperature

TEMPERATURE (

150

MAX

SINK CURRENT (

160

170

180

220

200

125

1553 G11

210

190

100

Shutdown Supply Current

vs Temperature

TEMPERATURE (

MAXIMUM G1 DUTY CYCLE (%)

1553 G13

100

125

OSCILLATOR FREQUENCY = 300kHz

G1, G2 CAPACITANCE = 1100pF

5500pF
7700pF

2200pF
3300pF

Maximum G1 Duty Cycle
vs Temperature

Operating Supply Current

vs Temperature

TEMPERATURE (

0.9

1.0

1.2

1553 G14

0.8

0.7

100

125

0.6

0.5

1.1

OPERATING SUPPLY CURRENT (mA)

= 5V

OSC

= 300kHz

TEMPERATURE (

SHUTDOWN SUPPLY CURRENT (mA)

225

1553 G15

150

100

250

200

175

125

100

125

GATE CAPACITANCE (pF)

SUPPLY CURRENT (mA)

6000

1553 G16

2000

4000

8000

= 12V

= 25

Supply Current

vs Gate Capacitance

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

0.5

1.5

2.0

2.5

1553 G17

1.0

3.0

Q1 CASE = 90

C, V

OUT

= 2.8V

Q1 = 2

MTD20N03HDL

Q2 = 1

MTD20N03HDL

IMAX

= 2.7k, R

IFB

= 20

SS CAP = 0.01

SHORT-CIRCUIT

CURRENT

Output Over Current Protection

50mV/DIV

5A/DIV

100

s/DIV

1553 G18

Transient Response

LTC1553

G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,
Q2. This output will swing from PV

to GND. It will always

be low when G1 is high or when the output is disabled. To
prevent undershoot during a soft start cycle, G2 is held low
until G1 first goes high.

(Pin 2): Power Supply for G1 and G2. PV

must be

connected to a potential of at least V

+ V

GS(ON)Q1

. If

= 5V, PV

can be generated using a simple charge

pump connected to the switching node between Q1 and
Q2 (see Figure 7), or it can be connected to an auxiliary 12V
supply if one exists. For applications where V

= 12V,

can be generated using a 17V charge pump (see

Figure 9).

GND (Pin 3): Power Ground. GND should be connected to
a low impedance ground plane in close proximity to the
source of Q2.

SGND (Pin 4): Signal Ground. SGND is connected to the
low power internal circuitry and should be connected to
the negative terminal of the output capacitor where it
returns to the ground plane. GND and SGND should be
shorted right at the LTC1553.

(Pin 5): Power Supply. Power for the internal low

power circuity. V

should be wired separately from the

drain of Q1 if they share the same supply. A 10

F bypass

capacitor is recommended from this pin to SGND.

SENSE (Pin 6): Output Voltage Pin. Connect to the positive
terminal of the output capacitor. There is an internal 120k
resistor connected from this pin to SGND. SENSE is a very
sensitive pin; for optimum performance, connect an exter-
nal 0.1

F capacitor from this pin to SGND. By connecting

a small external resistor between the output capacitor and
the SENSE pin, the initial output voltage can be raised
slightly. Since the internal divider has a nominal imped-
ance of 120k

, a 1200

series resistor will raise the

nominal output voltage by 1%. If an external resistor is
used, the value of the 0.1

F capacitor on the SENSE pin

must be greatly reduced or loop phase margin will suffer.
Set a time constant for the RC combination of approxi-
mately 0.1

s. So, for example, with a 1200

resistor, set

C = 83pF. Use a standard 100pF capacitor.

CTIO

MAX

(Pin 7): Current Limit Threshold. Current limit is set

by the voltage drop across an external resistor connected
between the drain of Q1 and I

MAX

. There is a 180

A internal

pull-down at I

MAX

(Pin 8): Current Limit Sense Pin. Connect to the

switching node between the source of Q1 and the drain of
Q2. If I

drops below I

MAX

when G1 is on, the LTC1553

will go into current limit. The current limit circuit can be
disabled by floating I

MAX

and shorting I

to V

through

an external 10k resistor. For V

= 12V, a 15V Zener diode

from I

to GND is recommended to prevent the voltage

spike at I

from exceeding the maximum voltage rating.

SS (Pin 9): Soft Start. Connect to an external capacitor to
implement a soft start function. During moderate overload
conditions, the soft start capacitor will be discharged
slowly in order to reduce the duty cycle. In hard current
limit, the soft start capacitor will be forced low immedi-
ately and the LTC1553 will rerun a complete soft start
cycle. C

must be selected such that during power-up the

current through Q1 will not exceed the current limit value.

COMP (Pin 10): External Compensation. The COMP pin is
connected directly to the output of the error amplifier and
the input of the PWM comparator. An RC + C network is
used at this node to compensate the feedback loop to
provide optimum transient response.

OT (Pin 11): Over-Temperature Fault. OT is an open-drain
output and will be pulled low if OUTEN is less than 2V. If
OUTEN = 0, OT pulls low.

FAULT (Pin 12): Overvoltage Fault. FAULT is an open-
drain output. If V

OUT

reaches 15% above the nominal

output voltage, FAULT will go low and G1 and G2 will be
disabled. Once triggered, the LTC1553 will remain in this
state until the power supply is recycled or the OUTEN pin
is toggled. If OUTEN = 0, FAULT floats or is pulled high by
an external resistor.

PWRGD (Pin 13): Power Good. This is an open-drain
signal to indicate validity of output voltage. A high indi-
cates that the output has settled to within

5% of the rated

output for more than 1ms. PWRGD will go low if the output
is out of regulation for more than 500

s. If OUTEN = 0,

PWRGD pulls low.

LTC1553

CTIO

VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):
Digital Voltage Select. TTL inputs used to set the regulated
output voltage required by the processor (Table 3). There
is an internal 20k

pull-up at each pin. When all five VID

pins are high or floating, the chip will shut down.

OUTEN (Pin 19): Output Enable. TTL input which enables
the output voltage. The external MOSFET temperature can
be monitored with an external thermistor as shown in
Figure 13. When the OUTEN input voltage drops below 2V,

OT trips. As OUTEN drops below 1.7V, the drivers are
internally disabled to prevent the MOSFETs from heating
further. If OUTEN is less than 1.2V for longer than 30

the LTC1553 will enter shutdown mode. The internal
oscillator can be synchronized to a faster external clock by
applying the external clocking signal to the OUTEN pin.

G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET,
Q1. This output will swing from PV

to GND. It will always

be low when G2 is high or the output is disabled.

BLOCK DIAGRA

VID0

VID1

VID2

VID3

VID4

OUTEN 19

COMP

1553 BD

SENSE

PWM

SYSTEM
POWER
DOWN

DISDR

REF

115% V

REF

0.5V

REF

0.7V

REF

HCL MONO

MHCL

REF

+ 5%

DELAY

DAC

LOGIC

MAX

MIN

ERR

MAX

PWRGD

LVC

FAULT

LTC1553

TEST CIRCUITS

Figure 4

12V

0.1

G2 RISE/FALL

G1 RISE/FALL

5000pF

SGND

GND

SENSE

0.1

LTC1553

1553 F04

90%

NOL

50%

10%

50%

90%

50%

10%

10k

OUTEN

PWRGD

FAULT

COMP

SGND

GND

SENSE

0.1

VID0 VID1 VID2 VID3 VID4

LTC1553

MAX

1553 F03

0.1

10k

Figure 3

OUTEN

PWRGD

FAULT

VID0 TO VID4

COMP

SGND

GND

SENSE

Q1*

Q2*

12V

15A

LTC1553

MAX

0.1

1553 F02

0.01

8.2k

100pF

0.1

OUT

C1
150pF

10k

VID0 TO VID4

100pF

1200

*SILICONIX SUD50N03-10

**SANYO 10MV1200GX

COILTRONICS CTX02-13198 OR

PANASONIC 12TS-2R5SP

AVX TPSE337M006R0100

OUT

330

Figure 2

LTC1553

Table 3. Rated Output Voltage (cont)

INPUT PIN

RATED OUTPUT

ID4

ID3

ID2

ID1

ID0

VOLTAGE (V)

FU CTIO TABLES

Table 1. OT Logic

OUTEN (V)

OT*

< 2

> 2

Table 2. PWRGD and FAULT Logic

INPUT

OUTPUT*

OUTEN

SENSE

FAULT

PWRGD

< 95%

> 95%

< 105%

>105%

> 115%

Table 3. Rated Output Voltage

INPUT PIN

RATED OUTPUT

ID4

ID3

ID2

ID1

ID0

VOLTAGE (V)

Disabled

(1.30)

Disabled

(1.35)

Disabled

(1.40)

Disabled

(1.45)

Disabled

(1.50)

Disabled

(1.55)

Disabled

(1.60)

Disabled

(1.65)

Disabled

(1.70)

Disabled

(1.75)

1.80

1.85

1.90

1.95

2.00

2.05

SHDN

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

* With external pull-up resistor

** With respect to the output voltage selected in Table 3 as required by

Intel Specification VRM 8.2

These code selections are disabled in LTC1553

X Don't care

LTC1553

APPLICATIO

S I

FOR

ATIO

OVERVIEW

The LTC1553 is a voltage feedback, synchronous switch-
ing regulator controller (see Block Diagram) designed for
use in high power, low voltage step-down (buck) convert-
ers. It is designed to satisfy the requirements of the Intel
Pentium II power supply specification. It includes an
on-chip DAC to control the output voltage, a PWM genera-
tor, a precision reference trimmed to

1%, two high power

MOSFET gate drivers and all the necessary feedback and
control circuitry to form a complete switching regulator
circuit.

The LTC1553 includes a current limit sensing circuit that
uses the upper external power MOSFET as a current
sensing element, eliminating the need for an external
sense resistor. Once the current comparator, CC, detects
an overcurrent condition, the duty cycle is reduced by
discharging the soft start capacitor through a voltage-
controlled current source. Under severe overloads or
output short circuit conditions, the chip will be repeatedly
forced into soft start until the short is removed, preventing
the external components from being damaged. Under
output overvoltage conditions, the MOSFET drivers will be
disabled permanently until the chip power supply is
recycled or the OUTEN pin is toggled.

OUTEN can optionally be connected to an external nega-
tive temperature coefficient (NTC) thermistor placed near
the external MOSFETs or the microprocessor. Three thresh-
old levels are provided internally. When OUTEN drops to
2V, OT will trip, issuing a warning to the external CPU. If
the temperature continues to rise and the OUTEN input
drops to 1.7V, the G1 and G2 pins will be forced low. If
OUTEN is pulled below 1.2V, the LTC1553 will go into
shutdown mode, cutting the supply current to a minimum.
If thermal shutdown is not required, OUTEN can be con-
nected to a conventional TTL enable signal. The free-
running 300kHz PWM frequency can be synchronized to
a faster external clock connected to OUTEN. Adjusting the
oscillator frequency can add flexibility in the external
component selection. See the Clock Synchronization
section.

Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX com-
parators. If the output is

5% beyond the selected value

for more than 500

s, the PWRGD output will be pulled

low. Once the output has settled within

5% of the

selected value for more than 1ms, PWRGD will return
high.

THEORY OF OPERATION

Primary Feedback Loop

The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance
of approximately 120k

. This divided down voltage is

subtracted from a reference voltage supplied by the DAC
output. The resulting error voltage is amplified by the error
amplifier and the output is compared to the oscillator ramp
waveform by the PWM comparator. This PWM signal
controls the external MOSFETs through G1 and G2. The
resulting chopped waveform is filtered by L

and C

OUT

closing the loop. Loop frequency compensation is achieved
with an external RC + C network at the COMP pin, which is
connected to the output node of the transconductance
amplifier.

MIN, MAX Feedback Loops

Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifier may not respond quickly enough. MIN compares
the feedback signal FB to a voltage 60mV (5%) below the
internal reference. If FB is lower than the threshold of this
comparator, the MIN comparator overrides the ERR
amplifier and forces the loop to full duty cycle which is set
by the internal oscillator typically to 84%. Similarly, the
MAX comparator forces the output to 0% duty cycle if FB
is more than 5% above the internal reference. To prevent
these two comparators from triggering due to noise, the
MIN and MAX comparators' response times are deliber-
ately controlled so that they take two to three microsec-
onds to respond. These two comparators help prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.

LTC1553

APPLICATIO

S I

FOR

ATIO

Soft Start and Current Limit

The LTC1553 includes a soft start circuit which is used for
initial start-up and during current limit operation. The SS
pin requires an external capacitor to GND with the value
determined by the required soft start time. An internal
10

A current source is included to charge the external SS

capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to maxi-
mum duty cycle. The LTC1553 will begin to operate at low
duty cycle as the SS pin rises above about 1.2V (V

COMP

1.8V). As SS continues to rise, Q

turns off and the error

amplifier begins to regulate the output. The MIN compara-
tor is disabled when soft start is active to prevent it from
overriding the soft start function.

The LTC1553 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the I

pin. Note that when V

= 12V, the

pin requires an external Zener to GND to prevent

voltage transients at the switching node between Q1 and
Q2 from damaging internal structures. CC compares the
voltage at I

to the voltage at the I

MAX

pin. As the peak

current rises, the measured voltage across Q1 increases
due to the drop across the R

DS(ON)

of Q1. When the voltage

at I

drops below I

MAX

, indicating that Q1's drain current

has exceeded the maximum level, CC starts to pull current
out of the external soft start capacitor, cutting the duty
cycle and controlling the output current level. The CC
comparator pulls current out of the SS pin in proportion to
the voltage difference between I

and I

MAX

. Under minor

overload conditions, the SS pin will fall gradually, creating
a time delay before current limit takes effect. Very short,
mild overloads may not affect the output voltage at all.
More significant overload conditions will allow the SS pin
to reach a steady state, and the output will remain at a
reduced voltage until the overload is removed. Serious
overloads will generate a large overdrive at CC, allowing it
to pull SS down quickly and preventing damage to the
output components.

By using the R

DS(ON)

of Q1 to measure the output current,

the current limiting circuit eliminates an expensive dis-
crete sense resistor that would otherwise be required. This
helps minimize the number of components in the high
current path. Due to switching noise and variation of
R

DS(ON)

, the actual current limit trip point is not highly

accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuit begins to take effect will vary from unit to unit as the
R

DS(ON)

of Q1 varies.

For a given current limit level, the external resistor from
I

MAX

to V

can be determined by:

IMAX

LMAX

DS ON Q

IMAX

( )(

)

(

) 1

where,

LMAX

LOAD

RIPPLE

LOAD

= Maximum load current

RIPPLE

= Inductor ripple current

(

)( )

( )( )( )

OUT

OSC

= LTC1553 oscillator frequency = 300kHz

= Inductor value

DS(ON)Q1

= Hot on-resistance of Q1 at I

LMAX

IMAX

= Internal 180

A sink current at I

MAX

180

OUT

1553 F05

OUT

IMAX

LTC1553

MAX

Figure 5. Current Limit Setting

LTC1553

Table 4. Recommended Minimum R

IMAX

Resistor (k

) vs Maximum Operating Load Current and External MOSFET Q1

MAXIMUM OPERATING

SUD50N03-10

MTD20N03HDL

LOAD CURRENT (A)

SUD50N03-10

(TWO IN PARALLEL)

MTD20N03HDL

(TWO IN PARALLEL)

2.4

1.2

4.3

2.2

2.7

1.3

5.1

2.7

3.0

1.5

6.2

3.0

3.6

1.8

6.8

3.3

3.9

2.0

7.5

3.6

APPLICATIO

S I

FOR

ATIO

OUTEN and Thermistor Input

The LTC1553 includes a low power shutdown mode,
controlled by the logic at the OUTEN pin. A high at OUTEN
allows the part to operate normally. A low level at OUTEN
stops all internal switching, pulls COMP and SS to ground
internally and turns Q1 and Q2 off. OT and PWRGD are
pulled low, and FAULT is left floating. In shutdown, the
LTC1553 quiescent current will drop to about 130

A. The

remaining current is used to keep the thermistor sensing
circuit at OUTEN alive. Note that the leakage current of
the external MOSFETs may add to the total shutdown
current consumed by the circuit, especially at elevated
temperature.

OUTEN is designed with multiple thresholds to allow it to
also be utilized for over-temperature protection. The power
MOSFET operating temperature can be monitored with an
external negative temperature coefficient (NTC) thermistor
mounted next to the external MOSFET which is expected
to run the hottest often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to V

. Their midpoint

should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Under normal operating conditions, the OUTEN pin should
stay above 2V. All circuits will function normally, and the
OT pin will remain in a high state. If the temperature gets
abnormally high, the OUTEN pin voltage will eventually
drop below 2V. OT will switch to a logic low, providing an
over-temperature warning to the system. As OUTEN drops
below 1.7V, the LTC1553 disables both FET drivers. If

Figure 6. OUTEN Pin as a Thermistor Input

OUT

1553 F06

OUT

5.6k

NTC THERMISTOR

MOUNT IN CLOSE

THERMAL PROXIMITY

TO Q1

LTC1553

PENTIUM II

SYSTEM

OUTEN

OUTEN is less than 1.2V, the LTC1553 will enter shutdown
mode. To activate any of these three modes, the OUTEN
voltage must drop below the respective threshold for
longer than 30

Clock Synchronization

The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
the LTC1553 will decrease. Since the loop gain is inversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
when external synchronization is used.

LTC1553

APPLICATIO

S I

FOR

ATIO

0.1

OUT

1553 F07

OUT

1N5248B
18V

1N5817

OPTIONAL FOR V

> 5V

LTC1553

Figure 7. Doubling Charge Pump

MOSFET Gate Drive

Power for the internal MOSFET drivers is supplied by
PV

. This supply must be above the input supply voltage

by at least one power MOSFET V

GS(ON)

for efficient opera-

tion. This higher voltage can be supplied with a separate
supply, or it can be generated using a simple charge pump
as shown in Figure 7. The 84% typical maximum duty
cycle ensures sufficient off-time to refresh the charge
pump during each cycle. Figure 8 shows a tripling charge
pump, which provides additional V

overdrive to the

external MOSFETs. This circuit can be useful for standard
threshold MOSFETs which demand a higher turn-on volt-
age. An 18V Zener diode (1N5248B) is recommended with
tripler charge pump designs to ensure that PV

never

exceeds the LTC1553's 20V absolute maximum PV

voltage. This becomes more critical as V

rises. With V

= 12V, the doubler circuit of Figure 7 will also exceed the
20V limit. Figure 9 shows an alternate 17V charge pump
derived from both the 5V and 12V supplies.

If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V

and PV

power up from a 0V condition, an internal undervoltage
lockup circuit prevents G1 and G2 from going high until
V

reaches about 3.5V. If V

powers up while PV

is at

ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.

Power MOSFETs

Two N-channel power MOSFETs are required for most
LTC1553 circuits. They should be selected based prima-
rily on threshold and on-resistance considerations. The
required MOSFET threshold should be determined based
on the available power supply voltages and/or the com-
plexity of the gate driver charge pump scheme. In 5V input
designs where a 12V supply is used to power PV

standard MOSFETs with R

DS(ON)

specified at V

= 5V or

6V can be used with good results. However, logic level
devices will improve efficiency. The current drawn from
the 12V supply varies with the MOSFETs used and the
LTC1553 operating frequency, but is generally less than
50mA.

Figure 9. 17V Charge Pump for V

= 12V

0.1

OUT

1553 F09

OUT

12V

VCC

1N5248B
18V

1N5817

LTC1553

0.1

OUT

1553 F08

OUT

1N5248B
18V

1N5817

LTC1553

1N5817

Figure 8. Tripling Charge Pump

LTC1553

APPLICATIO

S I

FOR

ATIO

MAX

should be calculated based primarily on required

efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for Pentium II with a 5V input
and a 2.8V, 11.2A output might allow no more than 4%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
P

MAX

value of:

[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET

and a required R

DS(ON)

of:

DS ON Q

( )

( )(

)

( )( )

( )(

)

(

)( )

1 39

2 8

11 2

0 019

1 39

2 8

11 2

0 025

Note also that while the required R

DS(ON)

values suggest

large MOSFETs, the dissipation numbers are only 1.39W
per device or lesslarge TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions. Siliconix Si4410DY or International Rectifier IRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
face mount devices with R

DS(ON)

values below 0.03

at 5V

of gate drive that work well in LTC1553 circuits. With
higher output voltages, the R

DS(ON)

of Q1 may need to be

significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher P

MAX

value

in the R

DS(ON)

calculations will generally decrease MOSFET

cost and circuit efficiency while increasing MOSFET heat
sink requirements.

The LTC1553 designs that use a 5V V

voltage and a

doubler charge pump to generate PV

will not provide

enough drive voltage to fully enhance standard power
MOSFETs. Under this condition, the effective MOSFET
R

DS(ON)

may be quite high, raising the dissipation in the

FETs and reducing efficiency. Logic level FETs are a better
choice for 5V-only systems as shown in Figure 7 or 12V
input systems using the 17V charge pump of Figure 9.
They can be fully enhanced with the generated charge
pump voltage and will operate at maximum efficiency.
Note that doubler charge pump designs running from
supplies higher than 5V, and all tripler charge pump
designs, should include a Zener clamp diode at PV

prevent transients from exceeding the absolute maximum
rating at that pin. See the MOSFET Gate Drive section for
more charge pump information.

Once the threshold voltage has been selected, R

DS(ON)

should be chosen based on input and output voltage,
allowable power dissipation and maximum required out-
put current. In a typical LTC1553 buck converter circuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:

DC Q

OUT

( )

= -

(

)

The R

DS(ON)

required for a given conduction loss can now

be calculated by rearranging the relation P = I

DC Q

DS ON Q

MAX Q

MAX

MAX Q

OUT

MAX

DS ON Q

MAX Q

MAX

MAX Q

OUT

MAX

( )

[ ]

( )

( )( )

( )

[ ]

( )

(

)( )

LTC1553

APPLICATIO

S I

FOR

ATIO

Table 5. Recommended MOSFETs for LTC1553 Applications

TYPICAL INPUT

DS(ON)

CAPACITANCE

PARTS

AT 25

C (m

)

RATED CURRENT (A)

ISS

(pF)

(

C/W)

JMAX

(

Siliconix SUD50N03-10

15 at 25

3200

1.8

175

TO-252

10 at 75

Siliconix Si4410DY

10 at 25

2700

150

SO-8

8 at 75

Motorola MTD20N03HDL

20 at 25

880

1.67

150

D PAK

16 at 100

SGS-Thomson STD20N03L

20 at 25

2300

2.5

175

D PAK

14 at 100

Motorola MTB75N03HDL

7.5

75 at 25

4025

1.0

150

DD PAK

59 at 100

IRF IRL3103S

56 at 25

1600

1.8

175

DD PAK

40 at 100

IRF IRLZ44

50 at 25

3300

1.0

175

TO-220

36 at 100

Fuji 2SK1388

35 at 25

1750

2.08

150

TO-220

Inductor Selection

The inductor is often the largest component in the LTC1553
design and should be chosen carefully. Inductor value and
type should be chosen based on output slew rate require-
ments, output ripple requirements and expected peak
current. Inductor value is primarily controlled by the
required current slew rate. The maximum rate of rise of
current in the inductor is set by its value, the input-to-
output voltage differential and the maximum duty cycle of
the LTC1553. In a typical 5V input, 2.8V output applica-
tion, the maximum current slew rate will be:

MAX

OUT

(

)

1 83

where L is the inductor value in

H. With proper frequency

compensation, the combination of the inductor and output
capacitor will determine the transient recovery time. In
general, a smaller value inductor will improve transient
response at the expense of increased output ripple voltage
and inductor core saturation rating. A 2

H inductor would

have a 0.9A/

s rise time in this application, resulting in a

5.5

s delay in responding to a 5A load current step. During

this 5.5

s, the difference between the inductor current and

the output current must be made up by the output capaci-
tor, causing a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1

H to 5

H range for most typical 5V input LTC1553

circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.

Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:

RIPPLE

OUT

OSC

(

)( )

( )( )( )

OSC

= LTC1553 oscillator frequency = 300kHz

= Inductor value

Note: Please refer to the manufacturer's data sheet for testing conditions
and detail information.

LTC1553

Solving this equation with our typical 5V to 2.8V applica-
tion with a 2

H inductor, we get:

2 2 0 56

300

( )( )

(

)( )

kHz

P-P

Peak inductor current at 11.2A load:

11 2

12 2

The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductors with gradual saturation characteristics are often
the best choice.

Input and Output Capacitors

A typical LTC1553 design puts significant demands on
both the input and the output capacitors. During constant
load operation, a buck converter like the LTC1553 draws
square waves of current from the input supply at the
switching frequency. The peak current value is equal to the
output load current plus 1/2 peak-to-peak ripple current,
and the minimum value is zero. Most of this current is
supplied by the input bypass capacitor. The resulting RMS
current flow in the input capacitor will heat it up, causing
premature capacitor failure in extreme cases. Maximum
RMS current occurs with 50% PWM duty cycle, giving an
RMS current value equal to I

OUT

/2. A low ESR input

capacitor with an adequate ripple current rating must be
used to ensure reliable operation.

Note that capacitor manufacturers' ripple current ratings
are often based on only 2000 hours (three months)

APPLICATIO

S I

FOR

ATIO

lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer's speci-
fication is recommended to extend the useful life of the
circuit. Lower operating temperature will have the largest
effect on capacitor longevity.

The output capacitor in a buck converter sees much less
ripple current under steady-state conditions than the input
capacitor. Peak-to-peak current is equal to that in the
inductor, usually 10% to 40% of the total load current.
Output capacitor duty places a premium not on power
dissipation but on ESR. During an output load transient,
the output capacitor must supply all of the additional load
current demanded by the load until the LTC1553 can
adjust the inductor current to the new value. Output
capacitor ESR results in a step in the output voltage equal
to the ESR value multiplied by the change in load current.
An 11A load step with a 0.05

ESR output capacitor will

result in a 550mV output voltage shift; this is 19.6% of the
output voltage for a 2.8V supply! Because of the strong
relationship between output capacitor ESR and output
load transient response, the output capacitor is usually
chosen for ESR, not for capacitance value; a capacitor with
suitable ESR will usually have a larger capacitance value
than is needed for energy storage.

Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1553 applications. OS-CON
electrolytic capacitors from SANYO and other manufac-
turers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. AVX TPS series surface mount
devices are popular surge tested tantalum capacitors that
work well in LTC1553 applications.

A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical LTC1553

LTC1553

APPLICATIO

S I

FOR

ATIO

application might exhibit 5A input ripple current. SANYO
OS-CON part number 10SA220M (220

F/10V) capacitors

feature 2.3A allowable ripple current at 85

C; three in

parallel at the input (to withstand the input ripple current)
will meet the above requirements. Similarly, AVX
TPSE337M006R0100 (330

F/6V) have a rated maximum

ESR of 0.1

; seven in parallel will lower the net output

capacitor ESR to 0.014

. For low cost application, SANYO

MV-GX series of capacitors can be used with acceptable
performance.

Feedback Loop Compensation

The LTC1553 voltage feedback loop is compensated at the
COMP pin, attached to the output node of the internal g

error amplifier. The feedback loop can generally be com-
pensated properly with an RC + C network from COMP to
GND as shown in Figure 10a.

Loop stability is affected by the values of the inductor,
output capacitor, output capacitor ESR, error amplifier
transconductance and error amplifier compensation net-
work. The inductor and the output capacitor creates a
double pole at the frequency:

)(C

OUT

)

The ESR of the output capacitor forms a zero at the
frequency:

ESR

(ESR)(C

OUT

)

The compensation network at the error amplifier output is
to provide enough phase margin at the 0dB crossover
frequency for the overall closed-loop transfer function.
The zero and pole from the compensation network are:

)(C

)

and f

)(C1)

respectively.

Figure 10b shows the Bode plot of the overall transfer
function.

The compensation value used in this design is based on
the following criteria: f

= 12f

, f

= f

and f

= 5f

. At

the closed-loop frequency f

, the attenuation due the LC

filter and the input resistor divider is compensated by the
gain of the PWM modulator and the gain of the error
amplifier (g

mERR

)(R

). Although a mathematical approach

to frequency compensation can be used, the added

Figure 10b. Bode Plot of the LTC1553 Overall Transfer Function

Figure 10a. Compensation Pin Hook-Up

20dB/DECADE

LOOP GAIN

ESR

FREQUENCY

1553 F10b

= LTC1553 SWITCHING

FREQUENCY
f

= CLOSED-LOOP CROSSOVER

FREQUENCY

1553 F10

DAC

LTC1553

SENSE

COMP

ERR

LTC1553

APPLICATIO

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FOR

ATIO

the suggested values slightly because of board layout and
operating condition differences.

An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500

F Sanyo MV-GX capacitors

for the output capacitor, Table 8 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.

Table 8. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500

F SANYO MV-GX

Output Capacitors

(

)

(

C1 (pF)

4500

4.3

0.022

270

6000

5.6

0.0047

220

9000

8.2

0.01

150

2.7

4500

0.01

100

2.7

6000

0.01

2.7

9000

0.01

5.6

4500

0.01

5.6

6000

0.0047

5.6

9000

0.0047

VID0 to VID4, PWRGD and FAULT

The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing V

OUT

to step

from a high to a low voltage by changing the VID

pins

quickly can cause FAULT to trip.

Figure 11 shows the relationship between the V

OUT

volt-

age, PWRGD and FAULT. To prevent PWRGD from inter-
rupting the CPU unnecessarily, the LTC1553 has a built-in
t

PWRBAD

delay to prevent noise at the SENSE pin from

toggling PWRGD. The internal time delay is designed to
take about 500

s for PWRGD to go low and 1ms for it to

recover. Once PWRGD goes low, the internal circuitry
watches for the output voltage to exceed 115% of the rated
voltage. If this happens, FAULT will be triggered. Once
FAULT is triggered, G1 and G2 will be forced low immedi-
ately and the LTC1553 will remain in this state until V

power supply is recycled or OUTEN is toggled.

complication of input and/or output filters, unknown
capacitor ESR, and gross operating point changes with
input voltage, load current variations, all suggest a more
practical empirical method. This can be done by injecting
a transient current at the load and using an RC network box
to iterate toward the final compensation values, or by
obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.

Table 6. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 330

F AVX TPS Output

Capacitors

(

)

(

C1 (pF)

990

1.8

0.022

680

1980

3.6

0.01

330

4950

9.1

0.01

120

2.7

990

5.1

0.01

220

2.7

1980

0.01

120

2.7

4950

0.0047

5.6

990

0.01

120

5.6

1980

0.0047

5.6

4950

0.0036

Table 7. Suggested Compensation Network for 12V Input
Application Using Multiple Paralleled 330

F AVX TPS Output

Capacitors

(

)

(

C1 (pF)

990

0.82

0.047

1500

1980

1.5

0.033

820

4950

3.9

0.022

330

2.7

990

2.2

0.033

560

2.7

1980

4.3

0.022

270

2.7

4950

0.01

120

5.6

990

4.3

0.022

270

5.6

1980

8.2

0.010

150

5.6

4950

0.010

Tables 6 and 7 show the suggested compensation com-
ponents for 5V and 12V input applications based on the
inductor and output capacitor values. The values were
calculated using multiple paralleled 330

F AVX TPS series

surface mount tantalum capacitors as the output capaci-
tor. The optimum component values might deviate from

LTC1553

APPLICATIO

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ATIO

disturbances in the LTC1553 and prevents differences
in ground potential from disrupting internal circuit
operation. This connection should then tie into the
ground plane at a single point, preferably at a fairly quiet
point in the circuit such as close to the output capaci-
tors. This is not always practical, however, due to
physical constraints. Another reasonably good point to
make this connection is between the output capacitors
and the source connection of the low side FET Q2. Do
not tie this single point ground in the trace run between
the low side FET source and the input capacitor ground,
as this area of the ground plane will be very noisy.

3. The small signal resistors and capacitors for frequency

compensation and soft start should be located very
close to their respective pins and the ground ends
connected to the signal ground pin through a separate
trace. Do not connect these parts to the ground plane!

4. The V

and PV

decoupling capacitors should be as

close to the LTC1553 as possible. The 10

F bypass

capacitors shown at V

and PV

will help provide

optimum regulation performance.

5. The (+) plate of C

should be connected as close as

possible to the drain of the upper MOSFET. An addi-
tional 1

F ceramic capacitor between V

and power

ground is recommended.

6. The SENSE pin is very sensitive to pickup from the

switching node. Care should be taken to isolate SENSE
from possible capacitive coupling to the inductor switch-
ing signal. A 0.1

F is required between the SENSE pin

and the SGND pin next to the LTC1553.

7. OUTEN is a high impedance input and should be

externally pulled up to a logic HIGH for normal
operation.

8. Kelvin sense I

MAX

and I

at Q1 drain and source pins.

RATED V

OUT

15%

PWRBAD

PWRGD

FAULT

PWRGD

1553 F11

Figure 11. PWRGD and FAULT

LAYOUT CONSIDERATIONS

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1553. These items are also illustrated graphically in
the layout diagram of Figure 12. The thicker lines show the
high current paths. Note that at 10A current levels or
above, current density in the PC board itself is a serious
concern. Traces carrying high current should be as wide
as possible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15

carry 10A.

1. In general, layout should begin with the location of the

power devices. Be sure to orient the power circuitry so
that a clean power flow path is achieved. Conductor
widths should be maximized and lengths minimized.
After you are satisfied with the power path, the control
circuitry should be laid out. It is much easier to find
routes for the relatively small traces in the control
circuits than it is to find circuitous routes for high
current paths.

2. The GND and SGND pins should be shorted right at the

LTC1553. This helps to minimize internal ground

LTC1553

PACKAGE DESCRIPTIO

Dimension in inches (millimeters) unless otherwise noted.

SW Package

20-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

S20 (WIDE) 0396

NOTE 1

0.496 0.512*

(12.598 13.005)

0.394 0.419

(10.007 10.643)

0.037 0.045

(0.940 1.143)

0.004 0.012

(0.102 0.305)

0.093 0.104

(2.362 2.642)

0.050

(1.270)

TYP

0.014 0.019

(0.356 0.482)

TYP

NOTE 1

0.009 0.013

(0.229 0.330)

0.016 0.050

(0.406 1.270)

0.291 0.299**

(7.391 7.595)

0.010 0.029

(0.254 0.737)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

LTC1553

1553f LT/TP 0198 4K · PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1997

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

TELEX: 499-3977

www.linear-tech.com

PWRGD

FAULT

VID0 TO VID4

OUTEN

COMP

SGND

SENSE

Q1*

Q2*

12V

18A

LTC1553

0.1

1553 F14

0.022

6.2k

5.6k

0.1

1N5245B
15V

GND

MAX

5.1k

1000

OUT

330

C1
180pF

PENTIUM

SYSTEM

* MOTOROLA MTD20N03HDL

** SANYO 16MV1000GX

COILTRONICS CTX02-13199

AVX TPSE337M006R0100

1N5248B
18V

1N5817

Figure 14. External Clock Synchronized 12V to 1.8V-3.5V Application

PART NUMBER DESCRIPTION

COMMENTS

LTC1142

Current Mode Dual Step-Down Switching Regulator Controller

Dual Version of LTC1148

LTC1148

Current Mode Step-Down Switching Regulator Controller

Synchronous, V

20V

LTC1149

Current Mode Step-Down Switching Regulator Controller

Synchronous, V

48V, for Standard Threshold FETs

LTC1159

Current Mode Step-Down Switching Regulator Controller

Synchronous, V

40V, for Logic Threshold FETs

LTC1266

Current Mode Step-Up/Down Switching Regulator Controller

Synchronous N- or P-Channel FETs, Comparator/Low-Battery Detector

LTC1430

High Power Step-Down Switching Regulator Controller

Synchronous N-Channel FETs, Voltage Mode

LTC1435

High Efficiency Low Noise Synchronous Step-Down

Drive Synchronous N-Channel, V

36V

Switching Regulator

LTC1438

Dual High Efficiency Low Noise Synchronous Step-Down

Dual LTC1435 with Power-On Reset

Switching Regulator

RELATED PARTS

TYPICAL APPLICATIO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1553CSW

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1553CSW