1
LTC1609
1609fa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LTC1609
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R1
IN
AGND1
R2
IN
R3
IN
NC
CAP
REF
NC
AGND2
NC
NC
SB/BTC
EXT/INT
DGND
V
DIG
V
ANA
PWRD
BUSY
CS
NC
NC
R/C
NC
TAG
NC
DATA
DATACLK
SYNC
+
33.2k
0.1
F
100
ANALOG INPUT
10V TO 10V
2.2
F
+
2.2
F
+
10
F
SERIAL INTERFACE
1609 TA01
5V
200
2.5V
2.5V
The LTC
1609 is a 200ksps, serial sampling 16-bit A/D
converter that draws only 65mW (typical) from a single 5V
supply. This easy-to-use device includes a sample-and-
hold, a precision reference, a switched capacitor succes-
sive approximation A/D and trimmed internal clock.
The input range is specified for bipolar inputs of
10V,
5V and
3.3V and unipolar inputs of 0V to 10V, 0V to 5V
and 0V to 4V. Maximum DC specs include
2LSB INL and
16-bit no missing codes over temperature. It has a typical
signal-to-noise ratio of 87dB.
The ADC has a high speed serial interface. The serial
output data can be clocked out using either the internal
serial shift clock or be clocked out by an external shift
clock. A separate convert start input (R/C) and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
16-Bit, 200ksps, Serial ADC
with Multiple Input Ranges
s
Sample Rate: 200ksps
s
Input Ranges
Unipolar: 0V to 10V, 0V to 5V and 0V to 4V
Bipolar:
10V,
5V and
3.3V
s
Guaranteed No Missing Codes
s
Serial I/O
s
Single 5V Supply
s
Power Dissipation: 65mW Typ
s
Power Down Mode: 50
W
s
SNR: 87dB Typ
s
Operates with Internal or External Reference
s
28-Pin SSOP and 20-Pin SO Packages
s
Improved 2nd Source to ADS7809 and AD977A
s
Industrial Process Control
s
Multiplexed Data Acquisition Systems
s
High Speed Data Acquisition for PCs
s
Digital Signal Processing
200kHz, 16-Bit Serial Sampling ADC Configured for
10V Inputs
, LTC and LT are registered trademarks of Linear Technology Corporation.
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
FREQUENCY (kHz)
0
60
40
0
75
1609 G06
80
100
25
50
100
120
130
20
MAGNITUDE (dB)
f
SAMPLE
= 200kHz
f
IN
= 1kHz
SINAD = 87.2dB
THD = 100.1dB
Nonaveraged 4096 Point FFT Plot
2
LTC1609
1609fa
(Notes 1, 2)
V
ANA
.......................................................................... 7V
V
DIG
to V
ANA
........................................................... 0.3V
V
DIG
........................................................................... 7V
Ground Voltage Difference
DGND, AGND1 and AGND2 ..............................
0.3V
Analog Inputs (Note 3)
R1
IN
, R2
IN
, R3
IN
................................................
25V
CAP ............................ V
ANA
+ 0.3V to AGND2 0.3V
REF .................................... Indefinite Short to AGND2
Momentary Short to V
ANA
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
ORDER PART
NUMBER
LTC1609CG
LTC1609IG
T
JMAX
= 125
C,
JA
= 95
C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R1
IN
AGND1
R2
IN
R3
IN
NC
CAP
REF
NC
AGND2
NC
NC
SB/BTC
EXT/INT
DGND
V
DIG
V
ANA
PWRD
BUSY
CS
NC
NC
R/C
NC
TAG
NC
DATA
DATACLK
SYNC
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Digital Input Voltage (Note 4) ........ DGND 0.3V to 10V
Digital Output Voltage ........ DGND 0.3V to V
DIG
+ 0.3V
Power Dissipation .............................................. 500mW
Operating Ambient Temperature Range
LTC1609AC/LTC1609C ............................ 0
C to 70
C
LTC1609AI/LTC1609I ......................... 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART
NUMBER
LTC1609CSW
LTC1609ISW
LTC1609ACSW
LTC1609AISW
1
2
3
4
5
6
7
8
9
10
TOP VIEW
SW PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
DGND
V
DIG
V
ANA
PWRD
BUSY
CS
R/C
TAG
DATA
DATACLK
SYNC
T
JMAX
= 125
C,
JA
= 130
C/W
The
q
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With external reference (Notes 5, 6).
LTC1609
LTC1609A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution
q
16
16
Bits
No Missing Codes
q
15
16
Bits
Transition Noise
0.9
0.9
LSB
RMS
Integral Linearity Error
(Note 7)
q
3
2
LSB
Differential Linearity Error
q
2
3
1
1.75
LSB
Bipolar Zero Error
External Reference = 2.5V (Note 8), Bipolar Ranges
q
10
10
mV
CO
N
VERTER CHARACTERISTICS
U
3
LTC1609
1609fa
LTC1609
LTC1609A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
S/(N + D)
Signal-to-(Noise
1kHz Input Signal (Note 14)
87.5
85
87.5
dB
+ Distortion) Ratio
10kHz Input Signal
87
87
dB
20kHz, 60dB Input Signal
30
30
dB
THD
Total Harmonic
1kHz Input Signal, First 5 Harmonics
100
100
96
dB
Distortion
10kHz Input Signal, First 5 Harmonics
94
94
dB
Peak Harmonic or
1kHz Input Signal
102
102
dB
Spurious Noise
10kHz Input Signal
94
94
dB
Full-Power Bandwidth
(Note 15)
275
275
kHz
3dB Input Bandwidth
1
1
MHz
Aperture Delay
40
40
ns
Aperture Jitter
Sufficient to Meet AC Specs Sufficient to Meet AC Specs
Transient Response
Full-Scale Step (Note 9)
2
2
s
Overvoltage Recovery
(Note 16)
150
150
ns
LTC1609/LTC1609A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 9)
4.75V
V
ANA
5.25V, 4.75V
V
DIG
5.25V,
q
10, 0V to 5V, etc.
V
(See Tables 1a and 1b)
C
IN
Analog Input Capacitance
10
pF
R
IN
Analog Input Impedance
See Tables 1a and 1b
k
The
q
indicates specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
(Notes 5, 14)
A ALOG I PUT
U
U
DY
A
IC ACCURACY
U
W
LTC1609/LTC1609A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
q
2.470
2.500
2.520
V
V
REF
Output Tempco
I
OUT
= 0
5
ppm/
C
Internal Reference Source Current
1
A
External Reference Voltage for Specified Linearity
(Notes 9, 10)
2.30
2.50
2.70
V
External Reference Current Drain
External Reference = 2.5V (Note 9)
q
100
A
CAP Output Voltage
I
OUT
= 0
2.50
V
The
q
indicates specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 5)
I
N
TER
N
AL REFERE
N
CE CHARACTERISTICS
U
U
U
The
q
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With external reference (Notes 5, 6).
LTC1609
LTC1609A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bipolar Zero Error Drift
Bipolar Ranges
2
2
ppm/
C
Unipolar Zero Error
External Reference = 2.5V, Unipolar Ranges
q
10
10
mV
Unipolar Zero Error Drift
Unipolar Ranges
2
2
ppm/
C
Full-Scale Error Drift
7
7
ppm/
C
Full-Scale Error
External Reference = 2.5V (Notes 12, 13)
q
0.50
0.25
%
Full-Scale Error Drift
External Reference = 2.5V
2
2
ppm/
C
Power Supply Sensitivity
V
ANA
= V
DIG
= V
DD
V
DD
= 5V
5% (Note 9)
8
8
LSB
CO
N
VERTER CHARACTERISTICS
U
4
LTC1609
1609fa
LTC1609/LTC1609A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 5.25V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 4.75V
q
0.8
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
10
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 4.75V
I
O
= 10
A
4.5
V
I
O
= 200
A
q
4.0
V
V
OL
Low Level Output Voltage
V
DD
= 4.75V
I
O
= 160
A
0.05
V
I
O
= 1.6mA
q
0.10
0.4
V
I
SOURCE
Output Source Current
V
OUT
= 0V
10
mA
I
SINK
Output Sink Current
V
OUT
= V
DD
10
mA
The
q
indicates specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
LTC1609/LTC1609A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
1
Convert Pulse Width
(Note 11)
q
40
ns
t
2
R/C, CS to BUSY Delay
C
L
= 25pF
q
80
ns
t
3
BUSY Low Time
q
3
s
t
4
BUSY Delay After End of Conversion
100
ns
t
5
Aperture Delay
5
ns
t
6
Conversion Time
q
3
s
t
7
Acquisition Time
q
2
s
t
6
+ t
7
Throughput Time
q
5
s
t
8
R/C Low to DATACLK Delay
260
ns
t
9
DATACLK Period
150
ns
t
10
DATA Valid Setup Time
q
15
ns
t
11
DATA Valid Hold Time
q
40
ns
t
12
External DATACLK Period
q
50
ns
t
13
External DATACLK High
q
20
ns
t
14
External DATACLK Low
q
20
ns
t
15
R/C, CS to External DATACLK Setup Time
q
15
t
12
ns
t
16
R/C to CS Setup Time
q
10
ns
t
17
External DATACLK to SYNC Delay
q
6
50
ns
t
18
External DATACLK to DATA Valid Delay
q
10
50
ns
t
19
CS to External DATACLK Rising Edge Delay
q
10
ns
t
20
Previous DATA Valid After CS, R/C Low
(Note 9)
q
2.2
s
t
21
BUSY to External DATACLK Setup Time
(Note 9)
q
5
ns
t
22
BUSY Falling Edge to Final External DATACLK
(Notes 10, 17)
q
1.2
s
t
23
TAG Valid Setup Time
q
0
ns
t
24
TAG Valid Hold Time
q
15
ns
The
q
indicates specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 5)
TI I G CHARACTERISTICS
U
W
5
LTC1609
1609fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above V
ANA
=
V
DIG
= V
DD
, they will be clamped by internal diodes. This product can
handle input currents of greater than 100mA below ground or above V
DD
without latch-up.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 200kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a V
IN
input
with respect to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from 0.5 LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Unipolar zero error is the offset voltage measured from
0.5LSB when the output codes flickers between 0000. . .0000 and 0000. .
.0001.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 1.2
s after the
start of the conversion.
Note 12: As measured with fixed 1% resistors shown in Figures 3a and
3b. Adjustable to zero with external potentiometer.
Note 13: Full-scale error is the worst-case of FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of
offset error. For unipolar input ranges full-scale error is the deviation of
the last code transition from ideal divided by the transiton voltage and
includes the effect of offset error.
Note 14: All specifications in dB are referred to a full-scale
5V input.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 16: Recovers to specified performance after (2
FS) input
overvoltage.
Note 17: When data is shifted out during a conversion, with an external
data clock, complete the process within 1.2
s from the start of the
conversion (BUSY falling). This will help keep any external disturbances
from causing an error in the conversion result.
POWER REQUIRE
M
E
N
TS
W
U
LTC1609/LTC1609A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Positive Supply Voltage
(Notes 9, 10)
4.75
5.25
V
I
DD
Positive Supply Current
PWRD = Low
q
13
20
mA
P
DIS
Power Dissipation
PWRD = Low
65
100
mW
PWRD = High
50
W
The
q
indicates specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
6
LTC1609
1609fa
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Typical INL Curve
CODE
0
INL (LSB)
0
0.5
1.0
65535
1609 G04
0.5
1.0
2.0
16384
32768
49152
1.5
2.0
1.5
CODE
0
DNL (LSB)
0
0.5
1.0
65535
1609 G05
0.5
1.0
2.0
16384
32768
49152
1.5
2.0
1.5
FREQUENCY (kHz)
0
60
40
0
75
1609 G06
80
100
25
50
100
120
130
20
MAGNITUDE (dB)
f
SAMPLE
= 200kHz
f
IN
= 1kHz
SINAD = 87.2dB
THD = 100.1dB
Typical DNL Curve
Nonaveraged 4096 Point FFT Plot
SINAD vs Input Frequency
THD vs Input Frequency
FREQUENCY (kHz)
60
75
70
65
95
90
85
80
1609 G07
SINAD (dB)
1
100
10
FREQUENCY (kHz)
110
80
90
100
40
50
60
70
1609 G08
THD (dB)
1
100
10
Supply Current vs Supply Voltage
Change in CAP Voltage
vs Load Current
SUPPLY VOLTAGE (V)
4.5
SUPPLY CURRENT (mA)
13.0
13.5
14.0
5.5
1609 G01
12.5
12.0
11.0
4.75
5.0
5.25
11.5
15.0
14.5
f
SAMPLE
= 200kHz
LOAD CURRENT (mA)
14
0.05
CHANGE IN CAP VOLTAGE (V)
0.04
0.02
0.01
0
0.05
0.02
10
6
4
4
1609 G02
0.03
0.03
0.04
0.01
12
8
2
0
2
RIPPLE FREQUENCY (Hz)
1
10
30
POWER SUPPLY REJECTION (dB)
20
10
0
100
10k
1k
1M
100k
1609 G03
40
50
60
70
f
SAMPLE
= 200kHz
Power Supply Rejection
vs Ripple Frequency
7
LTC1609
1609fa
R1
IN
(Pin 1/Pin 1): Analog Input. See Table 1 and Figure 1
for input range connections.
AGND1 (Pin 2/Pin 2): Analog Ground. Tie to analog ground
plane.
R2
IN
(Pin 3/Pin 3): Analog Input. See Table 1 and Figure 1
for input range connections.
R3
IN
(Pin 4/Pin 4): Analog Input. See Table 1 and Figure 1
for input range connections.
NC (28-Pin SSOP Only--Pins 5, 8, 10, 11, 18, 20, 22,
23): No Connect.
CAP (Pin 5/Pin 6): Reference Buffer Output. Bypass with
2.2
F tantalum capacitor.
REF (Pin 6/Pin 7): 2.5V Reference Output. Bypass with
2.2
F tantalum capacitor. Can be driven with an external
reference.
AGND2 (Pin 7/Pin 9): Analog Ground. Tie to analog
ground plane.
SB/BTC (Pin 8/Pin 12): Select straight binary or two's
complement data output format. Tie pin high for straight
binary or tie low for two's complement format.
EXT/INT (Pin 9/Pin 13): Select external or internal clock
for shifting out the output data. Tie the pin high to
synchronize the output data to the clock that is applied to
the DATACLK pin. If the pin is tied low, a convert command
will start transmitting the output data from the previous
conversion synchronized to 16 clock pulses that are
outputted on the DATACLK pin.
DGND (Pin 10/Pin 14): Digital Ground.
SYNC (Pin 11/Pin 15): Sync Output. If EXT/INT is high,
either a rising edge on R/C with CS low or a falling edge on
CS with R/C high will output a pulse on SYNC synchro-
nized to the external clock applied on the DATACLK pin.
DATACLK (Pin 12/Pin 16): Either an input or an output
depending on the level set on EXT/INT. The output data is
synchronized to this clock. When EXT/INT is high an
external shift clock is applied to this pin. If EXT/INT is taken
PI
N
FU
N
CTIO
N
S
U
U
U
low, 16 clock pulses are output during each conversion.
The pin will stay low between conversions.
DATA (Pin 13/Pin 17): Serial Data Output. The output data
is synchronized to the DATACLK and the format is deter-
mined by SB/BTC. In the external shift clock mode, after 16
bits of data have been shifted out and CS is low and R/C is
high, the level in the TAG pin will be outputted. This can be
used to daisy-chain the serial data output from several
LTC1609s. If EXT/INT is low, the output data is valid on
both the rising and falling edge of the internal shift clock
which is outputted on DATACLK. In between conversions,
DATA will stay at the level of the TAG input when the
conversion was started.
TAG (Pin 14/Pin 19): Tag input is used in the external clock
mode. If EXT/INT is high, digital inputs applied to TAG will
be shifted out on DATA delayed 16 DATACLK pulses as
long as CS is low and R/C is high.
R/C (Pin 15/Pin 21): Read/Convert Input. With CS low, a
falling edge on R/C puts the internal sample-and-hold into
the hold state and starts a conversion. With CS low, a
rising edge on R/C enables the serial output data.
CS (Pin 16/Pin 24): Chip Select. Internally OR'd with R/C.
With R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the serial
output data.
BUSY (Pin 17/Pin 25): Output Shows Converter Status. It
is low when a conversion is in progress. Data valid on the
rising edge of BUSY. CS or R/C must be high when BUSY
rises or another conversion will start without time for
signal acquisition.
PWRD (Pin 18/Pin 26): Power Down Input. If the pin is tied
high, conversions are inhibited and power consumption is
reduced (10
A typ). Results from the previous conversion
are maintained in the output shift register.
V
ANA
(Pin 19/Pin 27): 5V Analog Supply. Bypass to ground
with a 0.1
F ceramic and a 10
F tantalum capacitor.
V
DIG
(Pin 20/Pin 28): 5V Digital Supply. Connect directly
to V
ANA
.
(20-Pin SO/28-Pin SSOP)
8
LTC1609
1609fa
16-BIT CAPACITIVE DAC
COMP
REF BUF
2.5V REF
CAP
(2.5V)
C
SAMPLE
C
SAMPLE
DATA
DATACLK
SYNC
BUSY
CONTROL LOGIC
R/C
PWRD
SB/BTC
EXT/INT
TAG
INTERNAL
CLOCK
CS
ZEROING SWITCHES
V
DIG
V
ANA
R1
IN
R2
IN
R3
IN
REF
AGND1
AGND2
DGND
1609 BD
+
SUCCESSIVE APPROXIMATION
REGISTER
SERIAL INTERFACE
4k
20k
10k
5k
20k
FU
N
CTIO
N
AL BLOCK DIAGRA
U
U
W
APPLICATIO S I FOR ATIO
W
U
U
U
Conversion Details
The LTC1609 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 16-bit serial output. The ADC is complete
with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs. (Please refer to the Digital Interface section for
timing information.)
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register (SAR) is reset. Once a conversion cycle has begun
it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, V
IN
is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
and the comparator offset is nulled by the autozero switches.
In this acquire phase, a minimum delay of 2
s will provide
enough time for the sample-and-hold capacitor to acquire
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches C
SAMPLE
to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
V
DAC
1609 F01
+
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
16-BIT
SHIFT REGISTER
COMPARATOR
SAMPLE
SI
R
IN2
R
IN1
V
IN
Figure 1. LTC1609 Simplified Equivalent Circuit
9
LTC1609
1609fa
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the end of a conversion, the DAC output balances the V
IN
input charge. The SAR contents (a 16-bit data word) that
represents the V
IN
are loaded into the 16-bit output shift
register.
Driving the Analog Inputs
The LTC1609 analog input ranges, along with the nominal
input impedances, are shown in Tables 1a and 1b. The
inputs are overvoltage protected to
25V. The input im-
pedance can get as low as 10k
, therefore, it should be
driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
taken to select an amplifier with adequate accuracy, linear-
ity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1609. More detailed information is available in the
Linear Technology data books and LinearView
TM
CD-ROM.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA sup-
ply current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good
AC/DC specs.
LT1468 - 90MHz, 22V/
s 16-bit accurate amplifier
LT1469 - Dual LT1468
Offset and Gain Adjustments
The LTC1609 is specified to operate with three unipolar
and three bipolar input ranges. Pins R1
IN
, R2
IN
and R3
IN
are connected as shown in Tables 1a and 1b for the
different input ranges. The tables also list the nominal
input impedance for each range. Table 1c shows the
output codes for the ideal input voltages of each of the six
input ranges.
The LTC1609 offset and full-scale errors have been trimmed
at the factory with the external resistors shown in Figures
3a and 3b. This allows for external adjustment of offset and
full scale in applications where absolute accuracy is im-
portant. The offset and gain adjustment circuits for the six
input ranges are also shown in Figures 3a and 3b. To
adjust the offset for a bipolar input range, apply an input
voltage equal to 0.5LSB where 1LSB = (+ FS FS)/
65536 and change the offset resistor so the output code is
changing between 1111 1111 1111 1111 and 0000 0000
0000 0000. The gain is trimmed by applying an input
voltage of + FS 1.5LSB and adjusting the gain trim resis-
tor until the output code is changing between 0111 1111
1111 1110 and 0111 1111 1111 1111. In both cases the
data is in two's complement format (SB/BTC = LOW)
To adjust the offset for a unipolar input range, apply an
input voltage equal to + 0.5LSB where 1LSB = + FS/65536.
Then adjust the offset trim resistor until the output code
changes between 0000 0000 0000 0000 and 0000 0000
0000 0001. To adjust the gain, apply an input voltage equal
to + FS 1.5LSB and vary the gain trimming resistor until
the output code is changing between 1111 1111 1111 1110
and 1111 1111 1111 1111. In the unipolar case, the data
is in straight binary format (SB/BTC = HIGH). Figures 4a
and 4b show the transfer characteristics of the LTC1609.
R1
IN
1000pF
A
IN1
200
R2
IN
1000pF
A
IN2
100
LTC1609
R3
IN
1000pF
A
IN3
1609 F02
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current
5V to
15V supplies. Gain bandwidth product
8MHz. DC applications.
LT1097 - Low cost, low power precision amplifier. 300
A
supply current.
5V to
15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227 - 140MHz video current feedback amplifier. 10mA
supply current.
5V to
15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA sup-
ply current.
5V to
15V supplies. Good AC/DC specs.
LinearView is a trademark of Linear Technology Corporation.
10
LTC1609
1609fa
Figure 3a. Offset/Gain Circuits for Unipolar Input Ranges
Table 1a. Analog Input Range Connections for Figure 3a
ANALOG INPUT
CONNECT R1
IN
CONNECT R2
IN
CONNECT R3
IN
INPUT
RANGE
VIA 200
TO
VIA 100
TO
TO
IMPEDANCE
0V to 10V
AGND
V
IN
AGND
13.3k
0V to 5V
AGND
AGND
V
IN
10k
0V to 4V
V
IN
AGND
V
IN
10.7k
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+
+
2.2
F
2.2
F
33.2k
200
100
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
50k
33.2k
200
100
576k
5V
50k
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
0V TO 10V
0V TO 5V
0V TO 4V
WITHOUT TRIM
INPUT RANGE
WITH TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
V
IN
+
+
2.2
F
2.2
F
33.2k
200
100
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
OFFSET
TRIM
GAIN
TRIM
OFFSET
TRIM
GAIN
TRIM
OFFSET
TRIM
GAIN
TRIM
50k
33.2k
200
100
576k
5V
50k
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
V
IN
+
+
2.2
F
2.2
F
33.2k
100
200
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
1609 F03a
+
2.2
F
50k
33.2k
200
100
576k
5V
50k
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
V
IN
11
LTC1609
1609fa
Figure 3b. Offset/Gain Circuits for Bipolar Input Ranges
Table 1b. Analog Input Range Connections for Figure 3b
ANALOG INPUT
CONNECT R1
IN
CONNECT R2
IN
CONNECT R3
IN
INPUT
RANGE
VIA 200
TO
VIA 100
TO
TO
IMPEDANCE
10V
V
IN
AGND
CAP
22.9k
5V
AGND
V
IN
CAP
13.3k
3.3V
V
IN
V
IN
CAP
10.7k
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+
+
2.2
F
2.2
F
33.2k
100
200
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
50k
33.2k
100
576k
200
5V
50k
OFFSET
TRIM
OFFSET
TRIM
GAIN
TRIM
GAIN
TRIM
OFFSET
TRIM
GAIN
TRIM
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
10V
5V
3.3V
WITHOUT TRIM
INPUT RANGE
WITH TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
V
IN
+
+
2.2
F
2.2
F
33.2k
200
100
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
50k
33.2k
200
100
576k
5V
50k
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
V
IN
+
+
2.2
F
2.2
F
33.2k
100
200
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
1609 F03b
+
2.2
F
50k
33.2k
100
200
576k
5V
50k
5V
LTC1609
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
LTC1609
V
IN
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Table 1c. LTC1609 Output Codes for Ideal Input Voltages
TWO'S COMPLEMENT
STRAIGHT BINARY
DESCRIPTION
ANALOG INPUT
(SB/BTC LOW)
(SB/BTC HIGH)
Full-Scale Range
10V
5V
3.34
0V to 10V
0V to 5V
0V to 4V
Least Significant Bit
305
V
153
V
102
V
153
V
76
V
61
V
+Full Scale (FS 1LSB) 9.999695V 4.999847V
3.339898V
9.999847V 4.999924V 3.999939V
0111 1111 1111 1111
1111 1111 1111 1111
Midscale
0V
0V
0V
5V
2.5V
2V
0000 0000 0000 0000
1000 0000 0000 0000
1LSB Below Midscale
305
V
153
V
102
V
4.999847V 2.499924V 1.999939V
1111 1111 1111 1111
0111 1111 1111 1111
Full Scale
10V
5V
3.340000V
0V
0V
0V
1000 0000 0000 0000
0000 0000 0000 0000
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO'S COMPLIMENT)
1
LSB
1609 F04a
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 1LSB
FSR/2
FSR = +FS FS
1LSB = FSR/65536
INPUT VOLTAGE (V)
OUTPUT CODE
1609 F04b
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS 1LSB
0V
1LSB = FS/65536
Figure 4a. LTC1609 Bipolar Transfer Characteristics
Figure 4b. LTC1609 Unipolar Transfer Characteristics
The ideal
FS value for the
3.3V range is 3.340000V 1LSB
and 3.340000V, respectively. The external 33.2k resistor
that is connected between the CAP pin and the R2
IN
pin,
slightly attenuates the input signal applied to R2
IN
. With-
out the 33.2k resistor the
FS value would be 3.333333V
1LSB and 3.333333V (zero volt offset), respectively.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example in Figure 5 the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.9LSB.
Figure 5. Histogram for 4096 Conversions
CODE
3
0
COUNT
500
1000
1500
2000
2
1
0
1
1609 F05
2
3
13
LTC1609
1609fa
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Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC's frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC's spectral content can be examined
for frequencies outside the fundamental. Figure 6 shows
a typical LTC1609 FFT plot which yields a SINAD of
87.2dB and THD of 100dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 6 shows a typical SINAD of 87.2dB with
a 200kHz sampling rate and a 1kHz input.
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the
second through Nth harmonics.
Internal Voltage Reference
The LTC1609 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC scales
with V
REF
. The output of the reference is connected to the
input of a unity-gain buffer through a 4k resistor (see
Figure 7). The input to the buffer or the output of the
reference is available at REF. The internal reference can be
overdriven with an external reference if more accuracy is
needed. The buffer output drives the internal DAC and is
available at CAP. The CAP pin can be used to drive a steady
DC load of less than 2mA. Driving an AC load is not
recommended because it can cause the performance of
the converter to degrade.
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2
F tantalum).
Figure 6. LTC1609 Nonaveraged 4096 Point FFT Plot
S
S
+
1609 F07
INTERNAL
CAPACITOR
DAC
BANDGAP
REFERENCE
V
ANA
4k
2.2
F
CAP
(2.5V)
2.2
F
REF
(2.5V)
6
7
Figure 7. Internal or External Reference Source
FREQUENCY (kHz)
0
60
40
0
75
1609 F06
80
100
25
50
100
120
130
20
MAGNITUDE (dB)
f
SAMPLE
= 200kHz
f
IN
= 1kHz
SINAD = 87.2dB
THD = 100.1dB
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD
V
V
V
V
V
N
=
+
+
+
20
2
2
3
2
4
2
2
1
log
...
14
LTC1609
1609fa
Power Shutdown
When the PWRD pin is tied high, power consumption
drops to a typical value of 50
W from a specified maxi-
mum of 100mW. In the power shutdown mode, the result
from the previous conversion is still available in the
internal shift register, assuming the data had not been
clocked out before going into power shutdown.
The internal reference buffer and the reference are shut
down, so the power-up recovery time will be dependent
upon how fast the bypass capacitors on these pins can be
charged. If the internal reference is used, the 4k resistor in
series with the output and the external bypass capacitor,
typically 2.2
F, will be the main time constant for the
power-up recovery time. If an external reference is used,
the reference buffer output will be able to ramp from 0V to
2.5V in 1ms, while charging a typical bypass capacitor of
2.2
F. The recovery time will be less if the bypass capaci-
tor has not completely discharged.
DIGITAL INTERFACE
Internal Conversion Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 2.7
s. No external adjust-
ments are required and, with the typical acquisition time of
1.5
s, throughput performance of 200ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
The conversion result is clocked out serially on the DATA
pin. It can be synchronized by using the internal data clock
or by using an external clock provided by the user. Tying
the EXT/INT pin high puts the LTC1609 in the external
clock mode and the DATACLK pin is a digital input. Tying
the EXT/INT pin low puts the part in the internal clock mode
and the DATACLK pin becomes a digital output.
Internal Clock Mode
With the EXT/INT pin tied low, the LTC1609 provides the
data clock on the DATACLK pin. The timing diagram is
shown in Figure 8. Typically, CS is tied low and the R/C
pin is used to start a conversion. During the conversion
a 16-bit word will be shifted out MSB-first on the DATA
pin. This word represents the result from the previous
conversion. The DATACLK pin outputs 16 clock pulses
used to synchronize the data. The output data is valid on
both the rising and falling edges of the clock. After the
LSB bit has been clocked out, the DATA pin will take on
the state of the TAG pin at the start of the conversion. The
DATACLK pin goes low until the next conversion is
requested. The data clock is derived from the internal
conversion clock. To avoid errors from occurring during
the current conversion, minimize the loading on the
DATACLK pin and the DATA pin. For the best conversion
results the external clock mode is recommended.
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Figure 8. Serial Data Timing Using Internal Clock (CS, EXT/INT and TAG Tied Low)
t
2
t
10
t
1
t
11
t
3
B14
B13
B2
B1
B0
1609 F08
B15
(MSB)
BUSY
DATA
DATACLK
R/C
2
3
14
15
16
1
t
8
t
9
15
LTC1609
1609fa
External Clock Mode
With the EXT/INT pin tied high, the DATACLK pin becomes
a digital input and the LTC1609 can accept an externally
supplied data clock. There are several ways in which the
conversion results can be clocked out. The data can be
clocked out during or after a conversion with a continuous
or discontinuous data clock. Figures 9 to 12 show the
timing diagram for each of these methods.
External Discontinuous Data Clock Data Read
After the Conversion
Figure 9 shows how the result from the current conver-
sion can be read out after the conversion has been
completed. The externally supplied data clock is running
discontinuously. R/C is used to initiate a conversion with
CS tied low. The conversion starts on the falling edge of
R/C. R/C should be returned high within 1.2
s to prevent
the transition from disturbing the conversion. After the
conversion has been completed (BUSY returning high), a
pulse on the SYNC pin will be generated on the rising edge
of DATACLK #0. The SYNC output can be captured on the
falling edge of DATACLK #0 or on the rising edge of
DATACLK #1. After the rising edge of DATACLK #1, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #1 or on the rising edge of DATACLK #2. The
LSB will be valid on the falling edge of DATACLK #16 or the
rising edge of DATACLK #17. After the rising edge of
DATACLK #17 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #1.
A minimum of 17 clock pulses are required if the data is
captured on falling clock edges.
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will
not degrade the 200kHz throughput. This method mini-
mizes the possible external disturbances that can occur
while a conversion is in progress and will yield the best
performance.
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Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion
0
1
2
3
15
16
17
TAG0
TAG
DATA
SYNC
BUSY
R/C
EXTERNAL
DATACLK
TAG1
TAG2
TAG3
TAG15
B1
B14
B13
B15
(MSB)
B0
TAG0
TAG1
TAG2
TAG16
TAG17
TAG18
TAG19
1606 F09
t
23
t
24
t
18
t
17
t
3
t
2
t
21
t
1
t
13
t
14
t
12
t
12
16
LTC1609
1609fa
External Data Clock Data Read After the Conversion
Figure 10 shows how the result from the current conver-
sion can be read out after the conversion has been com-
pleted. The externally supplied data clock is running
continuously. CS and R/C are first used together to initiate
a conversion and then CS is used to read the result. The
conversion starts on the falling edge of CS with R/C low.
Both CS and R/C should be returned high within 1.2
s to
prevent the transition from disturbing the conversion.
After the conversion has been completed (BUSY returning
high), a pulse on the SYNC pin will be generated after the
first rising edge of DATACLK #1 that occurs after CS goes
low (R/C high). The SYNC output can be captured on the
falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. After the rising edge of DATACLK #2, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #2 or on the rising edge of DATACLK #3. The
LSB will be valid on the falling edge of DATACLK #17 or the
rising edge of DATACLK #18. After the rising edge of
DATACLK #18 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #2.
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will not
degrade the 200kHz throughput.
External Discontinuous Data Clock Data Read
During the Conversion
Figure 11 shows how the result from the previous conver-
sion can be read out during the current conversion. The
externally supplied data clock is running discontinuously.
R/C is used to initiate a conversion with CS tied low. The
conversion starts on the falling edge of R/C. R/C should be
returned high within 1.2
s to prevent the transition from
disturbing the conversion. A pulse on the SYNC pin will be
generated on rising edge of DATACLK #0. The SYNC
output can be captured on the falling edge of DATACLK #0
or on the rising edge of DATACLK #1. After the rising edge
of DATACLK #1, the SYNC output will go low and the MSB
will be clocked out on the DATA pin. This bit can be latched
on the falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. The LSB will be valid on the falling edge of
DATACLK #16. Another clock pulse would be needed if the
LSB is captured on a rising edge. A minimum of 17 clock
pulses are required if the data is captured on falling clock
edges.
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0
1
2
3
4
17
18
TAG0
TAG
DATA
SYNC
BUSY
R/C
CS
EXTERNAL
DATACLK
TAG1
TAG2
TAG15
B1
B14
B15
(MSB)
B0
TAG0
TAG1
TAG16
TAG17
TAG18
TAG19
1606 F10
t
23
t
24
t
18
t
17
t
3
t
2
t
16
t
16
t
15
t
13
t
14
t
1
t
12
t
19
t
12
Figure 10. Conversion and Read Timing with External Clock (EXT/INT Tied High). Read After Conversion
17
LTC1609
1609fa
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DATA
SYNC
BUSY
R/C
B1
B14
B15
(MSB)
B0
1606 F11
t
17
t
18
t
3
t
2
t
1
t
21
t
22
t
15
0
1
2
15
16
EXTERNAL
DATACLK
t
13
t
14
t
12
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2
s from the start of the conver-
sion. Using the maximum data clock frequency of 20MHz
will ensure this condition is met.
External Data Clock Data Read During the Conversion
Figure 12 shows how the result from the previous conver-
sion can be read out during the current conversion. The
externally supplied data clock is running continuously. CS
and R/C are used to initiate a conversion and read the data
from the previous conversion. The conversion starts on
the falling edge of CS after R/C is low. A pulse on the SYNC
pin will be generated on the first rising edge of DATACLK
#1 after R/C has returned high. The SYNC output can be
captured on the falling edge of DATACLK #1 or on the
rising edge of DATACLK #2. After the rising edge of
DATACLK #2 the SYNC output will go low and the MSB will
be clocked out on the DATA pin. This bit can be latched on
the falling edge of DATACLK #2 or on the rising edge of
DATACLK #3. The LSB will be valid on the falling edge of
DATACLK #17 or the rising edge of DATACLK #18. After
the rising edge of DATACLK #18 the DATA pin will take on
the value of the TAG pin that occurred at the rising edge of
DATACLK #2.
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2
s from the start of the conver-
sion. Using the maximum data clock frequency of 20MHz
will ensure this condition is met. Since there is no through-
put penalty for clocking the data out after the conversion,
clocking the data out during the conversion is not recom-
mended.
Use of the TAG Input
The TAG input pin is used to daisy-chain multiple convert-
ers. This is useful for applications where hardware con-
straints may limit the number of lines needed to interface
to a large number of converters. This mode of operation
works only using the external clock method of shifting out
the data.
Figure 13 shows how this feature can be used. R/C, CS and
the DATACLK are tied together on both LTC1609s. CS can
be grounded if a discontinuous data clock is used. A falling
edge on R/C will allow both LTC1609s to capture their
respective analog input signals simultaneously. Once the
conversion has been completed the external data clock
DCLK is started. The MSB from device #1 will be valid after
the rising edge of DCLK #1. Once the LSB from device #1
has been shifted out on the rising edge of DCLK #16, a null
Figure 11. Conversion and Read Timing Using a Discontinuous Data Clock (EXT/INT Tied High, CS Tied Low).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2
s
18
LTC1609
1609fa
TAG0
TAG
DATA
SYNC
BUSY
R/C
CS
TAG1
TAG2
TAG3
TAG15
B1
B14
B13
B15
(MSB)
B0
TAG0
TAG1
TAG16
TAG17
TAG18
TAG19
1606 F12
t
23
t
24
t
17
t
18
t
3
t
2
t
16
t
15
t
12
0
1
2
3
4
16
17
18
EXTERNAL
DATACLK
t
13
t
14
t
12
t
19
Figure 12. Conversion and Read Timing Using an External Data Clock (EXT/INT Tied High).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2
s
APPLICATIO S I FOR ATIO
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DATA
CS
R/C
DCLK
DCLK IN
R/C IN
CS IN
TAG
LTC1609
#2
DATA
CS
R/C
DCLK
TAG
DATA OUT
1609 F13
LTC1609
#1
Figure 13. Two LTC1609s Cascaded
Together Using the TAG Input
bit will be shifted out on the following clock pulse before
the MSB from device #2 becomes available (Figure 14).
The reason for this is the MSB from device #2 will not be
valid soon enough to meet the minimum setup time of
device #1's TAG input. A minimum of 34 clock pulses are
needed to shift out the results from both LTC1609s
assuming the data is captured on the falling clock edge.
Using the highest frequency permitted for DATACLK
(20MHz), a 200kHz throughput can still be achieved.
19
LTC1609
1609fa
Output Data Format
The SB/BTC pin controls the format of the serial digital
output word. With the pin tied high the format is straight
binary. With the pin tied low the data format is two's
complement. See Table 1c.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1609, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
APPLICATIO S I FOR ATIO
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B15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
R/C
BUSY
DCLK
DATA
OUT
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
DEVICE DATA #1
DEVICE DATA #2
B2
B1
B0
NULL
BIT
B14
B13
B12
B11
B10
1609 F14
B15
Figure 14. Data Output from Cascading Two (CS = Low, TAG (#2) = Low) LTC1609s Together
Pay particular attention to the design of the analog and
digital ground planes. Placing the bypass capacitor as
close as possible to the V
DIG
and V
ANA
pins, the REF pin
and reference buffer output is very important. Low imped-
ance common returns for these bypass capacitors are
essential to low noise operation of the ADC, and the foil
width for these tracks should be as wide as possible. Also,
since any potential difference in grounds between the
signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedance as much as pos-
sible. The digital output latches and the onboard sampling
clock have been placed on the digital ground plane. The
two ground planes are tied together at the power supply
ground connection.
A "postage stamp" (1.6in
1.5in) evaluation board is
available and allows fast in-situ evaluation of the LTC1609.
See Figures 15a through 15d, inclusive.
20
LTC1609
1609fa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LTC1609
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R1
IN
AGND1
R2
IN
R3
IN
NC
CAP
REF
NC
AGND2
NC
NC
SB/BTC
EXT/INT
DGND
V
DIG
V
ANA
PWRD
BUSY
CS
NC
NC
R/C
NC
TAG
NC
DATA
DATACLK
SYNC
R4
200
E15
R4
E16
R5
E17
R6
E1
R3
IN
R5
100
R6
33k
1609 F15a
JP2
E2
GND
JP1
5V
C1
10
F
E8
5V
E13
PWRD
E12
CS
E4
RC
E14
GND
C7
0.1
F
C2
1000pF
C3
1000pF
C4
1000pF
C6
2.2
F
C5
2.2
F
R1 10k
R2 10k
R3 10k
E3
BUSY
E11
TAG
E5
DATA
E7
SYNC
E10
GND
E6
DATACLK
APPLICATIO S I FOR ATIO
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Figure 15a. LTC1609 "Postage Stamp" Evaluation Circuit Schematic
21
LTC1609
1609fa
APPLICATIO S I FOR ATIO
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Figure 15b. LTC1609 "Postage Stamp" Evaluation Board
Silkscreen (2
Actual Size)
Figure 15c. LTC1609 "Postage Stamp" Evaluation Board
Top Metal Layer (2
Actual Size)
Figure 15d. LTC1609 "Postage Stamp" Evaluation Board
Bottom Metal Layer (2
Actual Size)
22
LTC1609
1609fa
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
200
100
787k
LTC1609
OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
200
100
787k
LTC1609
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
200
100
787k
LTC1609
V
IN
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
100
33.2k
33.2k
787k
200
LTC1609
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
+
2.2
F
200
100
787k
LTC1609
V
IN
+
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
2.2
F
1609 F16
+
2.2
F
33.2k
100
200
787k
LTC1609
V
IN
33.2k
33.2k
0.1
F
OFFSET
TRIM
GAIN
TRIM
5V
LTC1662
CS/LD
SCK
SDI
REF
CS/LD
SCK
SDI
V
OUTA
GND
V
CC
V
OUTB
33.2k
0V TO 10V
0V TO 5V
0V TO 4V
10V
5V
3.3V
APPLICATIO S I FOR ATIO
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Figure 16. Digitally-Controlled Offset and Full-Scale Adjust Circuits Using
the LTC1662 Dual 10-Bit V
OUT
DAC (Adjust Offset First at 0V, Then Adjust Gain)
23
LTC1609
1609fa
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PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G28 SSOP 0501
.13 .22
(.005 .009)
0
8
.55 .95
(.022 .037)
5.20 5.38**
(.205 .212)
7.65 7.90
(.301 .311)
1
2 3
4
5
6 7 8
9 10 11 12
14
13
10.07 10.33*
(.397 .407)
25
26
22 21 20 19 18 17 16 15
23
24
27
28
1.73 1.99
(.068 .078)
.05 .21
(.002 .008)
.65
(.0256)
BSC
.25 .38
(.010 .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24
LTC1609
1609fa
LINEAR TECHNOLOGY CORPORATION 2000
LT/TP 0302 1.5K REV A PRINTED IN THE USA
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
Low Power 400ksps 14-Bit ADC
20mW, Single 5V or
5V, Serial I/O
LTC1418
Low Power 200ksps 14-Bit ADC
15mW, Single 5V or
5V, Serial/Parallel I/O
LTC1595/LTC1596
16-Bit Mulitplying DACs
Low Glitch, Serial I/O, SO-8/S16 Packages
LTC1597
16-Bit Mulitplying DAC
4-Quadrant Resistors On-Chip, Low Glitch, Parallel I/O
LTC1604
16-Bit 333ksps Sampling ADC
2.5V Input, 90dB SINAD, 100dB THD, Parallel I/O
LTC1605
Low Power 100ksps 16-Bit ADC
Single 5V,
10V Input
LTC1605-1
Low Power 100ksps 16-Bit ADC
Single 5V, 0V to 4V Input
LTC1605-2
Low Power 100ksps 16-Bit ADC
Single 5V,
4V Input
LTC1606
Low Power 250ksps 16-Bit ADC
Single 5V,
10V Input, Parallel I/O
LTC1608
16-Bit 500ksps Sampling ADC
2.5V Input, Pin Compatible with LTC1604
LTC1650
16-Bit
5V Voltage Output DAC
Low Glitch, 4
s Settling Time, Serial I/O
LTC1655/LTC1655L
16-Bit Single 5V/3V Voltage Output DACs
SO-8 Package, Micropower, Serial I/O
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
U
PACKAGE DESCRIPTIO
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
S20 (WIDE) 1098
NOTE 1
0.496 0.512*
(12.598 13.005)
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
0.394 0.419
(10.007 10.643)
9
10
11
12
0.037 0.045
(0.940 1.143)
0.004 0.012
(0.102 0.305)
0.093 0.104
(2.362 2.642)
0.050
(1.270)
BSC
0.014 0.019
(0.356 0.482)
TYP
0
8
TYP
NOTE 1
0.009 0.013
(0.229 0.330)
0.016 0.050
(0.406 1.270)
0.291 0.299**
(7.391 7.595)
45
0.010 0.029
(0.254 0.737)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
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