1
LT4250L/LT4250H
4250lhf
V
EE
AND
DRAIN
20V/DIV
I
D
(Q1)
5A/DIV
500
s/DIV
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Negative 48V
Hot Swap Controller
s
Allows Safe Board Insertion and Removal
from a Live 48V Backplane
s
Circuit Breaker Immunity to Voltage Steps and
Current Spikes
s
Programmable Inrush and
Short-Circuit Current Limits
s
Pin Compatible with LT1640L/LT1640H
s
Operates from 20V to 80V
s
Programmable Overvoltage Protection
s
Programmable Undervoltage Lockout
s
Power Good Control Output
s
Bell-Core Compatible ON/OFF Threshold
The LT
4250L/LT4250H are 8-pin, negative 48V Hot Swap
TM
controllers that allow a board to be safely inserted and
removed from a live backplane. Inrush current is limited to
a programmable value by controlling the gate voltage of an
external N-channel pass transistor. The pass transistor is
turned off if the input voltage is less than the program-
mable undervoltage threshold or greater than the over-
voltage threshold. A programmable current limit protects
the system against shorts. After a 500
s timeout the
current limit activates the electronic circuit breaker. The
PWRGD (LT4250L) or PWRGD (LT4250H) signal can be
used to directly enable a power module. The LT4250L is
designed for modules with a low enable input and the
LT4250H for modules with a high enable input.
The LT4250L/LT4250H are available in 8-pin PDIP and SO
packages.
s
Central Office Switching
s
48V Distributed Power Systems
s
Negative Power Supply Control
Hot Swap is a trademark of Linear Technology Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Voltage Step On Input Supply
V
EE
V
DD
LT4250L
SENSE
C1
470nF
25V
C2
15nF
100V
C3
0.1
F
100V
C4
100
F
100V
Q1
IRF530
R2
10
5%
R3
1k, 5%
R4
549k
1%
R6
10k
1%
R1
0.02
5%
4
OV
48V RTN
48V RTN
(SHORT PIN)
3
2
OV =
71V
*
* DIODES INC. SMAT70A
THESE COMPONENTS ARE APPLICATION
SPECIFIC AND MUST BE SELECTED BASED
UPON OPERATING CONDITIONS AND DESIRED
PERFORMANCE. SEE APPLICATIONS
INFORMATION.
UV =
38.5V
UV
5
6
8
7
1
GATE
DRAIN
PWRGD
4250 TA01
V
OUT
+
SENSE
+
TRIM
SENSE
V
OUT
V
IN
ON/OFF
LUCENT
JW050A1-E
V
IN
+
2
9
5V
8
7
6
5
1
4
+
C5
100
F
16V
+
48V
INPUT 1
48V
INPUT 2
UV
RELEASE
AT 43V
R5
6.49k
1%
0.1
F
10V
2
LT4250L/LT4250H
4250lhf
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
Supply Voltage (V
DD
V
EE
) .................... 0.3V to 100V
PWRGD, PWRGD Pins ........................... 0.3V to 100V
SENSE, GATE Pins .................................... 0.3V to 20V
UV, OV Pins .............................................. 0.3V to 60V
DRAIN Pin .................................................. 2V to 100V
Maximum Junction Temperature ......................... 125
C
Operating Temperature Range
LT4250LC/LT4250HC ............................. 0
C to 70
C
LT4250LI/LT4250HI .......................... 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
(Note 1), All Voltages Referred to V
EE
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 2), V
DD
= 48V, V
EE
= 0V unless otherwise noted.
W
U
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
S8 PART MARKING
LT4250LCN8
LT4250LCS8
LT4250LIN8
LT4250LIS8
4250L
4250LI
T
JMAX
= 125
C,
JA
= 120
C/W (N8)
T
JMAX
= 125
C,
JA
= 150
C/W (S8)
1
2
3
4
8
7
6
5
TOP VIEW
V
DD
DRAIN
GATE
SENSE
PWRGD
OV
UV
V
EE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
ORDER PART
NUMBER
S8 PART MARKING
LT4250HCN8
LT4250HCS8
LT4250HIN8
LT4250HIS8
4250H
4250HI
T
JMAX
= 125
C,
JA
= 120
C/W (N8)
T
JMAX
= 125
C,
JA
= 150
C/W (S8)
1
2
3
4
8
7
6
5
TOP VIEW
V
DD
DRAIN
GATE
SENSE
PWRGD
OV
UV
V
EE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
Consult LTC Marketing for parts specified with wider operating temperature ranges.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC
V
DD
Supply Voltage Operating Range
q
20
80
V
I
DD
Supply Current
UV = 3V, OV = V
EE
, SENSE = V
EE
q
1.6
5
mA
V
UVL
Undervoltage Lockout
q
15.4
V
V
CL
Current Limit Trip Voltage
V
CL
= (V
SENSE
V
EE
)
q
40
50
60
mV
I
PU
GATE Pin Pull-Up Current
Gate Drive On, V
GATE
= V
EE
q
30
45
60
A
I
PD
GATE Pin Pull-Down Current
Gate Drive OFF
24
50
70
mA
I
SENSE
SENSE Pin Current
V
SENSE
= 50mV
20
A
V
GATE
External Gate Drive
(V
GATE
V
EE
), 20V
V
DD
80V
q
10
13.5
18
V
V
UVH
UV Pin High Threshold Voltage
UV Increasing
q
1.240
1.255
1.270
V
V
UVL
UV Pin Low Threshold Voltage
UV Decreasing
q
1.105
1.125
1.145
V
V
UVHY
UV Pin Hysteresis
130
mV
I
INUV
UV Pin Input Current
V
UV
= V
EE
q
0.02
0.5
A
V
OVH
OV Pin High Threshold Voltage
OV Increasing
q
1.235
1.255
1.275
V
V
OVL
OV Pin Low Threshold Voltage
OV Decreasing
q
1.210
1.235
1.255
V
3
LT4250L/LT4250H
4250lhf
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 2), V
DD
= 48V, V
EE
= 0V unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.3
1.4
1.5
60
100
1640 G01
1.2
1.1
0
20
40
80
1.6
1.7
1.8
T
A
= 25
C
Supply Current vs Supply Voltage
TEMPERATURE (
C)
50
25
1.0
SUPPLY CURRENT (mA)
1.1
1.2
1.3
1.4
1.6
0
25
50
75
1640 G02
100
1.5
V
DD
= 48V
Supply Current vs Temperature
SUPPLY VOLTAGE (V)
0
6
GATE VOLTAGE (V)
7
9
10
11
40
80
100
15
1640 G03
8
20
60
12
13
14
T
A
= 25
C
Gate Voltage vs Supply Voltage
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OVHY
OV Pin Hysteresis
20
mV
I
INOV
OV Pin Input Current
V
OV
= V
EE
q
0 .03
0.5
A
V
DL
DRAIN Low Threshold
V
DRAIN
V
EE
, DRAIN Decreasing
1.1
1.6
2.3
V
V
GH
GATE High Threshold
V
GATE
V
GATE
Decreasing
1.3
V
I
DRAIN
Drain Input Bias Current
V
DRAIN
= 48V
q
10
80
500
A
V
OL
PWRGD Output Low Voltage
PWRGD (LT4250L), (V
DRAIN
V
EE
) < V
DL
I
OUT
= 1mA
q
0.48
0.8
V
I
OUT
= 5mA
q
1.2
3.0
V
PWRGD Output Low Voltage
PWRGD (LT4250H), V
DRAIN
= 5V
(PWRGD DRAIN)
I
OUT
= 1mA
q
0.75
1.0
V
I
OH
Output Leakage
PWRGD (LT4250L), V
DRAIN
= 48V, V
PWRGD
= 80V
q
0.05
10
A
PWRGD (LT4250H), V
DRAIN
= 0V, V
PWRGD
= 80V
q
0.05
10
A
AC
t
PHLOV
OV High to GATE Low
Figures 1a, 2
1.7
s
t
PHLUV
UV Low to GATE Low
Figures 1a, 3
1.5
s
t
PLHOV
OV Low to GATE High
Figures 1a, 2
5.5
s
t
PLHUV
UV High to GATE High
Figures 1a, 3
6.5
s
t
PHLSENSE
SENSE High to Gate Low
Figures 1a, 4a
1
3
s
t
PHLCB
Current Limit to GATE Low
Figures 1b, 4b
500
s
t
PHLDL
DRAIN Low to PWRGD Low
(LT4250L) Figures 1a, 5a
1
s
DRAIN Low to (PWRGD DRAIN) High
(LT4250H) Figures 1a, 5a
1
s
t
PHLGH
GATE High to PWRGD Low
(LT4250L) Figures 1a, 5b
1.5
s
GATE High to (PWRGD DRAIN) High
(LT4250H) Figures 1a, 5b
1.5
s
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V
EE
unless otherwise
specified.
4
LT4250L/LT4250H
4250lhf
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Gate Voltage vs Temperature
TEMPERATURE (
C)
12.0
GATE VOLTAGE (V) 13.0
14.0
15.0
12.5
13.5
14.5
25
0
75
1640 G04
100
50
25
50
V
DD
= 48V
TEMPERATURE (
C)
50
48
TRIP VOLTAGE (mV)
49
51
52
53
55
25
0
50
1640 G05
50
54
100
25
75
TEMPERATURE (
C)
50
GATE PULL-UP CURRENT (
A)
48
47
46
45
44
43
42
41
40
75
1640 G06
25
100
50
25
0
V
GATE
= 0V
Gate Pull-Up Current
vs Temperature
Gate Pull-Down Current
vs Temperature
TEMPERATURE (
C)
50
GATE PULL-DOWN CURRENT (mA)
49
52
55
75
1640 G07
46
43
40
25
0
25
50
100
V
GATE
= 2V
PWRGD Output Low Voltage
vs Temperature (LT4250L)
TEMPERATURE (
C)
50
PWRGD OUTPUT LOW VOLTAGE (V)
0.3
0.4
0.5
75
1640 G08
0.2
0.1
0
25
25
0
50
100
I
OUT
= 1mA
TEMPERATURE (
C)
50
2
OUTPUT IMPEDANCE (k
)
3
4
5
6
7
8
25
25
0
50
75
1640 G09
100
V
DRAIN
V
EE
> 2.4V
PWRGD Output Impedance
vs Temperature (LT4250H)
Current Limit Trip Voltage
vs Temperature
This condition is latched until the GATE pin is turned off via
the UV, OV, UVLO or the electronic circuit breaker.
When the DRAIN pin of the LT4250H is above V
EE
by more
than V
DL
or V
GATE
is more than V
GH
from
V
GATE
, the
PWRGD pin will sink current to the DRAIN pin which pulls
the module's enable pin low, forcing it off. When V
DRAIN
drops below V
DL
and V
GATE
rises above V
GH
, the PWRGD
sink current is turned off, allowing the module's pull-up
current to pull the enable pin high and turn on the module.
This condition is latched until the GATE pin is turned off via
the UV, OV, UVLO or the electronic circuit breaker.
PI
N
FU
N
CTIO
N
S
U
U
U
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will latch a power good indication when V
DRAIN
is within V
DL
of V
EE
and V
GATE
is within V
GH
of
V
GATE
. This pin can be
connected directly to the enable pin of a power module.
When the DRAIN pin of the LT4250L is above V
EE
by more
than V
DL
or V
GATE
is more than V
GH
from
V
GATE
, the
PWRGD pin will be high impedance, allowing the pull-up
current of the module's enable pin to pull the pin high and
turn the module off. When V
DRAIN
drops below V
DL
and
V
GATE
rises above V
GH
, the PWRGD pin sinks current to
V
EE
, pulling the enable pin low and turning on the module.
5
LT4250L/LT4250H
4250lhf
PI
N
FU
N
CTIO
N
S
U
U
U
OV
(Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.255V threshold, an overvoltage condition is
detected and the GATE pin will be immediately pulled low.
The GATE pin will remain low until OV drops below the
1.235V threshold.
UV (Pin 3): Analog Undervoltage Input. When UV is
pulled below the 1.125V threshold, an undervoltage
condition is detected and the GATE pin will be immedi-
ately pulled low. The GATE pin will remain low until UV
rises above the 1.255 threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur. The response
time for this pin is 1.5
s. Add an external capacitor to this
pin for additional filtering.
V
EE
(Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and
SENSE, the overcurrent condition will pull down the
GATE pin and regulate the voltage across the resistor to
be 50mV. If the overcurrent condition exists for more
than 500
s the electronic circuit breaker will trip and turn
off the external MOSFET.
If the current limit value is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
current limit feature, V
EE
and SENSE can be shorted
together.
GATE (Pin 6): Gate Drive Output for the External
N-Channel MOSFET. The GATE pin will go high when the
following start-up conditions are met: the UV pin is high,
the OV pin is low, (V
SENSE
V
EE
) < 50mV and the V
DD
pin
is greater than V
UVLOH
. The GATE pin is pulled high by a
45
A current source and pulled low with a 50mA current
source. During current limit the GATE pin is pulled low
using a 100mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel MOSFET and the
V
pin of the power module. When the DRAIN pin is
below V
DL
, the PWRGD/PWRGD pin will latch to indicate
the switch is on.
V
DD
(Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. An undervoltage lockout
circuit disables the chip until the V
DD
pin is greater than
the 16V V
UVLOH
threshold.
BLOCK DIAGRA
W
+
+
+
+
DRAIN
4250 BD
GATE
SENSE
V
EE
V
EE
V
DL
OUTPUT
DRIVE
PWRGD/PWRGD
50mV
V
CC
V
DD
REF
REF
UV
OV
LOGIC
V
CC
AND
REFERENCE
GENERATOR
+
+
+
+
V
GATE
V
GH
500
s
DELAY
GATE
DRIVER
UVLO
6
LT4250L/LT4250H
4250lhf
PWRGD/PWRGD
V
DD
V
+
5V
OV
V
DRAIN
48V
R
5k
DRAIN
LT4250L/LT4250H
UV
GATE
V
EE
SENSE
V
SENSE
1640 F01a
V
UV
V
OV
+
Figure 1a. Test Circuit 1
2V
1V
4250 F02
t
PHLOV
1.255V
0V
OV
GATE
1V
1.235V
t
PLHOV
TI
M
I
N
G DIAGRA
M
S
W
U
W
Figure 2. OV to GATE Timing
2V
1V
4250 F03
t
PHLUV
1.125V
0V
UV
GATE
1V
1.255V
t
PLHUV
Figure 3. UV to GATE Timing
Figure 4a. SENSE to GATE Timing
1V
4250 F04a
t
PHLSENSE
60mV
SENSE
GATE
100mV
V
EE
Figure 5a. DRAIN to PWRGD/PWRGD Timing
Figure 4b. Active Current Limit Timeout
1V
4250 F04b
t
PHLCB
UV
GATE
1V
PWRGD/PWRGD V
DD
OV
48V
20V
DRAIN
LT4250L/LT4250H
UV
GATE
V
EE
SENSE
4250 F01b
V
UV
0.1
F
+
+
10k
10
10
IRF530
Figure 1b. Test Circuit 2
Figure 5b. GATE to PWRGD/PWRGD Timing
4250 F05b
V
PWRGD
V
DRAIN
= 0
GATE
PWRGD
1V
1.4V
1.4V
V
EE
GATE
PWRGD
1V
t
PHLGH
t
PHLGH
V
GATE
V
GATE
= 0
V
GATE
V
GATE
= 0
4250 F05a
V
PWRGD
V
DRAIN
= 0V
DRAIN
PWRGD
1V
1.4V
V
EE
DRAIN
PWRGD
1V
1.4V
t
PHLDL
t
PHLDL
V
EE
V
EE
7
LT4250L/LT4250H
4250lhf
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Hot Circuit Insertion
When circuit boards are inserted into a live 48V backplane,
the bypass capacitors at the input of the board's power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board's components
and cause glitches on the system power supply.
The LT4250 is designed to turn on a board's supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the V
EE
pin of the LT4250). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the inrush current charging load capacitors C3 and
C4 can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The C2 capacitor can
be calculated with the following equation:
C2 = (45
A C
L
)/I
INRUSH
where C
L
is the total load capacitance = C3 + C4 + module
input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to V
EE
C2/C
GS(Q1)
before the
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
C
V
V
V
C
C
INMAX
TH
TH
GD
1
2
=
-
+
(
)
C1
35 C2 for V
INMAX
= 72V
where V
TH
is the MOSFET's minimum gate threshold and
V
INMAX
is the maximum operating input voltage.
R3 should not exceed a value that produces an
R3 C2 time-constant of 150
s. A 1k value for R3 will
ensure this for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
Figure 6a. Inrush Control Circuitry
+
V
EE
V
DD
LT4250H
PWRGD
UV = 38.5V
OV = 71V
SENSE
C1
470nF
25V
C3
0.1
F
100V
C4
100
F
100V
C5
100
F
16V
Q1
IRF530
R2
10
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02
5%
4
3
2
OV
48V RTN
48V RTN
(SHORT PIN)
48V
UV
5
6
8
7
1
GATE
DRAIN
VICOR
VI-J30-CY
V
OUT
+
V
OUT
V
IN
+
5V
4250 F06a
GATE IN
V
IN
+
*
* DIODES INC. SMAT70A
4
3
2
1
Figure 6b. Inrush Control Waveforms
INRUSH
CURRENT
500mA/DIV
GATE V
EE
10V/DIV
DRAIN
50V/DIV
V
EE
50V/DIV
25ms/DIV
4250 F06b
CONTACT
BOUNCE
MODULE
TURN-ON
MODULE
TURN-ON
CONTACT
BOUNCE
8
LT4250L/LT4250H
4250lhf
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Current Limit/Electronic Circuit Breaker
The LT4250 features a current limit function that protects
against short circuits or excessive supply currents. If the
current limit is active for more than 500
s the electronic
circuit breaker will trip. By placing a sense resistor
between the V
EE
and SENSE pin, the current limit will be
activated whenever the voltage across the sense resistor
is greater than 50mV.
Note that the current limit threshold should be set suffi-
ciently high to account for the sum of the load current and
the inrush current. The maximum value of the inrush
current is given by:
I
mV
R
I
INRUSH
SENSE
LOAD
0 8
40
.
,
where the 0.8 factor is used as a worst case margin
combined with the minimum trip voltage (40mV).
In the case of a short circuit, the current limit circuitry
activates and immediately pulls the GATE low, servos the
SENSE voltage to 50mV, and starts a 500
s timer. The
MOSFET current is limited to 50mV/R
SENSE
(see Figure 7).
If the short circuit persists for more than 500
s, the circuit
breaker trips and pulls the GATE pin low, shutting off the
MOSFET. The circuit breaker is reset by pulling UV low, or
by cycling power to the part. If the short circuit clears
before the 500
s timing interval the current limit will
deactivate and release the GATE.
Figure 7. Short-Circuit Protection Waveforms
The LT4250 guards against voltage steps on the input
supply. A positive voltage step (increasing in magnitude)
on the input supply causes an inrush current that is
proportional to the voltage slew rate I = C
L
V/
T. If the
inrush exceeds 50mV/R
SENSE
, the current limit will acti-
vate as shown in Figure 8. The GATE pin pulls low, limiting
the current to 50mV/R
SENSE
. At this level the MOSFET
drain will not follow the source as the input voltage rapidly
changes, but instead remains at the voltage stored on the
load capacitance. The load capacitance begins to charge
at a current of 50mV/R
SENSE
, but not for long. As the load
capacitance charges, C2 pushes back on the gate and
limits the MOSFET current in a manner identical to the
initial start-up condition which is less than the short circuit
limiting value of 50mV/R
SENSE
. Thus the circuit breaker
does not trip. To ensure correct operation under input
voltage step conditions, R
SENSE
must be chosen to pro-
vide a current limit value greater than the sum of the load
current and the dynamic current in the load capacitance.
For C2 values less than 10nF a positive voltage step on the
input supply can result in the Q1 turning off momentarily
which can shut down the output. By adding an additional
resistor and diode, Q1 remains on during the voltage step.
This is shown as D1 and R7 in Figure 9. The purpose of D1
is to shunt current around R7 when the power pins first
make contact and allow C1 to hold the GATE low. The value
of R7 should be sized to generate an R7 C1 time constant
of 33
s.
Under some conditions, a short circuit at the output can
cause the input supply to dip below the UV threshold. The
LT4250 turns off once and then turns on until the elec-
tronic circuit breaker is tripped. This can be minimized by
adding a deglitching delay to the UV pin with a capacitor
from UV to V
EE
. This capacitor forms an RC time constant
with the resistors at UV, allowing the input supply to
recover before the UV pin resets the circuit breaker.
DRAIN
50V/DIV
GATE
10V/DIV
I
D
(Q1)
5A/DIV
1ms/DIV
9
LT4250L/LT4250H
4250lhf
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 10. Automatic Restart After Current Fault
Figure 9. Circuit for Input Steps with Small C2 (<10nF)
Figure 8. Voltage Step on
Input Supply Waveforms
A circuit that automatically resets the circuit breaker after
a current fault is shown in Figure 10. Transistors Q2 and
Q3 along with R7, R8, C4 and D1 form a programmable
one-shot circuit. Before a short occurs, the GATE pin is
pulled high and Q3 is turned on, pulling node 2 to V
EE
.
Resistor R8 turns off Q2. When a short occurs, the GATE
pin is pulled low and Q3 turns off. Node 2 starts to charge
C4 and Q2 turns on, pulling the UV pin low and resetting
the circuit breaker. As soon as C4 is fully charged, R8 turns
off Q2, UV goes high and the GATE starts to ramp up. Q3
turns back on and quickly pulls node 2 back to V
EE
. Diode
D1 clamps node 3 one diode drop below V
EE
. The duty
cycle is set to 10% to prevent Q1 from overheating.
V
EE
V
DD
LT4250H
PWRGD
SENSE
C1
150nF
25V
C3
0.1
F
100V
C4
22
F
100V
Q1
IRF530
R2
10
5%
R3
1k
5%
C2
3.3nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02
5%
4
3
2
48V RTN
48V
OV
UV
5
6
8
1
GATE
DRAIN
4250 F09
+
7
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
R7
220
5%
4
3
2
1
D1
BAT85
V
EE
V
DD
LT4250L
PWRGD
SENSE
C1
470nF
25V
C4
1
F
100V
C3
100
F
100V
Q1
IRF530
R2
10
5%
R8
510k
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R7
1M
5%
R5
16.5k
1%
R9
10k
1%
R6
549k
1%
Q3
ZVN3310
Q2
2N2222
D1
1N4148
R1
0.02
5%
4
3
2
OV
48V
UV
5
6
8
7
1
GATE
DRAIN
4250 F10a
3
2
+
48V RTN
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
4
3
2
1
V
EE
AND
DRAIN
20V/DIV
I
D
(Q1)
5A/DIV
500
s/DIV
NODE 2
50V/DIV
GATE
2V/DIV
1s/DIV
10
LT4250L/LT4250H
4250lhf
V
EE
V
DD
LT4250L/LT4250H
R4
R5
R6
4
4250 F11
OV
48V RTN
3
2
48V
UV
8
V
UV
= 1.255
R4 + R5+ R6
R5 + R6
(
)
V
OV
= 1.255
R4 + R5+ R6
R6
(
)
48V RTN
(SHORT PIN)
+
V
EE
V
DD
LT4250H
SENSE
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
OV
48V RTN
48V
UV
5
6
8
1
7
GATE
4250 F12
PWRGD
DRAIN
V
EE
Q3
ACTIVE HIGH
ENABLE MODULE
V
OUT
+
V
OUT
V
IN
+
V
IN
ON/OFF
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
4
3
2
1
Q2
V
DL
V
GH
+
+
+
+
GATE
V
GATE
I
1
internal transistor Q3 is turned off and I
1
and Q2 clamp the
PWRGD pin one SAT drop (
0.3V) above the DRAIN pin.
Transistor Q2 sinks the module's pull-up current and the
module turns off.
When the DRAIN voltage drops below V
DL
and the GATE
voltage is high, Q3 will turn on, shorting the bottom of I
1
to DRAIN and turning Q2 off. The pull-up current in the
module pulls the PWRGD pin high and enables the
module.
When the DRAIN voltage of the LT4250L is high with
respect to V
EE
or the GATE voltage is low, the internal pull-
down transistor Q2 is off and the PWRGD pin is in a high
impedance state (Figure 13). The PWRGD pin will be
pulled high by the module's internal pull-up current source,
turning the module off. When the DRAIN voltage drops
below V
DL
and the GATE voltage is high, Q2 will turn on and
the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown
in Figure 14.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 20V, the
GATE pin voltage is regulated at 13.5V above V
EE
. The gate
voltage will be no greater than 18V for supply voltages up
to 80V.
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power
supply input. The UV and OV pins are internally connected
to analog comparators with 130mV and 20mV of hyster-
esis respectively. When the UV pin falls below its threshold
or the OV pin rises above its threshold, the GATE pin is
immediately pulled low. The GATE pin will be held low until
UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the
undervoltage threshold is set to 38.5V (with a 43V release
from undervoltage) and the overvoltage threshold is set to
71V. The resistor divider will also gain up the hysteresis
at the UV pin and OV pin to 4.5V and 1.2V at the input
respectively.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT4250L has a PWRGD output for
modules with an active low enable input, and the LT4250H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT4250H is high with
respect to V
EE
(Figure 12) or the GATE voltage is low, the
Figure 12. Active High Enable Module
Figure 11. Undervoltage and Overvoltage Sensing
11
LT4250L/LT4250H
4250lhf
Figure 14. Using PWRGD to Drive an Optoisolator
Figure 13. Active Low Enable Module
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N8 1098
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130
0.005
(3.302
0.127)
0.020
(0.508)
MIN
0.018
0.003
(0.457
0.076)
0.125
(3.175)
MIN
1
2
3
4
8
7
6
5
0.255
0.015*
(6.477
0.381)
0.400*
(10.160)
MAX
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.016 0.050
(0.406 1.270)
0.010 0.020
(0.254 0.508)
45
0
8
TYP
0.008 0.010
(0.203 0.254)
SO8 1298
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
TYP
0.004 0.010
(0.101 0.254)
0.050
(1.270)
BSC
1
2
3
4
0.150 0.157**
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
V
EE
LT4250L
SENSE
OV
UV
V
DL
V
GH
+
+
+
+
GATE
V
GATE
+
V
DD
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
48V RTN
48V
5
6
8
1
7
GATE
4250 F13
PWRGD
DRAIN
V
EE
ACTIVE LOW
ENABLE MODULE
V
OUT
+
V
OUT
V
IN
+
V
IN
ON/OFF
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
4
3
2
1
Q2
V
EE
V
DD
LT4250L
PWRGD
SENSE
C1
470nF
25V
C3
100
F
100V
Q1
IRF530
R2
10
5%
R7
51k
5%
R3
1k, 5%
C2
15nF
100V
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02
5%
4
3
2
OV
48V RTN
48V
UV
5
6
8
7
1
MOC207
GATE
DRAIN
4250 F14
PWRGD
+
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
4
3
2
1
U
PACKAGE DESCRIPTIO
APPLICATIO S I FOR ATIO
W
U
U
U
12
LT4250L/LT4250H
4250lhf
PART NUMBER
DESCRIPTION
COMMENTS
LTC
1421
Dual Hot Swap Controller with Additional 12V Control
Operates from 3V to 12V
LTC1422
Hot Swap Controller in SO-8
System Reset Output with Programmable Delay
LT1640AH/LT1640AL
48V Hot Swap Controller in SO-8
LT4250 is a Pin-Compatible Upgrade to LT1640
LT1641-1/LT1641-2
+48V Hot Swap Controller in SO-8
Foldback Current Limit, 9V to 80V, Auto-Retry/Latch-Off
LTC1642
Fault Protected Hot Swap Controller
Operates Up to 16.5V, Protected to 33V
LTC1643
PCI Hot Swap Controller
3.3V, 5V, 12V, 12V Supplies for PCI Bus
LTC1645
Dual Hot Swap Controller
Operates from 1.2V to 12V, Power Sequencing
LTC1646
Dual CompactPCI Hot Swap Controller
3.3V, 5V Supplies with Precharge and Local PCI Reset Logic
LTC1647
Dual Hot Swap Controller
Dual ON Pins for Supplies from 3V to 15V
LTC4211
Hot Swap Controller with Multifunction Current Control
2.5V to 16.5V Supplies, Active Inrush Current Limiting
LTC4251
48 Hot Swap Controller in SOT-23
Active Current Limiting, Fast Comparator
for Catastrophic Faults
LTC4252
48 Hot Swap Controller in MSOP
Active Current Limiting, Fast Comparator for Catastrophic
Faults, Separate UV/0V Pins, Power-Good Output
LINEAR TECHNOLOGY CORPORATION 2001
LT/TP 0402 2K PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
TYPICAL APPLICATIO
N
U
Using an EMI Filter Module
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
using the Lucent FLTR100V10 filter module is shown in
Figure 15. When using a filter, an optoisolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
RELATED PARTS
Figure 15. Typical Application Using a Filter Module
+
V
EE
V
DD
LT4250L
PWRGD
SENSE
C1
470nF
25V
C2
15nF
100V
C3
0.1
F
100V
C4
0.1
F
100V
C6
0.1
F
100V
C5
100
F
100V
C7
100
F
16V
Q1
IRF530
R2
10
5%
R3
1k
5%
R4
549k
1%
R5
6.49k
1%
R6
10k
1%
R1
0.02
5%
4
OV
48V RTN
3
2
48V
UV
5
6
8
7
1
GATE
DRAIN
LUCENT
JW050A1-E
V
OUT
+
SENSE
+
TRIM
SENSE
V
OUT
V
IN
+
9
5V
4250 F15
8
7
6
5
3
1
2
4
ON/OFF
CASE
V
IN
V
OUT
+
V
OUT
V
IN
+
CASE
V
IN
+
LUCENT
FLTR100V10
48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
4
3
2
1
MOC207
R7
51k
5%
1N4003
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