1
LTC1657
Parallel 16-Bit Rail-to-Rail
Micropower DAC
s
16-Bit Monotonic Over Temperature
s
Deglitched Rail-to-Rail Voltage Output: 8nVs
s
5V Single Supply Operation
s
I
CC
: 650
A Typ
s
Maximum DNL Error:
1LSB
s
Settling Time: 20
s to
1LSB
s
Internal or External Reference
s
Internal Power-On Reset to Zero Volts
s
Asynchronous CLR Pin
s
Output Buffer Configurable for Gain of 1 or 2
s
Parallel 16-Bit or 2-Byte Double Buffered Interface
s
Narrow 28-Lead SSOP Package
s
Multiplying Capability
The LTC
1657 is a complete single supply, rail-to-rail
voltage output, 16-bit digital-to-analog converter (DAC) in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 2.048V reference and
a double buffered parallel digital interface.
The LTC1657 operates from a 4.5V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.
The LTC1657 is similar to Linear Technology Corporation's
LTC1450 12-bit V
OUT
DAC family allowing an upgrade
path. It is the only buffered 16-bit parallel DAC in a 28-lead
SSOP package and includes an onboard reference for
stand alone performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Instrumentation
s
Digital Calibration
s
Industrial Process Control
s
Automatic Test Equipment
s
Communication Test Equipment
Differential Nonlinearity
vs Input Code
REFLO
GND
0V TO
4.096V
5V
16-BIT
DAC
R
R
25
REFHI
REFOUT
22
24
23
X1/X2
21
20
26
1657 TA01
V
OUT
V
CC
D15 (MSB)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
2
28
27
D8
D7
DATA IN FROM
MICROPROCESSOR
DATA BUS
FROM
MICROPROCESSOR
DECODE LOGIC
FROM
SYSTEM RESET
D0 (LSB)
+
REFERENCE
2.048V
16-BIT
DAC
REGISTER
POWER-ON
RESET
LDAC
CLR
WR
CSMSB
CSLSB
LSB
8-BIT
INPUT
REGISTER
MSB
8-BIT
INPUT
REGISTER
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
DIGITAL INPUT CODE
0
16384
32768
49152
65535
DIFFERENTIAL NONLINEARITY (LSB)
1657 G01
1.0
0.8
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
1.0
2
LTC1657
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
(Note 1)
V
CC
to GND .............................................. 0.5V to 7.5V
TTL Input Voltage, REFHI, REFLO,
X1/X2 ....................................................... 0.5V to 7.5V
V
OUT
, REFOUT ............................ 0.5V to (V
CC
+ 0.5V)
Operating Temperature Range
LTC1657C ............................................. 0
C to 70
C
LTC1657I ........................................ 40
C to 85
C
Maximum Junction Temperature .......................... 125
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
ORDER PART
NUMBER
Consult factory for Military grade parts.
T
JMAX
= 125
C,
JA
= 95
C/ W (G)
T
JMAX
= 125
C,
JA
= 58
C/ W (N)
LTC1657CGN
LTC1657CN
LTC1657IGN
LTC1657IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD PLASTIC SSOP
N PACKAGE
28-LEAD PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WR
CSLSB
CSMSB
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
LDAC
CLR
X1/X2
V
OUT
V
CC
REFOUT
REFHI
REFLO
GND
D15 (MSB)
D14
D13
D12
D11
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 4.5V to 5.5V, V
OUT
unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC (Note 2)
Resolution
q
16
Bits
Monotonicity
q
16
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 3)
q
0.5
1.0
LSB
INL
Integral Nonlinearity
(Note 3)
q
4
12
LSB
ZSE
Zero Scale Error
q
0
2
mV
V
OS
Offset Error
Measured at Code 200
q
0.3
3
mV
V
OS
TC
Offset Error Tempco
5
V/
C
Gain Error
q
2
16
LSB
Gain Error Drift
0.5
ppm/
C
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance
q
4.5
5.5
V
I
CC
Supply Current
4.5V
V
CC
5.5V (Note 4)
q
650
1200
A
Op Amp DC Performance
Short-Circuit Current Low
V
OUT
Shorted to GND
q
70
120
mA
Short-Circuit Current High
V
OUT
Shorted to V
CC
q
80
140
mA
Output Impedance to GND
Input Code = 0
q
40
120
Output Line Regulation
Input Code = 65535, V
CC
= 4.5V to 5.5V
q
4
mV/V
3
LTC1657
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 4.5V to 5.5V, V
OUT
unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: External reference REFHI = 2.2V. V
CC
= 5V.
Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.
Note 4: Digital inputs at 0V or V
CC
.
Note 5: DAC switched between all 1s and all 0s.
Note 6: Guaranteed by design. Not subject to test.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
Voltage Output Slew Rate
(Note 5)
q
0.3
0.7
V/
s
Voltage Output Settling Time
(Note 5) to 0.0015% (16-Bit Settling Time)
20
s
(Note 5) to 0.012% (13-Bit Settling Time)
10
s
Digital Feedthrough
0.3
nV s
Midscale Glitch Impulse
DAC Switch Between 8000
H
and 7FFF
H
8
nV s
Output Voltage Noise Spectral Density
At 1kHz
250
nV/
Hz
Digital I/O
V
IH
Digital Input High Voltage
q
2.4
V
V
IL
Digital Input Low Voltage
q
0.8
V
V
OH
Digital Output High Voltage
q
V
CC
1
V
V
OL
Digital Output Low Voltage
q
0.4
V
I
LEAK
Digital Input Leakage
V
IN
= GND to V
CC
q
10
A
C
IN
Digital Input Capacitance
(Note 6)
10
pF
Switching Characteristics
t
CS
CS (MSB or LSB) Pulse Width
q
40
ns
t
WR
WR Pulse Width
q
40
ns
t
CWS
CS to WR Setup
q
0
ns
t
CWH
CS to WR Hold
q
0
ns
t
DWS
Data Valid to WR Setup
q
40
ns
t
DWH
Data Valid to WR Hold
q
0
ns
t
LDAC
LDAC Pulse Width
q
40
ns
t
CLR
CLR Pulse Width
q
40
ns
Reference Output (REFOUT)
Reference Output Voltage
q
2.036
2.048
2.060
V
Reference Output
15
ppm/
C
Temperature Coefficient
Reference Line Regulation
V
CC
= 4.5V to 5.5V
q
1.5
mV/V
Reference Load Regulation
Measured at I
OUT
= 100
A
q
5
mV/A
Short-Circuit Current
REFOUT Shorted to GND
q
50
100
mA
Reference Input
REFHI, REFLO Input Range
(Note 6) See Applications Information
X1/X2 Tied to V
OUT
q
0
V
CC
1.5
V
X1/X2 Tied to GND
q
0
V
CC
/2
V
REFHI Input Resistance
q
16
25
k
4
LTC1657
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
DIGITAL INPUT CODE
0
16384
32768
49152
65535
DIFFERENTIAL NONLINEARITY (LSB)
1657 G01
1.0
0.8
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
1.0
DIGITAL INPUT CODE
0
16384
32768
49152
65535
INTEGRAL NONLINEARITY (LSB)
1657 G02
5
4
3
2
1
0
1
2
3
4
5
LOAD CURRENT (mA)
0
5
10
V
CC
V
OUT
(V)
1657 G03
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CODE ALL 1'S
V
OUT
1LSB
125
C
25
C
55
C
OUTPUT SINK CURRENT (mA)
0
5
10
15
OUTPUT PULL-DOWN VOLTAGE (V)
1657 G04
1.2
1.0
0.8
0.6
0.4
0.2
0
CODE ALL 0'S
V
OUT
1LSB
125
C
25
C
55
C
TEMPERATURE (
C)
55
25
5
35
65
95
125
FULL-SCALE VOLTAGE (V)
1657 G05
4.110
4.105
4.100
4.095
4.090
4.085
4.080
TEMPERATURE (
C)
55
10
35
80
125
OFFSET (mV)
1657 G06
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LOGIC INPUT VOLTAGE (V)
0
1
2
3
4
5
SUPPLY CURRENT (mA)
1657 G07
8
7
6
5
4
3
2
1
0
TEMPERATURE (
C)
55 35 15
5
25
45
65
85 105 125
SUPPLY CURRENT (
A)
1657 G08
700
680
660
640
620
600
580
560
540
520
500
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
Differential Nonlinearity
Integral Nonlinearity
Minimum Supply Headroom for
Full Output Swing vs Load Current
Minimum Output Voltage vs
Output Sink Current
Full-Scale Voltage vs
Temperature
Offset Error vs Temperature
Supply Current vs Logic Input
Voltage
Supply Current vs Temperature
TIME (20
s/DIV)
OUTPUT VOLTAGE (V)
1657 G09
5
4
3
2
1
0
V
OUT
UNLOADED
T
A
= 25
C
Large-Signal Transient Response
5
LTC1657
WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/or CSLSB to control the input registers. While WR and
CSMSB and/or CSLSB are held low, data writes into the
input register.
CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input regis-
ters. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
D0 to D7 (Pins 4 to 11): Input data for the Least Significant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.
D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-
cant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.
GND (Pin 20): Ground.
REFLO (Pin 21): Lower input terminal of the DAC's inter-
nal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)
H
will connect the positive input of
PI
N
FU
N
CTIO
N
S
U
U
U
the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.
REFHI (Pin 22): Upper input terminal of the DAC's internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)
H
will connect the positive input of the
output buffer to 1LSB below this voltage.
REFOUT (Pin 23): Output of the internal 2.048V reference.
Typically connected to REFHI to drive internal DAC resistor
ladder.
V
CC
(Pin 24): Positive Power Supply Input. 4.5V
V
CC
5.5V. Requires a 0.1
F bypass capacitor to ground.
V
OUT
(Pin 25): Buffered DAC Output.
X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND
for G = 2 or to V
OUT
for G = 1. This pin should always be
tied to a low impedance source, such as ground or V
OUT
,
to ensure stability of the output buffer when driving
capacitive loads.
CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.
LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
input registers which will immediately update V
OUT
.
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