1
LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
March 2000
The LTC
1662 is an ultralow power, fully buffered volt-
age output, dual 10-bit digital-to-analog converter (DAC).
Each DAC draws just 1.7
A (typ) total supply-plus-
reference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable Sleep
mode further reduces total operating current to a negli-
gible 0.05
A.
Linear Technology's proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write to
either DAC without interrupting Sleep mode.
With its ultralow operating current and exceptionally
small size, the LTC1662 is ideal for use in battery-
powered products.
The LTC1662 is pin- and software-compatible with the
LTC1661 micropower dual 10-bit DAC. It is available in
8-pin MSOP and PDIP packages and is specified over the
industrial temperature range.
s
Ultralow Power: 1.5
A (Typ) I
CC
per DAC Plus
0.05
A Sleep Mode for Extended Battery Life
s
Tiny: Two 10-Bit DACs in an 8-Lead MSOP--
Half the Size of an SO-8
s
Wide 2.7V to 5.5V Supply Range
s
Double Buffered for Simultaneous DAC Updates
s
Rail-to-Rail Voltage Outputs Drive 1000pF
s
Reference Range Includes Supply for Ratiometric
0V-to-V
CC
Output
s
Reference Input Impedance Is Code-Independent
(7.1M
Typ)--Eliminates External Buffers
s
3-Wire Serial Interface with
Schmitt Trigger Inputs
s
Differential Nonlinearity:
0.75LSB Max
, LTC and LT are registered trademarks of Linear Technology Corporation.
Total Supply-Plus-Reference
Operating Current
s
Mobile Communications
s
Portable Battery-Powered Instruments
s
Remote Industrial Devices
s
Digitally Controlled Amplifiers and Attenuators
s
Automatic Calibration for Manufacturing
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
BLOCK DIAGRA
W
V
CC
(V)
2.5
3.5
4.5
3.0
4.0
5.0
5.5
TOTAL OPERATING CURRENT (
A)
1662 G01
5.5
5.0
4.5
4.0
3.5
3.0
2.5
V
REF
= V
CC
T
A
= 25
C
CODE = 1023
CODE = 512
CODE = 0
Final Electrical Specifications
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
CS/LD
1662 BD
1
4
10-BIT
DAC A
10-BIT
DAC B
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
D
IN
REF
3
V
OUT
A
8
5
GND
7
V
CC
V
OUT
B
6
LATCH
LATCH
LATCH
LATCH
SCK
2
2
LTC1662
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
(Note 1)
V
CC
to GND .............................................. 0.3V to 7.5V
Logic Inputs to GND ................................ 0.3V to 7.5V
V
OUT A
, V
OUT B
, REF to GND ......... 0.3V to (V
CC
+ 0.3V)
Maximum Junction Temperature ......................... 125
C
Storage Temperature Range ................ 65
C to 150
C
Operating Temperature Range
LTC1662C ............................................. 0
C to 70
C
LTC1662I ........................................... 40
C to 85
C
Lead Temperature (Soldering, 10 sec)................ 300
C
ELECTRICAL C
C
HARA TERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
q
10
Bits
Monotonicity
(Note 2)
q
10
Bits
DNL
Differential Nonlinearity
(Note 2)
q
0.12
0.75
LSB
INL
Integral Nonlinearity
(Note 2)
q
0.8
4
LSB
V
OS
Offset Error
V
CC
= 5V, V
REF
= 4.096V, Measured at Code 20
q
5
25
mV
V
OS
TC
V
OS
Temperature Coefficient
15
V/
C
GE
Gain Error
V
CC
= 5V, V
REF
= 4.096V
q
1
8
LSB
GE TC
Gain Error Temperature
12
V/
C
Coefficient
PSR
Power Supply Rejection
V
REF
= 2.5V
0.18
LSB/V
Reference Input
Input Voltage Range
q
0
V
CC
V
Input Resistance
Active Mode
q
3.9
7.1
M
Sleep Mode
2.5
G
Input Capacitance
10
pF
W
U
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
MS8 PART MARKING
ORDER PART
NUMBER
T
JMAX
= 125
C,
JA
= 150
C/W
1
2
3
4
CS/LD
SCK
D
IN
REF
8
7
6
5
V
OUT A
GND
V
CC
V
OUT B
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
1
2
3
4
8
7
6
5
TOP VIEW
CS/LD
SCK
D
IN
REF
V
OUT A
GND
V
CC
V
OUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
LTC1662CN8
LTC1662IN8
LTC1662CMS8
LTC1662IMS8
Consult factory for Military grade parts.
T
JMAX
= 125
C,
JA
= 100
C/W
The
q
denotes the specifications which apply over the full operating
temperature range (T
A
= T
MIN
to T
MAX
), otherwise specifications are at T
A
= 25
C. V
CC
= 2.7V to 5.5V, V
REF
V
CC
, V
OUT
Unloaded
unless otherwise noted.
LTKB
LTKC
3
LTC1662
The
q
denotes the specifications which apply over the full operating
ELECTRICAL C
C
HARA TERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
The
q
denotes the specifications which apply over the full operating
temperature range (T
A
= T
MIN
to T
MAX
), otherwise specifications are at T
A
= 25
C. V
CC
= 2.7V to 5.5V, V
REF
V
CC
, V
OUT
Unloaded
unless otherwise noted.
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance
q
2.7
5.5
V
I
CC
Supply Current
V
CC
= 3V (Note 3)
3.0
4.0
A
V
CC
= 5V (Note 3)
3.5
4.5
A
V
CC
= 3V (Note 3)
q
5.0
A
V
CC
= 5V (Note 3)
q
5.5
A
Sleep Mode Operating Current Supply Plus Reference Current, V
CC
= V
REF
= 5V, (Note 3)
0.05
0.10
A
q
0.18
A
DC Performance
Short-Circuit Current Low
V
OUT
= 0V, V
CC
= V
REF
= 5V, Code = 1023 (Note 7)
q
5
12
70
mA
Short-Circuit Current High
V
OUT
= V
CC
= V
REF
= 5V, Code = 0 (Note 7)
q
3
10
80
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
20
V/ms
Falling (Notes 4, 5)
7
V/ms
Voltage Output Settling Time
0.1V
FS
to 0.9V
FS
0.5LSB (Notes 4, 5)
0.40
ms
0.9V
FS
to 0.1V
FS
0.5LSB (Notes 4, 5)
0.75
ms
Capacitive Load Driving
1000
pF
Digital I/O
V
IH
Digital Input High Voltage
V
CC
= 2.7V to 5.5V
q
2.4
V
V
CC
= 2.7V to 3.6V
q
2.0
V
V
IL
Digital Input Low Voltage
V
CC
= 4.5V to 5.5V
q
0.8
V
V
CC
= 2.7V to 5.5V
q
0.6
V
I
LK
Digital Input Leakage
V
IN
= GND to V
CC
q
0.05
1.0
A
C
IN
Digital Input Capacitance
(Note 6)
1.5
pF
TI I G CHARACTERISTICS
U
W
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
= 4.5V to 5.5V
t
1
D
IN
Valid to SCK Setup
q
55
15
ns
t
2
D
IN
Valid to SCK Hold
q
0
10
ns
t
3
SCK High Time
(Note 6)
q
30
14
ns
t
4
SCK Low Time
(Note 6)
q
30
14
ns
t
5
CS/LD Pulse Width
(Note 6)
q
100
27
ns
t
6
LSB SCK High to CS/LD High
(Note 6)
q
30
2
ns
t
7
CS/LD Low to SCK High
(Note 6)
q
20
21
ns
t
9
SCK Low to CS/LD Low
(Note 6)
q
0
5
ns
t
11
CS/LD High to SCK Positive Edge
(Note 6)
q
20
0
ns
SCK Frequency
Square Wave (Note 6)
q
16.7
MHz
V
CC
= 2.7V to 5.5V
t
1
D
IN
Valid to SCK Setup
(Note 6)
q
75
20
ns
t
2
D
IN
Valid to SCK Hold
(Note 6)
q
0
10
ns
t
3
SCK High Time
(Note 6)
q
50
15
ns
t
4
SCK Low Time
(Note 6)
q
50
15
ns
4
LTC1662
TI I G DIAGRA
U
W
W
D
IN
CS/LD
SCK
A3
A2
1662 TD
A1
X1
X0
t
2
t
9
t
11
t
5
t
7
t
6
t
1
t
3
t
4
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
CODE
0
256
512
768
1023
INTEGRAL NONLINEARITY (LSB)
1662 G02
4
3
2
1
0
1
2
3
4
CODE
0
256
512
768
1023
DIFFERENTIAL NONLINEARITY (LSB)
1662 G03
0.60
0.40
0.20
0
0.20
0.40
0.60
0.80
0.75
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined and tested at V
CC
= 5V,
V
REF
= 4.096V, from code 20 to code 1023. See Figure 2.
Note 3: Digital inputs at 0V or V
CC
.
Note 4: Load is 10k
in parallel with 100pF.
Note 5: V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
; i.e.,
codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
TI I G CHARACTERISTICS
U
W
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C.
t
5
CS/LD Pulse Width
(Note 6)
q
150
30
ns
t
6
LSB SCK High to CS/LD High
(Note 6)
q
50
3
ns
t
7
CS/LD Low to SCK High
(Note 6)
q
30
14
ns
t
9
SCK Low to CS/LD Low
(Note 6)
q
0
5
ns
t
11
CS/LD High to SCK Positive Edge
(Note 6)
q
30
0
ns
SCK Frequency
Square Wave (Note 6)
q
10
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5
LTC1662
OPERATIO
U
D
IN
SCK
CS/LD
A3
A2
INPUT CODE
DON'T CARE
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
1662 F01
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(SCK ENABLED)
(INSTRUCTION
EXECUTED)
CONTROL CODE
INPUT WORD W
0
Figure 1. Register Loading Sequence
Table 1. DAC Control Functions
CONTROL
INPUT REGISTER
DAC REGISTER
POWER-DOWN STATUS
A3
A2
A1
A0
STATUS
STATUS
(SLEEP/WAKE)
COMMENTS
0
0
0
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
0
0
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1
0
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing Contents
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1
1
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
Outputs Set to High Impedance State
1
1
1
1
Load DACs A, B
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
with Same
Contents of Input Regs. Outputs Update. Part Wakes Up
10-Bit Code
6
LTC1662
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
IN
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compat-
ible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
D
IN
(Pin 3): Serial Interface Data Input. Input word data on
the D
IN
pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V
V
REF
V
CC
.
V
OUT A
, V
OUT B
(Pins 8,5): DAC Analog Voltage Outputs.
The output range is
0
1023
1024
V
V
V
OUTA
OUTB
REF
,
V
CC
(Pin 6): Supply Voltage Input. 2.7V
V
CC
5.5V.
GND (Pin 7): System Ground.
INL = [V
OUT
V
OS
(V
FS
V
OS
)(code/1023)]/LSB
where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
REF
/1024
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (
V
OUT
LSB)/LSB
where
V
OUT
is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows:
PI FU CTIO S
U
U
U
DEFI ITIO S
U
U
7
LTC1662
Transfer Function
The transfer function for the LTC1662 is:
V
k
V
OUT IDEAL
REF
(
)
=
1024
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V
REF
is the voltage at REF (Pin 6).
Power-On Reset
The LTC1662 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
0.3V
V
REF
V
CC
+ 0.3V (see Absolute Maximum
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
at V
CC
(Pin 6) is in transition.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don't-care bits.
Table 1. LTC1662 Input Word
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the D
IN
input
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don't-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110
b
is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital circuits
remain active while the analog sections are disabled; static
power consumption is greatly reduced. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110
b
(the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001
b
and
0010
b
); then, a single command (1000
b
) can be used both
to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001
b
is used to load DAC A
during Sleep. Then Control code 0101
b
loads DAC B,
wakes the part and simultaneously updates both DAC
outputs.
A3 A2 A1
Control Code
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
Input Code
Input Word
Don't
Care
After the Input word is loaded into the register (see Figure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
By selecting the appropriate 4-bit Control code (see Table 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
OPERATIO
U
8
LTC1662
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
1662 F02
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
512
0
1023
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1662 can typically source or sink up to 1mA
(V
CC
= 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 85
(typical) when driving a load to
the rails. The output amplifiers are stable driving capaci-
tive loads up to 1000pF.
OPERATIO
U
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
. If V
REF
= V
CC
and the DAC full-scale error
(FSE = V
OS
+ GE) is positive, the output for the highest
codes limits at V
CC
as shown in Figure 2c. No full-scale
limiting can occur if V
REF
is less than V
CC
FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
9
LTC1662
TYPICAL APPLICATIO
U
Using the LTC1258 and the LTC1662 In a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2
A
2
0.1
F
Li-ION BATTERY INPUT
V
IN
4.3V
LTC1258-4.1
1
4.096V
4
REF
D
IN
SCK
CS/LD
V
OUT A
GND
V
CC
LTC1662
V
OUT B
0V TO 4.096V
(4mV/BIT)
0V TO 4.096V
(4mV/BIT)
1662 F03
4
3
2
1
8
5
7
6
0.1
F
10
LTC1662
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021
0.006
(0.53
0.015)
0
6
TYP
SEATING
PLANE
0.007
(0.18)
0.040
0.006
(1.02
0.15)
0.012
(0.30)
REF
0.006
0.004
(0.15
0.102)
0.034
0.004
(0.86
0.102)
0.0256
(0.65)
BSC
1
2
3
4
0.193
0.006
(4.90
0.15)
8
7 6
5
0.118
0.004*
(3.00
0.102)
0.118
0.004**
(3.00
0.102)
11
LTC1662
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N8 1098
0.100
(2.54)
BSC
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130
0.005
(3.302
0.127)
0.020
(0.508)
MIN
0.018
0.003
(0.457
0.076)
0.125
(3.175)
MIN
1
2
3
4
8
7
6
5
0.255
0.015*
(6.477
0.381)
0.400*
(10.160)
MAX
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
12
LTC1662
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit V
OUT
DAC in 8-Lead MSOP Package
V
CC
= 2.7V to 5.5V, 60
A per DAC, Rail-to-Rail Output
LTC1663
Single 10-Bit V
OUT
DAC with 2-Wire Interface in SOT-23 Package
V
CC
= 2.7V to 5.5V, Internal Reference, 60
A
LTC1664
Quad 10-Bit V
OUT
DAC in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V, 60
A per DAC, Rail-to-Rail Output
LTC1665/LTC1660
Octal 8/10-Bit V
OUT
DAC in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V, 60
A per DAC, Rail-to-Rail Output
LTC1446/LTC1446L
Dual 12-Bit V
OUT
DACs in SO-8 Package with Internal Reference
LTC1446: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1446L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1448
Dual 12-Bit V
OUT
DAC in SO-8 Package
V
CC
= 2.7V to 5.5V, External Reference Can Be Tied to V
CC
LTC1454/LTC1454L
Dual 12-Bit V
OUT
DACs in SO-16 Package with Added Functionality
LTC1454: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1454L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1458L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit V
OUT
DAC in 8-Lead MSOP Package
Low Power Multiplying V
OUT
DAC. Output Swings from
V
CC
: 2.7V to 5.5V
GND to REF. REF Input Can Be Tied to V
CC
LINEAR TECHNOLOGY CORPORATION 2000
1662i LT/TP 0300 4K PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
TYPICAL APPLICATIO
U
RELATED PARTS
+
LT1495
4
3.3V
3.3V
V
OUT A
V
OUT B
8
2
1
CS/LD
D
IN
SCK
4
6
V
CC
REF
3
2
1
8
5
GND
7
3
0.1
F
R2
FINE
1.1M
LTC1662
U1
DAC A
DAC B
R1
COARSE
11k
3.3V
0.1
F
0.1
F
V
OUT
2
0.1
F
LTC1258-2.5
1
2.5V
4
R2
1.1M
R1
11k
1662 F04
V
REF
+
V
OUT
=
CODE A
1024
CODE B
1024
R1
R2
(
)
2.5V
+
=
CODE A
1024
CODE B
1024
1
100
(
)
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5
A
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