LTC1666/LTC1667/LTC1668

APPLICATIO S

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

12-Bit, 14-Bit, 16-Bit,

50Msps DACs

50Msps Update Rate

Pin Compatible 12-Bit, 14-Bit and 16-Bit Devices

High Spectral Purity: 87dB SFDR at 1MHz f

OUT

5pV-s Glitch Impulse

Differential Current Outputs

20ns Settling Time

Low Power: 180mW from

5V Supplies

TTL/CMOS (3.3V or 5V) Inputs

Small Package: 28-Pin SSOP

The LTC

1666/LTC1667/LTC1668 are 12-/14-/16-bit,

50Msps differential current output DACs implemented on
a high performance BiCMOS process with laser trimmed,
thin-film resistors. The combination of a novel current-
steering architecture and a high performance process
produces DACs with exceptional AC and DC performance.
The LTC1668 is the first 16-bit DAC in the marketplace to
exhibit an SFDR (spurious free dynamic range) of 87dB
for an output signal frequency of 1MHz.

Operating from

5V supplies, the LTC1666/LTC1667/

LTC1668 can be configured to provide full-scale output
currents up to 10mA. The differential current outputs of
the DACs allow single-ended or true differential operation.
The 1V to 1V output compliance of the LTC1666/
LTC1667/LTC1668 allows the outputs to be connected
directly to external resistors to produce a differential out-
put voltage without degrading the converter's linearity. Al-
ternatively, the outputs can be connected to the summing
junction of a high speed operational amplifier, or to a
transformer.

The LTC1666/LTC1667/LTC1668 are pin compatible and
are available in a 28-pin SSOP and are fully specified over
the industrial temperature range.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Cellular Base Stations

Multicarrier Base Stations

Wireless Communication

Direct Digital Synthesis (DDS)

xDSL Modems

Arbitrary Waveform Generation

Automated Test Equipment

Instrumentation

LTC1668, 16-Bit, 50Msps DAC

CLOCK

INPUT

16-BIT DATA

INPUT

LADCOM

AGND DGND

CLK

DB15

DB0

1666/7/8 TA01

OUT A

0.1

LTC1668

52.3

REFIN

REFOUT

COMP1

COMP2

0.1

SET

OUT B

52.3

OUT

P-P

DIFFERENTIAL

0.1

16-BIT

HIGH SPEED

DAC

2.5V

REFERENCE

LTC1668 SFDR vs f

OUT

and f

CLOCK

OUT

(MHz)

0.1

SFDR (dB)

100

1.0

100

1666/7/8

G05

5MSPS

25MSPS

50MSPS

DIGITAL AMPLITUDE = 0dBFS

LTC1666/LTC1667/LTC1668

LTC1666CG
LTC1666IG

JMAX

= 110

= 100

C/W

ORDER PART

NUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DB14

DB15 (MSB)

CLK

DGND

COMP2

COMP1

OUT A

OUT B

LADCOM

AGND

REFIN

REFOUT

Supply Voltage (V

) ................................................ 6V

Negative Supply Voltage (V

) ............................... 6V

Total Supply Voltage (V

to V

) .......................... 12V

Digital Input Voltage .................... 0.3V to (V

+ 0.3V)

Analog Output Voltage

OUT A

and I

OUT B

) ........ (V

0.3V) to (V

+ 0.3V)

PACKAGE/ORDER I FOR ATIO

ABSOLUTE AXI U RATI GS

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DB10

DB11 (MSB)

CLK

DGND

COMP2

COMP1

OUT A

OUT B

LADCOM

AGND

REFIN

REFOUT

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DB12

DB13 (MSB)

CLK

DGND

COMP2

COMP1

OUT A

OUT B

LADCOM

AGND

REFIN

REFOUT

Power Dissipation ............................................. 500mW
Operating Temperature Range

LTC1666C/LTC1667C/LTC1668C ........... 0

C to 70

LTC1666I/LTC1667I/LTC1668I .......... 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

(Note 1)

JMAX

= 110

= 100

C/W

JMAX

= 110

= 100

C/W

LTC1668CG
LTC1668IG

ORDER PART

NUMBER

LTC1667CG
LTC1667IG

ORDER PART

NUMBER

LTC1666/LTC1667/LTC1668

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V, V

= 5V, LADCOM = AGND = DGND = 0V, I

OUTFS

= 10mA.

ELECTRICAL CHARACTERISTICS

LTC1666

LTC1667

LTC1668

SYMBOL PARAMETER

CONDITIONS

MIN

TYP MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC Accuracy (Measured at I

OUT A

, Driving a Virtual Ground)

Resolution

Bits

Monotonicity

Bits

INL

Integral Nonlinearity

(Note 2)

LSB

DNL

Differential Nonlinearity

(Note 2)

LSB

Offset Error

0.1

0.2

0.1

0.2

0.1

0.2

% FSR

Offset Error Drift

ppm/

Gain Error

Internal Reference, R

IREFIN

= 2k

% FSR

External Reference,

% FSR

REF

= 2.5V, R

IREFIN

= 2k

Gain Error Drift

Internal Reference

ppm/

External Reference

ppm/

PSRR

Power Supply

= 5V

0.1

0.1 % FSR/V

Rejection Ratio

= 5V

0.2

0.2 % FSR/V

AC Linearity

SFDR

Spurious Free Dynamic

CLK

= 25Msps, f

OUT

= 1MHz

Range to Nyquist

0dB FS Output

6dB FS Output

12dB FS Output

CLK

= 50Msps, f

OUT

= 1MHz

CLK

= 50Msps, f

OUT

= 2.5MHz

CLK

= 50Msps, f

OUT

= 5MHz

CLK

= 50Msps, f

OUT

= 20MHz

Spurious Free Dynamic

CLK

= 25Msps,

Range Within a Window

OUT

= 1MHz, 2MHz Span

CLK

= 50Msps,

OUT

= 5MHz, 4MHz Span

THD

Total Harmonic Distortion f

CLK

= 25Msps, f

OUT

= 1MHz

CLK

= 50Msps, f

OUT

= 5MHz

LTC1666/LTC1667/LTC1668

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 5V, V

= 5V, LADCOM = AGND = DGND = 0V, I

OUTFS

= 10mA.

ELECTRICAL CHARACTERISTICS

LTC1666/LTC1667/LTC1668

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Analog Output

OUTFS

Full-Scale Output Current

Output Compliance Range

= 10mA

Output Resistance; R

IOUT A

, R

IOUT B

OUT A, B

to LADCOM

0.7

1.1

1.5

Output Capacitance

Reference Output

Reference Voltage

REFOUT Tied to I

REFIN

Through 2k

2.475

2.5

2.525

Reference Output Drift

ppm/

Reference Output Load Regulation

LOAD

= 0mA to 5mA

mV/mA

Reference Input

Reference Small-Signal Bandwidth

= 10mA, C

COMP1

= 0.1

kHz

Power Supply

Positive Supply Voltage

4.75

5.25

Negative Supply Voltage

4.75

5.25

Positive Supply Current

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

Negative Supply Current

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

DIS

Power Dissipation

= 10mA, f

CLK

= 25Msps, f

OUT

= 1MHz

180

= 1mA, f

CLK

= 25Msps, f

OUT

= 1MHz

Dynamic Performance (Differential Transformer Coupled Output, 50

Double Terminated, Unless Otherwise Noted)

CLOCK

Maximum Update Rate

Msps

Output Settling Time

To 0.1% FSR

Output Propagation Delay

Glitch Impulse

Single Ended

pV-s

Differential

pV-s

Output Rise Time

Output Fall Time

Output Noise

pA/

Digital Inputs

Digital High Input Voltage

2.4

Digital Low Input Voltage

0.8

Digital Input Current

Digital Input Capacitance

Input Setup Time

Input Hold Time

CLKH

Clock High Time

CLKL

Clock Low Time

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: For the LTC1666,

1LSB =

0.024% of full scale;

for the LTC1667,

1LSB =

0.006% of full scale =

61ppm of full scale;

for the LTC1668,

1LSB =

0.0015% of full scale =

15.3ppm of full scale.

LTC1666/LTC1667/LTC1668

FREQUENCY (MHz)

100

SIGNAL AMPLITUDE (dBFS)

1666/7/8 G01

SFDR = 87dB
f

CLOCK

= 50MSPS

OUT

= 1.002MHz

AMPL = 0dBFS

= 8.25dBm

TYPICAL PERFOR A CE CHARACTERISTICS

Single Tone SFDR at 50MSPS

2-Tone SFDR

FREQUENCY (MHz)

100

SIGNAL AMPLITUDE (dBFS)

1666/7/8 G02

4.5

5.0

5.5

SFDR > 86dB
f

CLOCK

= 50MSPS

OUT1

= 4.9MHz

OUT2

= 5.09MHz

AMPL = 0dBFS

4-Tone SFDR, f

CLOCK

= 50MSPS

4-Tone SFDR, f

CLOCK

= 5MSPS

SFDR vs f

OUT

and Digital Amplitude

(dBFS) at f

CLOCK

= 5MSPS

SFDR vs f

OUT

and f

CLOCK

FREQUENCY (MHz)

100

110

SIGNAL AMPLITUDE (dBFS)

1666/7/8 G03

4.6

8.2

11.8

15.4

SFDR > 74dB
f

CLOCK

= 50MSPS

OUT1

= 5.02MHz

OUT2

= 6.51MHz

OUT3

= 11.02MHz

OUT4

= 12.51MHz

AMPL = 0dBFS

FREQUENCY (MHz)

100

110

SIGNAL AMPLITUDE (dBFS)

1666/7/8 G04

0.1

0.46

0.82

1.18

1.54

1.9

SFDR > 82dB
f

CLOCK

= 5MSPS

OUT1

= 0.5MHz

OUT2

= 0.65MHz

OUT3

= 1.10MHz

OUT4

= 1.25MHz

AMPL = 0dBFS

OUT

(MHz)

0.1

SFDR (dB)

100

1.0

100

1666/7/8

G05

5MSPS

25MSPS

50MSPS

DIGITAL AMPLITUDE = 0dBFS

OUT

(MHz)

100

SFDR (dB)

1666/7/8 G06

0.4

0.8

1.2

1.6

2.0

12dBFS

6dBFS

0dBFS

(LTC1668)

OUT

(MHz)

SFDR (dB)

1666/7/8 G07

12dBFS

6dBFS

0dBFS

OUT

(MHz)

SFDR (dB)

1666/7/8 G08

12dBFS

6dBFS

0dBFS

OUT

(MHz)

SFDR (dB)

1666/7/8 G09

2.5

7.5

DIGITAL AMPLITUDE = 0dBFS

OUTFS

= 2.5mA

OUTFS

= 5mA

OUTFS

= 10mA

SFDR vs f

OUT

and Digital Amplitude

(dBFS) at f

CLOCK

= 25MSPS

SFDR vs f

OUT

and Digital Amplitude

(dBFS) at f

CLOCK

= 50MSPS

SFDR vs f

OUT

and I

OUTFS

CLOCK

= 25MSPS

LTC1666/LTC1667/LTC1668

Integral Nonlinearity

DIGITAL INPUT CODE

INTEGRAL NONLINEARITY (LSB)

16384

32768

1666/7/8 G18

49152

65535

TYPICAL PERFOR A CE CHARACTERISTICS

SFDR vs Digital Amplitude (dBFS)
and f

CLOCK

at f

OUT

= f

CLOCK

/11

Single-Ended Outputs
Full-Scale Transition

Differential Output
Full-Scale Transition

Single-Ended Output
Full-Scale Transition

Differential Output
Full-Scale Transition

Differential Midscale
Glitch Impulse

Single-Ended Midscale
Glitch Impulse

DIGITAL AMPLITUDE (dBFS)

100

SFDR (dB)

1666/7/8 G10

455kHz AT 5MSPS

4.55MHz AT 50MSPS

2.277MHz AT 25MSPS

DIGITAL AMPLITUDE (dBFS)

100

SFDR (dB)

1666/7/8 G11

1MHz AT 5MSPS

10MHz AT 50MSPS

5MHz AT 25MSPS

100mV

/DIV

CLK IN
5V/DIV

1666/7/8 G12

5ns/DIV

V(I

OUTB

)

V(I

OUTA

)

FFFF

0000

CLOCK INPUT

SFDR vs Digital Amplitude (dBFS)
and f

CLOCK

at f

OUT

= f

CLOCK

100mV

/DIV

CLK IN
5V/DIV

1666/7/8 G13

5ns/DIV

V(I

OUTA

) V(I

OUTB

)

FFFF

0000

100mV

/DIV

CLK IN
5V/DIV

1666/7/8 G14

5ns/DIV

V(I

OUTA

)

V(I

OUTB

)

FFFF

0000

CLOCK INPUT

100mV

/DIV

CLK IN
5V/DIV

1666/7/8 G15

5ns/DIV

V(I

OUTA

) V(I

OUTB

)

FFFF

0000

1mV/DIV

CLK IN
5V/DIV

1666/7/8 G16

5ns/DIV

V(I

OUTA

), V(I

OUTB

)

7FFF

8000

1mV/DIV

CLK IN
5V/DIV

1666/7/8 G17

5ns/DIV

V(I

OUTA

) V(I

OUTB

)

7FFF

8000

(LTC1668)

LTC1666/LTC1667/LTC1668

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Nonlinearity

DIGITAL INPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

1.0

65535

1666/7/8 G19

1.0

2.0

16384

32768

49152

2.0

0.5

1.5

(LTC1668)

PI FU CTIO S

LTC1666

REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1

F bypass capacitor

to AGND.

REFIN

(Pin 16): Reference Input Current. Nominal value is

1.25mA for I

= 10mA. I

= I

REFIN

· 8.

AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.

OUT B

(Pin 19): Complementary DAC Output Current. Full-

scale output current occurs when all data bits are 0s.

OUT A

(Pin 20): DAC Output Current. Full-scale output

current occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V

with 0.1

COMP2 (Pin 22): Internal Bypass Point. Bypass to V

with 0.1

(Pin 23): Negative Supply Voltage. Nominal value is

5V.

DGND (Pin 24): Digital Ground.

(Pin 25): Positive Supply Voltage. Nominal value is 5V.

CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.

DB11 to DB0 (Pins 27, 28, 1 to 10 ): Digital Input Data Bits.

LTC1666/LTC1667/LTC1668

LTC1667

REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1

F bypass capacitor

to AGND.

REFIN

(Pin 16): Reference Input Current. Nominal value is

1.25mA for I

= 10mA. I

= I

REFIN

· 8.

AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.

OUT B

(Pin 19): Complementary DAC Output Current. Full-

scale output current occurs when all data bits are 0s.

OUT A

(Pin 20): DAC Output Current. Full-scale output

current occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V

with 0.1

COMP2 (Pin 22): Internal Bypass Point. Bypass to V

with 0.1

(Pin 23): Negative Supply Voltage. Nominal value is

5V.

DGND (Pin 24): Digital Ground.

(Pin 25): Positive Supply Voltage. Nominal value is 5V.

CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.

DB13 to DB0 (Pins 27, 28, 1 to 12 ): Digital Input Data Bits.

LTC1668

REFOUT (Pin 15): Internal Reference Voltage Output.
Nominal value is 2.5V. Requires a 0.1

F bypass capacitor

to AGND.

REFIN

(Pin 16): Reference Input Current. Nominal value is

1.25mA for I

= 10mA. I

= I

REFIN

· 8.

AGND (Pin 17): Analog Ground.

LADCOM (Pin 18): Attenuator Ladder Common. Normally
tied to GND.

OUT B

(Pin 19): Complementary DAC Output Current. Full-

scale output current occurs when all data bits are 0s.

OUT A

(Pin 20): DAC Output Current. Full-scale output

current occurs when all data bits are 1s.

COMP1 (Pin 21): Current Source Control Amplifier Com-
pensation. Bypass to V

with 0.1

COMP2 (Pin 22): Internal Bypass Point. Bypass to V

with 0.1

(Pin 23): Negative Supply Voltage. Nominal value is

5V.

DGND (Pin 24): Digital Ground.

(Pin 25): Positive Supply Voltage. Nominal value is 5V.

CLK (Pin 26): Clock Input. Data is latched and the output
is updated on positive edge of clock.

DB15 to DB0 (Pins 27, 28, 1 to 14 ): Digital Input Data Bits.

PI FU CTIO S

LTC1666/LTC1667/LTC1668

BLOCK DIAGRA

REFIN

INT

SET

0.1

REFOUT

REF

COMP1

COMP2

2.5V

REFERENCE

ATTENUATOR

LADDER

LSB SWITCHES

INPUT LATCHES

CLOCK

INPUT

12-BIT

DATA INPUT

SEGMENTED SWITCHES

FOR DB15DB12

CURRENT SOURCE ARRAY

AGND

DGND

CLK

DB0

DB11

· · ·

1666 BD

LADCOM

OUT A

OUT B

52.3

OUT

P-P

DIFFERENTIAL

0.1

REFIN

INT

SET

0.1

REFOUT

REF

COMP1

COMP2

2.5V

REFERENCE

ATTENUATOR

LADDER

LSB SWITCHES

INPUT LATCHES

CLOCK

INPUT

14-BIT

DATA INPUT

SEGMENTED SWITCHES

FOR DB15DB12

CURRENT SOURCE ARRAY

AGND

DGND

CLK

DB0

DB13

· · ·

1667 BD

LADCOM

OUT A

OUT B

52.3

OUT

P-P

DIFFERENTIAL

0.1

LTC1666

LTC1667

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

Theory of Operation

The LTC1666/LTC1667/LTC1668 are high speed current
steering 12-/14-/16-bit DACs made on an advanced
BiCMOS process. Precision thin film resistors and well
matched bipolar transistors result in excellent DC linearity
and stability. A low glitch current switching design gives
excellent AC performance at sample rates up to 50Msps.
The devices are complete with a 2.5V internal bandgap
reference and edge triggered latches, and set a new
standard for DAC applications requiring very high dy-
namic range at output frequencies up to several mega-
hertz.

Referring to the Block Diagrams, the DACs contain an
array of current sources that are steered to I

OUTA

or I

OUTB

with NMOS differential current switches. The four most
significant bits are made up of 15 current segments of
equal weight. The remaining lower bits are binary weighted,
using a combination of current scaling and a differential
resistive attenuator ladder. All bits and segments are
precisely matched, both in current weight for DC linearity,
and in switch timing for low glitch impulse and low
spurious tone AC performance.

Setting the Full-Scale Current, I

OUTFS

The full-scale DAC output current, I

OUTFS

, is nominally

10mA, and can be adjusted down to 1mA. Placing a
resistor, R

SET

, between the REFOUT pin, and the I

REFIN

sets I

OUTFS

as follows.

The internal reference control loop amplifier maintains a
virtual ground at I

REFIN

by servoing the internal current

source, I

INT

, to sink the exact current flowing into I

REFIN

INT

is a scaled replica of the DAC current sources and

OUTFS

= 8 · (I

INT

), therefore:

OUTFS

= 8 · (I

REFIN

) = 8 · (V

REF

SET

)

(1)

For example, if R

SET

= 2k and is tied to V

REF

= REFOUT =

2.5V, I

REFIN

= 2.5/2k = 1.25mA and I

OUTFS

= 8 · (1.25mA)

= 10mA.

The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC perfor-
mance, C

COMP1

should be connected to V

and be placed

very close to the package (less than 0.1").

For fixed reference voltage applications, C

COMP1

should

be 0.1

F or more. The reference control loop small-signal

bandwidth is approximately 1/(2

) · C

COMP1

· 80 or 20kHz

for C

COMP1

= 0.1

Reference Operation

The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to I

REFIN

, corresponding to a

1.25mA load (I

OUTFS

= 10mA). REFOUT has nominal

output impedance of 6

, or 0.24% per mA, so it must be

buffered to drive any additional external load. A 0.1

capacitor is required on the REFOUT pin for compensa-
tion. Note that this capacitor is required for stability, even
if the internal reference is not being used.

External Reference Operation

Figure 1, shows how to use an external reference to control
the LTC1666/LTC1667/LTC1668 full-scale current.

Figure 1. Using the LTC1666/LTC1667/LTC1668
with an External Reference

REFOUT

REFIN

2.5V

REFERENCE

SET

0.1

1666/7/8 F02

EXTERNAL

REFERENCE

LTC1666/
LTC1667/

LTC1668

LTC1666/LTC1667/LTC1668

Adjusting the Full-Scale Output

In Figure 2, a serial interfaced DAC is used to set I

OUTFS

The LTC1661 is a dual 10-bit V

OUT

DAC with a buffered

voltage output that swings from 0V to V

REF

DAC Transfer Function

The LTC1666/LTC1667/LTC1668 use straight binary digital
coding. The complementary current outputs, I

OUT A

and I

OUT

, sink current from 0 to I

OUTFS

. For I

OUTFS

= 10mA (nomi-

nal), I

OUT A

swings from 0mA when all bits are low (e.g.,

Code = 0) to 10mA when all bits are high (e.g., Code = 65535
for LTC1668) (decimal representation). I

OUT B

is comple-

mentary to I

OUT A

. I

OUT A

and I

OUT B

are given by the following

formulas:

LTC1666:

OUT A

= I

OUTFS

· (DAC Code/4096)

(2)

OUT B

= I

OUTFS

· (4095 DAC Code)/4096

(3)

LTC1667:

OUT A

= I

OUTFS

· (DAC Code/16384)

(4)

OUT B

= I

OUTFS

· (16383 DAC Code)/16384

(5)

LTC1668:

OUT A

= I

OUTFS

· (DAC Code/65536)

(6)

OUT B

= I

OUTFS

· (65535 DAC Code)/65536

(7)

In typical applications, the LTC1666/LTC1667/LTC1668
differential output currents either drive a resistive load
directly or drive an equivalent resistive load through a
transformer, or as the feedback resistor of an I-to-V
converter. The voltage outputs generated by the I

OUT A

and

OUT B

output currents are then:

Figure 2. Adjusting the Full-Scale Current of
the LTC1666/LTC1667/LTC1668 with a DAC

APPLICATIO S I FOR ATIO

OUT A

= I

OUT A

· R

LOAD

(8)

OUT B

= I

OUT B

· R

LOAD

(9)

The differential voltage is:

DIFF

= V

OUT A

OUT B

(10)

= (I

OUT A

OUT B

) · (R

LOAD

)

Substituting the values found earlier for I

OUT A

, I

OUT B

and

OUTFS

(LTC1668):

DIFF

= {2 · DAC Code 65535)/65536} · 8 ·

LOAD

SET

) · (V

REF

)

(11)

From these equations some of the advantages of differen-
tial mode operation can be seen. First, any common mode
noise or error on I

OUT A

and I

OUT B

is cancelled. Second, the

signal power is twice as large as in the single-ended case.
Third, any errors and noise that multiply times I

OUT A

and

OUT B

, such as reference or I

OUTFS

noise, cancel near

midscale, where AC signal waveforms tend to spend the
most time. Fourth, this transfer function is bipolar; e.g. the
output swings positive and negative around a zero output
at mid-scale input, which is more convenient for AC
applications.

Note that the term (R

LOAD

SET

) appears in both the

differential and single-ended transfer functions. This means
that the Gain Error of the DAC depends on the ratio of
R

LOAD

to R

SET

, and the Gain Error tempco is affected by the

temperature tracking of R

LOAD

with R

SET

. Note also that

the absolute tempco of R

LOAD

is very critical for DC

nonlinearity. As the DAC output changes from 0mA to
10mA the R

LOAD

resistor will heat up slightly, and even a

very low tempco can produce enough INL bowing to be
significant at the 16-bit level. This effect disappears with
medium to high frequency AC signals due to the slow
thermal time constant of the load resistor.

Analog Outputs

The LTC1666/LTC1667/LTC1668 have two complemen-
tary current outputs, I

OUT A

and I

OUT B

(see DAC Transfer

Function). The output impedance of I

OUT A

and I

OUT B

IOUT A

and R

IOUT B

) is typically 1.1k

to LADCOM. (See

Figure 3.)

REFIN

2.5V

REFERENCE

SET

1.9k

REF

0.1

1/2 LTC1661

1666/7/8 F03

LTC1666/
LTC1667/

LTC1668

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

LADCOM

The LADCOM pin is the common connection for the
internal DAC attenuator ladder. It usually is tied to analog
ground, but more generally it should connect to the same
potential as the load resistors on I

OUT A

and I

OUT B

. The

LADCOM pin carries a constant current to V

of approxi-

mately 0.32 · (I

OUTFS

), plus any current that flows from

OUT A

and I

OUT B

through the R

IOUT A

and R

IOUT B

resistors.

Output Compliance

The specified output compliance voltage range is

1V. The

DC linearity specifications, INL and DNL, are trimmed and
guaranteed on I

OUT A

into the virtual ground of an

I-to-V converter, but are typically very good over the full
output compliance range. Above 1V the output current will
start to increase as the DAC current steering switch
impedance decreases, degrading both DC and AC linear-
ity. Below 1V, the DAC switches will start to approach the
transition from saturation to linear region. This will de-
grade AC performance first, due to nonlinear capacitance
and increased glitch impulse. AC distortion performance
is optimal at amplitudes less than

0.5V

P-P

on I

OUT A

and

OUT B

due to nonlinear capacitance and other large-signal

effects. At first glance, it may seem counter-intuitive to
decrease the signal amplitude when trying to optimize
SFDR. However, the error sources that affect AC perfor-
mance generally behave as additive currents, so decreas-
ing the load impedance to reduce signal voltage amplitude
will reduce most spurious signals by the same amount.

Figure 4. AC Characterization Setup (LTC1668)

16-BIT

HIGH SPEED

DAC

HP1663EA

LOGIC ANALYZER WITH

PATTERN GENERATOR

LADCOM

AGND DGND

CLK

DB15

DB0

DIGITAL
DATA

CLK
IN

1666/7/8 F05

OUT A

0.1

LTC1668

REFIN

REFOUT

COMP1

COMP2

0.1

OUT 1 OUT 2

0.1

SET

OUT B

HP8110A DUAL

PULSE GENERATOR

LOW JITTER

CLOCK SOURCE

CLK
IN

0.1

TO HP3589A
SPECTRUM
ANALYZER
50

INPUT

110

MINI-CIRCUITS

T11T

2.5V

REFERENCE

Figure 3. Equivalent Analog Output Circuit

IOUT B

1.1k

5pF

1666/7/8 F04

IOUT A

1.1k

LADCOM

OUT A

OUT B

52.3

LTC1666/LTC1667/LTC1668

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

Operating with Reduced Output Currents

The LTC1666/LTC1667/LTC1668 are specified to operate
with full-scale output current, I

OUTFS

, from the nominal

10mA down to 1mA. This can be useful to reduce power
dissipation or to adjust full-scale value. However, the DC
and AC accuracy is specified only at I

OUTFS

= 10mA, and

DC and AC accuracy will fall off significantly at lower I

OUTFS

values. At I

OUTFS

= 1mA, the LTC1668 INL and DNL

typically degrade to the 14-bit to 13-bit level, compared to
16-bit to 15-bit typical accuracy at 10mA I

OUTFS

. Increas-

ing I

OUTFS

from 1mA, the accuracy improves rapidly,

roughly in proportion to 1/I

OUTFS

. Note that the AC perfor-

mance (SFDR) is affected much more by reduced I

OUTFS

than it is by reduced digital amplitude (see Typical Perfor-
mance Characteristics). Therefore it is usually better to
make large gain adjustments digitally, keeping I

OUTFS

equal to 10mA.

Output Configurations

Based on the specific application requirements, the
LTC1666/LTC1667/LTC1668 allow a choice of the best of
several output configurations. Voltage outputs can be
generated by external load resistors, transformer coupling
or with an op amp I-to-V converter. Single-ended DAC
output configurations use only one of the outputs, prefer-
ably I

OUT A

, to produce a single-ended voltage output.

Differential mode configurations use the difference be-
tween I

OUT A

and I

OUT B

to generate an output voltage,

DIFF

, as shown in equation 11. Differential mode gives

much better accuracy in most AC applications. Because
the DAC chip is the point of interface between the digital
input signals and the analog output, some small amount
of noise coupling to I

OUT A

and I

OUT B

is unavoidable. Most

of that digital noise is common mode and is canceled by
the differential mode circuit. Other significant digital noise
components can be modeled as V

REF

or I

OUTFS

noise. In

single-ended mode, I

OUTFS

noise is gone at zero scale and

is fully present at full scale. In differential mode, I

OUTFS

noise is cancelled at midscale input, corresponding to zero
analog output. Many AC signals, including broadband and
multitone communications signals with high peak to aver-
age ratios, stay mostly near midscale.

Differential Transformer-Coupled Outputs

Differential transformer-coupled output configurations
usually give the best AC performance. An example is
shown in Figure 5. The advantages of transformer cou-
pling include excellent rejection of common mode distor-
tion and noise over a broad frequency range and conve-
nient differential-to-single-ended conversion with isola-
tion or level shifting. Also, as much as twice the power can
be delivered to the load, and impedance matching can be
accomplished by selecting the appropriate transformer
turns ratio. The center tap on the primary side of the
transformer is tied to ground to provide the DC current
path for I

OUT A

and I

OUT B

. For low distortion, the DC

average of the I

OUT A

and I

OUT B

currents must be exactly

equal to avoid biasing the core. This is especially impor-
tant for compact RF transformers with small cores. The
circuit in Figure 5 uses a Mini-Circuits T1-1T RF trans-
former with a 1:1 turns ratio. The load resistance on
I

OUT A

and I

OUT B

is equivalent to a single differential

resistor of 50

, and the 1:1 turns ratio means the output

impedance from the transformer is 50

. Note that the

load resistors are optional, and they dissipate half of the
output power. However, in lab environments or when
driving long transmission lines it is very desirable to have
a 50

output impedance. This could also be done with a

resistor at the transformer secondary, but putting

the load resistors on I

OUT A

and I

OUT B

is preferred since

it reduces the current through the transformer. At signal
frequencies lower than about 1MHz, the transformer core
size required to maintain low distortion gets larger, and at
some lower frequencies this becomes impractical.

Figure 5. Differential Transformer-Coupled Outputs

OUT B

OUT A

110

MINI-CIRCUITS

T1-1T

LOAD

1666/7/8 F06

LTC1666/
LTC1667/

LTC1668

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

Resistor Loaded Outputs

A differential resistor loaded output configuration is shown
in Figure 6. It is simple and economical, but it can drive
only differential loads with impedance levels and ampli-
tudes appropriate for the DAC outputs.

The recommended single-ended resistor loaded configu-
ration is essentially the same circuit as the differential
resistor loaded, case--simply use the I

OUT A

output,

referred to ground. Rather than tying the unused I

OUT B

output to ground, it is preferred to load it with the equiva-
lent R

LOAD

of I

OUT A

. Then I

OUT B

will still swing with a

waveform complementary to I

OUT A

helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings

1V around ground.

Figure 8 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1's slewing capabilities.

Digital Interface

The LTC1666/LTC1667/LTC1668 have parallel inputs that
are latched on the rising edge of the clock input. They
accept CMOS levels from either 5V or 3.3V logic and can
accept clock rates of up to 50MHz.

Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, V

2.4V min, V

= 0.8V max, work with 3.3V or 5V CMOS

levels over temperature. The guaranteed setup time, t

is 8ns minimum and the hold time, t

, is 4ns minimum.

The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1666/LTC1667/LTC1668 to be clocked at up to 50Msps
minimum.

For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor-
tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in-

Op Amp I to V Converter Outputs

Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 7.

This circuit complements the capabilities of the trans-
former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor-
mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and

Figure 6. Differential Resistor-Loaded Output

OUT B

OUT A

52.3

1666/7/8 F07

LTC1666/
LTC1667/

LTC1668

Figure 8. Single-Ended Op Amp I to V Converter

200

1666/7/8 F09

OUT A

OUT B

LADCOM

200

OUT

0V TO 2V

OUTFS

10mA

OUT

1812

LTC1666/
LTC1667/

LTC1668

OUT B

OUT A

52.3

500

52.3

1666/7/8 F08

200

500

200

60pF

LT1809

10dBm

OUT

LTC1666/
LTC1667/

LTC1668

Figure 7. Differential to Single-Ended Op Amp I-V Converter

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

cluding the output signal band of interest. Therefore, any
direct coupling of the digital signals to the analog output
will produce spurious tones that vary with the exact digital
input pattern.

Clock jitter should be minimized to avoid degrading the
noise floor of the device in AC applications, especially
where high output frequencies are being generated. Any
noise coupling from the digital inputs to the clock input will
cause phase modulation of the clock signal and the DAC
waveform, and can produce spurious tones. It is normally
best to place the digital data transitions near the falling
clock edge, well away from the active rising clock edge.
Because the clock signal contains spectral components
only at the sampling frequency and its multiples, it is
usually not a source of in band spurious tones. Overall, it
is better to treat the clock as you would an analog signal
and route it separately from the digital data input signals.
The clock trace should be routed either over the analog
ground plane or over its own section of the ground plane.
The clock line needs to have accurately controlled imped-
ance and should be well terminated near the LTC1666/
LTC1667/LTC1668.

Printed Circuit Board Layout Considerations--
Grounding, Bypassing and Output Signal Routing

The close proximity of high frequency digital data lines and
high dynamic range, wide-band analog signals makes
clean printed circuit board design and layout an absolute

necessity. Figures 11 to 15 are the printed circuit board
layers for an AC evaluation circuit for the LTC1668. Ground
planes should be split between digital and analog sections
as shown. All bypass capacitors should have minimum
trace length and be ceramic 0.1

F or larger with low ESR.

Bypass capacitors are required on V

, V

and REFOUT,

and all connected to the AGND plane. The COMP2 pin ties
to a node in the output current switching circuitry, and it
requires a 0.1

F bypass capacitor. It should be bypassed

to V

along with COMP1. The AGND and DGND pins

should both tie directly to the AGND plane, and the tie point
between the AGND and DGND planes should nominally be
near the DGND pin. LADCOM should either be tied directly
to the AGND plane or be bypassed to AGND. The I

OUT A

and

OUT B

traces should be close together, short, and well

matched for good AC CMRR. The transformer output
ground should be capable of optionally being isolated or
being tied to the AGND plane, depending on which gives
better performance in the system.

Suggested Evaluation Circuit

Figure 10 is the schematic and Figures 11 to 15 are the
circuit board layouts for a suggested evaluation circuit,
DC245A. The circuit can be programmed with component
selection and jumpers for a variety of differentially coupled
transformer output and differential and single-ended re-
sistor loaded output configurations.

REFOUT

LADCOM

OUT A

OUT

OUT B

REFIN

CLK

LTC1668

Q-CHANNEL

REFOUT

LADCOM

OUT A

OUT B

REFIN

CLK

LTC1668

I-CHANNEL

52.3

LOW-PASS

FILTER

LOW-PASS

FILTER

CLOCK

INPUT

REF

1/2 LTC1661

SERIAL

INPUT

2.1k

21k

0.1

LOCAL

OSCILLATOR

QAM
OUTPUT

QUADRATURE

MODULATOR

RELATIVE GAIN

ADJUSTMENT RANGE

1666/7/8 F10

Figure 9. QAM Modulation Using LTC1668 with
Digitally Controlled I vs Q Channel Gain Adjustment

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

Figure 10. Suggested Evaluation Circuit

OUT

OUT B

EXTCLK

JP9

1.91k

0.1%

200

JP1

C17

0.1

L
TC1668

0.1

TP5

TESTPOINT WHT

0.1

C18

0.1

C10

0.1

C11

0.1

0.1%

R12

49.9

JP6

R10

0.1%

C12

22pF

C12

22pF

0.1

JP5

TP3

TESTPOINT

WHT

JP7

JP3

110

JP4

JP2

REFOUT

REFIN

DB15 (MSB)

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

CLK

OUT A

OUT B

COMP1

COMP2

LADCOM

AGND

DGND

OUT A

MINI-

CIRCUITS

T11T

JP8

TP4

TESTPOINT

WHT

RN5

5VD

J10

TP6

TESTPOINT RED

L
T1460DCS8-2.5

AMP

102159-9

RN6

TP2

TESTPOINT WHT

2.5V

REF

TP10

TESTPOINT BLK

TP1

OUT

GND

0.1

EXTREF

C19

0.1

C14

25V

AGND

DGND

TP8

TESTPOINT RED

GROUND PLANE

TIE POINT

C20

0.1

C16

25V

1666/7/8

F11

C22

0.1

J11

TP7

TESTPOINT RED

TP9

TESTPOINT BLK

C23

0.1

C15

25V

C21

0.1

OPTIONAL

SIP

PULL-UP/

PULL-DOWN

RESISTORS

(NOT

INST

ALLED)

OPTIONAL

SIP

PULL-UP/

PULL-DOWN

RESISTORS

(NOT

INST

ALLED)

5VD

R16

R15

R14

R13

LTC1666/LTC1667/LTC1668

PACKAGE DESCRIPTIO

G28 SSOP 0501

.13 .22

(.005 .009)

.55 .95

(.022 .037)

5.20 5.38**

(.205 .212)

7.65 7.90

(.301 .311)

2 3

6 7 8

9 10 11 12

10.07 10.33*

(.397 .407)

22 21 20 19 18 17 16 15

1.73 1.99

(.068 .078)

.05 .21

(.002 .008)

.65

(.0256)

BSC

.25 .38

(.010 .015)

MILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

LTC1666/LTC1667/LTC1668

LINEAR TECHNOLOGY CORPORATION 2000

166678f LT/TP 0701 2K · PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

RELATED PARTS

TYPICAL APPLICATIO

Figure 16. Arbitrary Waveform Generator Has

10V Output Swing, 50Msps DAC Update Rate

REFOUT

LADCOM

OUT A

OUT B

REFIN

LTC1668

52.3

SET

AGND DGND CLK DB15-DB0

COMP1
COMP2

0.1

CLOCK

INPUT

18-BIT

DATA

INPUT

100pF

LT1227

OUT

10V

1666/7/8 F17

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC1406

8-Bit, 20Msps ADC

Undersampling Capability Up to 70MHz Input

LTC1411

14-Bit, 2.5Msps ADC

LTC1420

12-Bit, 10Msps ADC

72dB SINAD at 5MHz f

LTC1604/LTC1608

16-Bit, 333ksps/500ksps ADCs

16-Bit, No Missing Codes, 90dB SINAD, 100dB THD

DACs

LTC1591/LTC1597

Parallel 14/16-Bit Current Output DACs

On-Chip 4-Quadrant Resistors

LTC1595/LTC1596

Serial 16-Bit Current Output DACs

Low Glitch,

1LSB Maximum INL, DNL

LTC1650

Serial 16-Bit Voltage Output DAC

Low Power, Deglitched, 4-Quadrant Multiplying V

OUT

DAC,

4.5V Output Swing, 4

s Settling Time

LTC1655(L)

Single 16-Bit V

OUT

DAC with Serial Interface in SO-8

5V (3V) Single Supply, Rail-to-Rail Output Swing

LTC1657(L)

16-Bit Parallel Voltage Output DAC

5V (3V) Low Power, 16-Bit Monotonic Over Temp., Multiplying Capability

AMPLIFIERs

LT1809/LT1810

Single/Dual 180MHz, 350V/

s Op Amp

Rail-to-Rail Input and Output, Low Distortion

LT1812/LT1813

Single/Dual 100MHz, 750V/

s Op Amp

3.6mA Supply Current, 8nV/

Hz Input Noise Voltage

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1666

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1666