1
LTC1709-8/LTC1709-9
2-Phase, 5-Bit VID,
Current Mode, High Efficiency,
Synchronous Step-Down Switching Regulators
May 2000
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a trademark of Linear Technology Corporation.
The LTC
1709-8/LTC1709-9 are 2-phase, VID program-
mable, synchronous step-down switching regulator con-
trollers that drive two all N-channel external power MOSFET
stages in a fixed frequency architecture. The 2-phase
controller drives its two output stages out of phase at
frequencies up to 300kHz to minimize the RMS ripple
currents in both input and output capacitors. The 2-phase
technique effectively multiplies the fundamental frequency
by two, improving transient response while operating
each channel at an optimum frequency for efficiency.
Thermal design is also simplified.
An internal differential amplifier provides true remote
sensing of the regulated supply's positive and negative
output terminals as required for high current applications.
The RUN/SS pin provides soft-start and optional timed,
short-circuit shutdown. Current foldback limits MOSFET
dissipation during short-circuit conditions when the
overcurrent latchoff is disabled. OPTI-LOOP compensa-
tion allows the transient response to be optimized for a
wide range of output capacitors and ESR values. The
LTC1709-8/LTC1709-9 implement two different VID
tables compliant with VRM8.4 and VRM9.0 respectively.
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
Figure 1. High Current Dual Phase Step-Down Converter
s
Workstations
s
Internet Servers
s
Large Memory Arrays
s
DC Power Distribution Systems
s
Single Controller Operates Two Output Stages:
Antiphase Reducing Required Input Capacitance
and Power Supply Induced Noise
s
Two 5-Bit Desktop VID Codes:
LTC1709-8 For VRM8.4 (V
OUT
from 1.3V to 3.5V)
LTC1709-9 For VRM9.0 (V
OUT
from 1.1V to 1.85V)
s
Current Mode Control Ensures Best Current Sharing
s
True Remote Sensing Differential Amplifier
s
Power Good Output Indicator
s
OPTI-LOOP
TM
Compensation Minimizes C
OUT
s
Programmable Fixed Frequency: 150kHz to 300kHz
s
1% Output Voltage Accuracy
s
Wide V
IN
Range: 4V to 36V Operation
s
Adjustable Soft-Start Current Ramping
s
Internal Current Foldback and Short-Circuit Shutdown
s
Overvoltage Soft Latch Eliminates Nuisance Trips
s
Low Shutdown Current: 20
A
s
Available in 36-Lead SSOP Package
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Final Electrical Specifications
17097 F01
TG1
BOOST1
SW1
BG1
PGND
SENSE1
+
SENSE1
TG2
BOOST2
SW2
BG2
INTV
CC
SENSE2
+
SENSE2
V
IN
RUN/SS
V
DIFFOUT
I
TH
ATTENIN
ATTENOUT
EAIN
VID0VID4
V
OS
V
OS
+
LTC1709-8
SGND
PGOOD
0.1
F
220pF
5 VID BITS
S
S
3.3k
+
10
F
35V
4
+
+
C
OUT
1000
F
4V
2
V
OUT
1.3V TO 3.5V
40A
1
H
0.002
0.002
V
IN
5V TO 28V
1
H
0.47
F
0.47
F
10
F
2
LTC1709-8/LTC1709-9
ORDER PART
NUMBER
LTC1709EG-8
LTC1709EG-9
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
T
JMAX
= 125
C,
JA
= 85
C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 15V, V
BIAS
= 5V, V
RUN/SS
= 5V unless otherwise noted.
(Note 1)
Input Supply Voltage (V
IN
).........................36V to 0.3V
Topside Driver Voltages (BOOST1,2) .........42V to 0.3V
Switch Voltage (SW1, 2) .............................36V to 5 V
SENSE1
+
, SENSE2
+
, SENSE1
,
SENSE2
Voltages ........................ (1.1)INTV
CC
to 0.3V
EAIN, V
OS
+
, V
OS
, EXTV
CC
, INTV
CC
, RUN/SS,
V
BIAS
, ATTENIN, ATTENOUT, PGOOD,
VID0VID4, Voltages ...................................7V to 0.3V
Boosted Driver Voltage (BOOST-SW) .......... 7V to 0.3V
PLLFLTR, PLLIN, V
DIFFOUT
Voltages .... INTV
CC
to 0.3V
I
TH
Voltage ................................................2.7V to 0.3V
Peak Output Current <1
s(TGL1,2, BG1,2) ................ 3A
INTV
CC
RMS Output Current ................................ 50mA
Operating Ambient Temperature Range
(Note 2) ................................................ 40
C to 85
C
Junction Temperature (Note 3) ............................. 125
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
EAIN
Regulated Feedback Voltage
I
TH
Voltage = 1.2V (Note 4)
q
0.792
0.800
0.808
V
V
SENSEMAX
Maximum Current Sense Threshold
V
SENSE
= 5V
q
62
75
88
mV
I
INEAIN
Feedback Current
(Note 4)
5
50
nA
V
LOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop,
I
TH
Voltage: 1.2V to 0.7V
q
0.1
0.5
%
Measured in Servo Loop,
I
TH
Voltage: 1.2V to 2V
q
0.1
0.5
%
V
REFLNREG
Reference Voltage Line Regulation
V
IN
= 3.6V to 30V (Note 4)
0.002
0.02
%/V
V
OVL
Output Overvoltage Threshold
Measured at V
EAIN
q
0.84
0.86
0.88
V
UVLO
Undervoltage Lockout
V
IN
Ramping Down
3
3.5
4
V
g
m
Transconductance Amplifier g
m
I
TH
= 1.2V, Sink/Source 5
A (Note 4)
3
mmho
g
mOL
Transconductance Amplifier Gain
I
TH
= 1.2V, (g
m
xZ
L
; No Ext Load) (Note 4)
1.5
V/mV
I
Q
Input DC Supply Current
(Note 5)
Normal Mode
EXTV
CC
Tied to V
OUT
, V
OUT
= 5V
470
A
Shutdown
V
RUN/SS
= 0V
20
40
A
I
RUN/SS
Soft-Start Charge Current
V
RUN/SS
= 1.9V
0.5
1.2
A
V
RUN/SS
RUN/SS Pin ON Arming
V
RUN/SS
Rising
1.0
1.5
1.9
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RUNN/SS
SENSE1
+
SENSE1
EAIN
PLLFLTR
PLLIN
NC
I
TH
SGND
V
DIFFOUT
V
OS
V
OS
+
SENSE2
SENSE2
+
ATTENOUT
ATTENIN
VID0
VID1
NC
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
PGOOD
V
BIAS
VID4
VID3
VID2
3
LTC1709-8/LTC1709-9
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 15V, V
BIAS
= 5V, V
RUN/SS
= 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
RUN/SSLO
RUN/SS Pin Latchoff Arming
V
RUN/SS
Rising from 3V
4.1
4.5
V
I
SCL
RUN/SS Discharge Current
Soft Short Condition V
EAIN
= 0.5V, V
RUN/SS
= 4.5V
0.5
2
4
A
I
SDLHO
Shutdown Latch Disable Current
V
EAIN
= 0.5V
1.6
5
A
I
SENSE
Total Sense Pins Source Current
Each Channel: V
SENSE1
, 2
= V
SENSE1
+
, 2
+ = 0V
85
60
A
DF
MAX
Maximum Duty Factor
In Dropout
98
99.5
%
Top Gate Transition Time:
(Note 6)
TG1, 2 t
r
Rise Time
C
LOAD
= 3300pF
30
90
ns
TG1, 2 t
f
Fall Time
C
LOAD
= 3300pF
40
90
ns
Bottom Gate Transition Time:
(Note 6)
BG1, 2 t
r
Rise Time
C
LOAD
= 3300pF
30
90
ns
BG1, 2 t
f
Fall Time
C
LOAD
= 3300pF
20
90
ns
TG/BG t
1D
Top Gate Off to Bottom Gate On Delay
C
LOAD
= 3300pF Each Driver (Note 6)
90
ns
Synchronous Switch-On Delay Time
BG/TG t
2D
Bottom Gate Off to Top Gate On Delay
C
LOAD
= 3300pF Each Driver (Note 6)
90
ns
Top Switch-On Delay Time
t
ON(MIN)
Minimum On-Time
Tested with a Square Wave (Note 7)
180
ns
Internal V
CC
Regulator
V
INTVCC
Internal V
CC
Voltage
6V < V
IN
< 30V, V
EXTVCC
= 4V
4.8
5.0
5.2
V
V
LDO
INT
INTV
CC
Load Regulation
I
CC
= 0 to 20mA, V
EXTVCC
= 4V
0.2
1.0
%
V
LDO
EXT
EXTV
CC
Voltage Drop
I
CC
= 20mA, V
EXTVCC
= 5V
80
160
mV
V
EXTVCC
EXTV
CC
Switchover Voltage
I
CC
= 20mA, EXTV
CC
Ramping Positive
q
4.5
4.7
V
V
LDOHYS
EXTV
CC
Switchover Hysteresis
I
CC
= 20mA, EXTV
CC
Ramping Negative
0.2
V
VID Parameters
V
BIAS
Operating Supply Voltage Range
2.7
5.5
V
R
ATTEN
Resistance Between ATTENIN
LTC1709-8
20
k
and ATTENOUT Pins
LTC1709-9
10
k
ATTEN
ERR
Resistive Divider Error
LTC1709-8: VID4 = 0; LTC1709-9
q
0.25
0.25
%
LTC1709-8: VID4 = 1
q
0.35
0.35
%
R
PULLUP
VID0VID4 Pull-Up Resistance
(Note 8)
40
k
VID
THLOW
VID0VID4 Logic Threshold Low
0.4
V
VID
THHIGH
VID0VID4 Logic Threshold High
1.6
V
VID
LEAK
VID0VID4 Leakage
V
BIAS
< VID0VID4 < 7V
1
A
Oscillator and Phase-Locked Loop
f
NOM
Nominal Frequency
V
PLLFLTR
= 1.2V
190
220
250
kHz
f
LOW
Lowest Frequency
V
PLLFLTR
= 0V
120
140
160
kHz
f
HIGH
Highest Frequency
V
PLLFLTR
2.4V
280
320
360
kHz
R
PLLIN
PLLIN
Input Resistance
50
k
I
PLLFLTR
Phase Detector Output Current
Sinking Capability
f
PLLIN
< f
OSC
15
A
Sourcing Capability
f
PLLIN
> f
OSC
15
A
R
RELPHS
Controller 2-Controller 1 Phase
180
Deg
4
LTC1709-8/LTC1709-9
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 15V, V
RUN/SS
= 5V unless otherwise noted.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current
40% I
MAX
(see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Each built-in pull-up resistor attached to the VID inputs also has a
series diode to allow input voltages higher than the VIDV
CC
supply without
damage or clamping (see the Applications Information section).
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: The LTC1709EG is guaranteed to meet performance specifications
from 0
C to 70
C. Specifications over the 40
C to 85
C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC1709EG: T
J
= T
A
+ (P
D
85
C/W)
Note 4: The LTC1709-8/LTC1709-9 are tested in a feedback loop that
servos V
ITH
to a specified voltage and measures the resultant V
EAIN
.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Efficiency vs Output Current
(Figure 12)
OUTPUT CURRENT (A)
0.1
EFFICIENCY (%)
100
80
60
40
20
0
170989 G01
1
10
100
V
OUT
= 2V
V
EXTVCC
= 0V
FREQ = 200kHz
V
IN
= 5V
V
IN
= 8V
V
IN
= 12V
V
IN
= 20V
Efficiency vs Output Current
(Figure 12)
V
IN
(V)
5
EFFICIENCY (%)
100
90
80
70
170989 G03
10
15
20
V
OUT
= 3.3V
V
EXTVCC
= 5V
I
OUT
= 20A
Efficiency vs Output Current
(Figure 12)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGOOD Output
V
PGL
PGOOD Voltage Low
I
PGOOD
= 2mA
0.1
0.3
V
I
PGOOD
PGOOD Leakage Current
V
PGOOD
= 5V
1
A
V
PG
PGOOD Trip Level, Either Controller
V
EAIN
with Respect to Set Output Voltage
V
EAIN
Ramping Negative
6
7.5
9.5
%
V
EAIN
Ramping Positive
6
7.5
9.5
%
Differential Amplifier/Op Amp Gain Block
A
DA
Gain
0.995
1
1.005
V/V
CMRR
DA
Common Mode Rejection Ratio
0V < V
CM
< 5V
46
55
dB
R
IN
Input Resistance
Measured at V
OS
+ Input
80
k
OUTPUT CURRENT (A)
0.1
EFFICIENCY (%)
40
60
170989 G02
20
0
10
1
100
100
80
V
IN
= 12V
V
OUT
= 2V
FREQ = 200kHz
V
EXTVCC
= 5V
V
EXTVCC
= 0V
5
LTC1709-8/LTC1709-9
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Supply Current vs Input Voltage
and Mode (Figure 12)
EXTV
CC
Voltage Drop
INTV
CC
and EXTV
CC
Switch
Voltage vs Temperature
INPUT VOLTAGE (V)
0
5
0
SUPPLY CURRENT (
A)
400
1000
10
20
25
170989 G04
200
800
600
15
30
35
ON
SHUTDOWN
CURRENT (mA)
0
EXTV
CC
VOLTAGE DROP (mV)
150
200
250
40
170989 G05
100
50
0
10
20
30
50
TEMPERATURE (
C)
50
INTV
CC
AND EXTV
CC
SWITCH VOLTAGE (V)
4.95
5.00
5.05
25
75
170989 G06
4.90
4.85
25
0
50
100
125
4.80
4.70
4.75
INTV
CC
VOLTAGE
EXTV
CC
SWITCHOVER THRESHOLD
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Internal 5V LDO Line Reg
Maximum Current Sense Threshold
vs Duty Factor
INPUT VOLTAGE (V)
0
4.8
4.9
5.1
15
25
170989 G07
4.7
4.6
5
10
20
30
35
4.5
4.4
5.0
INTV
CC
VOLTAGE (V)
I
LOAD
= 1mA
DUTY FACTOR (%)
0
0
V
SENSE
(mV)
25
50
75
20
40
60
80
170989 G08
100
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
0
V
SENSE
(mV)
40
50
60
100
170989 G09
30
20
0
25
50
75
10
80
70
Maximum Current Sense Threshold
vs V
RUN/SS
(Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Current Sense Threshold
vs I
TH
Voltage
V
RUN/SS
(V)
0
0
V
SENSE
(mV)
20
40
60
80
1
2
3
4
170989 G10
5
6
V
SENSE(CM)
= 1.6V
COMMON MODE VOLTAGE (V)
0
V
SENSE
(mV)
72
76
80
4
170989 G11
68
64
60
1
2
3
5
V
ITH
(V)
0
V
SENSE
(mV)
30
50
70
90
2
170989 G12
10
10
20
40
60
80
0
20
30
0.5
1
1.5
2.5
6
LTC1709-8/LTC1709-9
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Load Regulation
V
ITH
vs V
RUN/SS
SENSE Pins Total Source Current
LOAD CURRENT (A)
0
NORMALIZED V
OUT
(%)
0.2
0.1
4
1629 G13
0.3
0.4
1
2
3
5
0.0
FCB = 0V
V
IN
= 15V
FIGURE 1
V
RUN/SS
(V)
0
0
V
ITH
(V)
0.5
1.0
1.5
2.0
2.5
1
2
3
4
1629 G14
5
6
V
OSENSE
= 0.7V
V
SENSE
COMMON MODE VOLTAGE (V)
0
I
SENSE
(
A)
0
1629 G15
50
100
2
4
50
100
6
Maximum Current Sense
Threshold vs Temperature
TEMPERATURE (
C)
50
25
70
V
SENSE
(mV)
74
80
0
50
75
170989 G16
72
78
76
25
100
125
RUN/SS Current vs Temperature
TEMPERATURE (
C)
50
25
0
RUN/SS CURRENT (
A)
0.2
0.6
0.8
1.0
75
100
50
1.8
170989 G17
0.4
0
25
125
1.2
1.4
1.6
Soft-Start (Figure 12)
Load Step (Figure 12)
V
ITH
1V/DIV
V
OUT
2V/DIV
V
RUN/SS
2V/DIV
100ms/DIV
170989 G18
I
OUT
0/20A
V
OUT
50mV/DIV
20
s/DIV
170989 G19
7
LTC1709-8/LTC1709-9
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Current Sense Pin Input Current
vs Temperature
EXTV
CC
Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (
C)
50
25
25
CURRENT SENSE INPUT CURRENT (
A)
29
35
0
50
75
170989 G20
27
33
31
25
100
125
V
OUT
= 5V
TEMPERATURE (
C)
50
25
0
EXTV
CC
SWITCH RESISTANCE (
)
4
10
0
50
75
170989 G21
2
8
6
25
100
125
TEMPERATURE (
C)
50
200
250
350
25
75
170989 G22
150
100
25
0
50
100
125
50
0
300
FREQUENCY (kHz)
V
FREQSET
= 5V
V
FREQSET
= OPEN
V
FREQSET
= 0V
Undervoltage Lockout
vs Temperature
TEMPERATURE (
C)
50
UNDERVOLTAGE LOCKOUT (V)
3.40
3.45
3.50
25
75
170989 G23
3.35
3.30
25
0
50
100
125
3.25
3.20
Shutdown Latch Thresholds
vs Temperature
TEMPERATURE (
C)
50
25
0
SHUTDOWN LATCH THRESHOLDS (V) 0.5
1.5
2.0
2.5
75
100
50
4.5
170989 G24
1.0
0
25
125
3.0
3.5
4.0
LATCH ARMING
LATCHOFF
THRESHOLD
RUN/SS (Pin 1): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
ground at this pin sets the ramp time to full current output.
Forcing this pin below 0.8V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.
SENSE1
+
, SENSE2
+
(Pins 2,14): The (+) Input to Each
Differential Current Comparator. The I
TH
pin voltage and
built-in offsets between SENSE
and SENSE
+
pins in
conjunction with R
SENSE
set the current trip threshold.
PI FU CTIO S
U
U
U
SENSE1
, SENSE2
(Pins 3, 13): The () Input to the
Differential Current Comparators.
EAIN (Pin 4): Input to the error amplifier that compares the
feedback voltage to the internal 0.8V reference voltage.
This pin is normally connected to a resistive divider from
the output of the differential amplifier (DIFFOUT).
PLLFLTR (Pin 5): The phase-locked loop's lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator.
8
LTC1709-8/LTC1709-9
PI FU CTIO S
U
U
U
TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top
N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTV
CC
superim-
posed on the switch node voltage SW.
SW2, SW1 (Pins 25, 34): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V
IN
.
BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies
to the Topside Floating Drivers. External capacitors are
connected between the BOOST and SW pins, and Schottky
diodes are connected between the BOOST and INTV
CC
pins.
BG2, BG1 (Pins 27, 31): High Current Gate Drives for
Bottom N-Channel MOSFETS. Voltage swing at these pins
is from ground to INTV
CC
.
PGND (Pin 28): Driver Power Ground. Connect to sources
of bottom N-channel MOSFETS and the () terminals of
C
IN
.
INTV
CC
(Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTV
CC
Switch. The driver and
control circuits are powered from this voltage source.
Decouple to power ground with a 1
F ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7
F
additional tantalum or other low ESR capacitor.
EXTV
CC
(Pin 30): External Power Input to an Internal
Switch. This switch closes and supplies INTV
CC,
bypass-
ing the internal
low dropout regulator whenever EXTV
CC
is
higher than 4.7V. See EXTV
CC
Connection in the Applica-
tions Information section. Do not exceed 7V on this pin
and ensure V
EXTVCC
V
IN
.
V
IN
(Pin 32): Main Supply Pin. Should be closely decoupled
to the IC's signal ground pin.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50k
. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
NC (Pins 7, 36): Do not connect.
I
TH
(Pin 8): Error Amplifier Output and Switching Regula-
tor Compensation Point. Both current comparator's thresh-
olds increase with this control voltage. The normal voltage
range of this pin is from 0V to 2.4V
SGND (Pin 9): Signal Ground. This pin is common to both
controllers. Route separately to the PGND pin.
V
DIFFOUT
(Pin 10): Output of a Differential Amplifier. This
pin provides true remote output voltage sensing. V
DIFFOUT
normally drives an external resistive divider that sets the
output voltage.
V
OS
, V
OS
+
(Pins 11, 12): Inputs to an Operational Ampli-
fier. Internal precision resistors capable of being elec-
tronically switched in or out can configure it as a differential
amplifier or an uncommitted op amp.
ATTENOUT (Pin 15): Voltage Feedback Signal Resistively
Divided According to the VID Programming Code.
ATTENIN (Pin 16): The Input to the VID Controlled Resis-
tive Divider.
VID0VID4 (Pins 17,18, 19, 20, 21): VID Control Logic
Input Pins.
V
BIAS
(Pin 22): Supply Pin for the VID Control Circuit.
PGOOD (Pin 23): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the EAIN pin is not
within
7.5% of its set point.
9
LTC1709-8/LTC1709-9
FU CTIO AL DIAGRA
U
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SWITCH
LOGIC
0.80V
4.7V
5V
V
IN
V
IN
CLK2
CLK1
+
+
V
REF
INTERNAL
SUPPLY
EXTV
CC
INTV
CC
SGND
+
5V
LDO
REG
SW
SHDN
TOP
BOOST
TG
C
B
C
IN
D
B
PGND
BOT
BG
INTV
CC
INTV
CC
V
IN
+
V
OUT
170989 FBD
EAIN
DROP
OUT
DET
RUN
SOFT
START
BOT
FORCE BOT
S
R
Q
Q
OSCILLATOR
PLLLPF
50k
EA
0.86V
0.80V
OV
1.2
A
6V
+
R
C
4(V
FB
)
RST
SHDN
RUN/SS
I
TH
C
C
C
SS
4(V
FB
)
0.86V
SLOPE
COMP
+
SENSE
SENSE
+
INTV
CC
30k
45k
2.4V
45k
30k
I
1
ATTENIN
20k (LTC1709-8)
10k (LTC1709-9)
R1
VID0
ATTENOUT
VID1
VID2
VID3
VID4
TYPICAL ALL
VID PINS
40k
V
BIAS
PHASE DET
PLLIN
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
+
R
SENSE
L
C
OUT
+
f
IN
R
LP
C
LP
A1
+
DIFFOUT
V
OS
+
V
OS
0.74V
0.86V
+
+
EAIN
PGOOD
5-BIT VID DECODER
10
LTC1709-8/LTC1709-9
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC1709 uses a constant frequency, current mode
step-down architecture with inherent current sharing.
During normal operation, the top MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the main current comparator, I
1
, resets
the RS latch. The peak inductor current at which I
1
resets
the RS latch is controlled by the voltage on the I
TH
pin,
which is the output of the error amplifier EA. The differen-
tial amplifier, A1, produces a signal equal to the differen-
tial voltage sensed across the output capacitor but
re-references it to the internal signal ground (SGND)
reference. The EAIN pin receives a portion of this voltage
feedback signal at the DIFFOUT as determined by VID
logic input pins (VID0 to VID4) and is compared to the
internal reference voltage by the EA. When the load
current increases, it causes a slight decrease in the EAIN
pin voltage
relative to the 0.8V reference, which in turn
causes the I
TH
voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on for the rest of the period.
The top MOSFET drivers are biased from floating boot-
strap capacitor C
B
, which normally is recharged during
each off cycle through an external Schottky diode. When
V
IN
decreases to a voltage close to V
OUT
, however, the loop
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor, C
B
.
The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2
A
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with
the I
TH
voltage clamped at approximately 30% of its
maximum value. As C
SS
continues to charge, I
TH
is
gradually released allowing normal operation to resume.
When the RUN/SS pin is low, all LTC1709 functions are
shut down. If V
OUT
has not reached 70% of its nominal
value when C
SS
has charged to 4.1V, an overcurrent
latchoff can be invoked as described in the Applications
Information section.
Low Current Operation
The LTC1709 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizes transient response at the expense of substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage and fre-
quency of operation.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 140kHz to 310kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.
Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by two and
power loss is proportional to the RMS current squared. A
two stage, single output voltage implementation can
reduce input path power loss by 75% and radically reduce
the required RMS current rating of the input capacitor(s).
INTV
CC
/EXTV
CC
Power
Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTV
CC
. When the
EXTV
CC
pin is left open, an internal 5V low dropout
regulator supplies INTV
CC
power. If the EXTV
CC
pin is
taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTV
CC
to INTV
CC
.
This allows the INTV
CC
power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTV
CC
to INTV
CC
in applications requiring greater than
the specified INTV
CC
current.
Voltages up to 7V can be
applied to EXTV
CC
for additional gate drive capability.
11
LTC1709-8/LTC1709-9
OPERATIO
U
(Refer to Functional Diagram)
Differential Amplifier
This amplifier provides true differential output voltage
sensing. Sensing both V
OUT
+
and V
OUT
benefits regula-
tion in high current applications and/or applications hav-
ing electrical interconnection losses. The AMPMD pin
allows selection of internal, precision feedback resistors
for high common mode rejection differencing applica-
tions, or direct access to the actual amplifier inputs
without these internal feedback resistors for other applica-
tions. The AMPMD pin is grounded to connect the internal
precision resistors in a unity-gain differencing application,
or tied to the INTV
CC
pin to bypass the internal resistors
and make the amplifier inputs directly available. The
amplifier is a unity-gain stable, 2MHz gain bandwidth,
>120dB open-loop gain design. The amplifier has an
output slew rate of 5V/
s and is capable of driving capaci-
tive loads with an output RMS current typically up to
35mA. The amplifier is not capable of sinking current and
therefore must be resistively loaded to do so.
Power Good (PGOOD)
The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET turns on when the output voltage
is not within
7.5% of its nominal output level as deter-
mined by the feedback divider. When the output is within
7.5% of its nominal value, the MOSFET is turned off
within 10
s and the PGOOD pin should be pulled up by an
external resistor to a source of up to 7V.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the controllers
have been given time, as determined by the capacitor on
the RUN/SS pin, to charge up the output capacitors and
provide full-load current, the RUN/SS capacitor is then
used as a short-circuit timeout circuit. If the output voltage
falls to less than 70% of its nominal output voltage the
RUN/SS capacitor begins discharging assuming that the
output is in a severe overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the RUN/SS capacitor, the
controller will be shut down until the RUN/SS pin voltage
is recycled. This built-in latchoff can be overidden by
providing a current >5
A at a compliance of 5V to the
RUN/SS pin. This current shortens the soft-start period
but also prevents net discharge of the RUN/SS capacitor
during a severe overcurrent and/or short-circuit condi-
tion. Foldback current limiting is activated when the output
voltage falls below 70% of its nominal level whether or not
the short-circuit latchoff circuit is enabled.
APPLICATIO S I FOR ATIO
W
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The basic LTC1709 application circuit is shown in Fig-
ure 1 on the first page. External component selection
begins with the selection of the inductor(s) based on
ripple current requirements and continues with the
R
SENSE1, 2
resistor selection using the calculated peak
inductor current and/or maximum current limit. Next, the
power MOSFETs and D1 and D2 are selected. The oper-
ating frequency and the inductor are chosen based mainly
on the amount of ripple current. Finally, C
IN
is selected for
its ability to handle the input ripple current (that
PolyPhase
TM
operation minimizes) and C
OUT
is chosen
with low enough ESR to meet the output ripple voltage
and load step specifications (also minimized with
PolyPhase). Current mode architecture provides inherent
current sharing between output stages. The circuit shown
in Figure 1 can be configured for operation up to an input
voltage of 28V (limited by the external MOSFETs).
R
SENSE
Selection For Output Current
R
SENSE1, 2
are chosen based on the required peak output
current. The LTC1709 current comparator has a maxi-
mum threshold of 75mV/R
SENSE
and an input common
mode range of SGND to 1.1(INTV
CC
). The current com-
parator threshold sets the peak inductor current, yielding
a maximum average output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current,
I
L
.
PolyPhase is a trademark of Linear Technology Corporation.
12
LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
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Allowing a margin for variations in the LTC1709 and
external component values yields:
R
SENSE
= 2(50mV/I
MAX
)
Operating Frequency
The LTC1709 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current
plus an additional current which is proportional to the
voltage applied to the PLLFLTR pin. Refer to Phase-
Locked Loop and Frequency Synchronization for addi-
tional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
effect of inductor value on ripple current and low current
operation must also be considered. The PolyPhase ap-
proach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current
I
L
per individual section, N,
decreases with higher inductance or frequency and
increases with higher V
IN
or V
OUT
:
I
V
fL
V
V
L
OUT
OUT
IN
=
-
1
where f is the individual output stage operating frequency.
In a 2-phase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for the 1- and 2- phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations, simplifying the
design process.
Figure 2. Operating Frequency vs V
PLLFLTR
OPERATING FREQUENCY (kHz)
120
170
220
270
320
PLLFLTR PIN VOLTAGE (V)
1709 F02
2.5
2.0
1.5
1.0
0.5
0
Figure 3. Normalized Output Ripple Current
vs Duty Factor [I
RMS
0.3 (
I
O(PP)
)]
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase di-
rectly with frequency. In addition to this basic tradeoff, the
DUTY FACTOR (V
OUT
/V
IN
)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1709 F03
2-PHASE
1-PHASE
I
O(P-P)
V
O
/fL
13
LTC1709-8/LTC1709-9
Accepting larger values of
I
L
allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
I
L
= 0.4(I
OUT
)/2, where I
OUT
is the total load current. Remem-
ber, the maximum
I
L
occurs at the maximum input
voltage. The individual inductor ripple currents are deter-
mined by the inductor, input and output voltages.
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool M
cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple.
Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool M
. Toroids are very space effi-
cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
controller with the LTC1709: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage. This voltage is typically 5V during start-up
(see EXTV
CC
Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V
IN
< 5V); then, sublogic-level threshold MOSFETs
(V
GS(TH)
< 1V) should be used. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the "ON"
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC1709 is operating in continuous mode the duty factors
for the top and bottom MOSFETs of each output stage are
given by:
Main Switch Duty Cycle
V
V
OUT
IN
=
Synchronous Switch Duty Cycle
V
V
V
IN
OUT
IN
=
The MOSFET power dissipations at maximum output
current are given by:
P
V
V
I
R
k V
I
C
f
MAIN
OUT
IN
MAX
DS ON
IN
MAX
RSS
=
+
( )
+
( )
( )( )
2
1
2
2
2
(
)
P
V
V
V
I
R
SYNC
IN
OUT
IN
MAX
DS ON
=
+
( )
(
)
2
1
2
where
is the temperature dependency of R
DS(ON)
and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
RSS
actual provides higher efficiency. The
APPLICATIO S I FOR ATIO
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Kool M
is a registered trademark of Magnetics, Inc.
14
LTC1709-8/LTC1709-9
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 +
) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
= 0.005/
C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
The Schottky diodes, D1 and D2 shown in Figure 1
conduct during the dead-time between the conduction of
the two large power MOSFETs. This helps prevent the
body diode of the bottom MOSFET from turning on,
storing charge during the dead-time, and requiring a
reverse recovery period which would reduce efficiency. A
1A to 3A Schottky (depending on output current) diode is
generally a good compromise for both regions of opera-
tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the input voltage is twice the
output voltage
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
V
V
k
OUT
IN
=
-
2
1
4
where k = 1, 2
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer's ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.
It is important to note that the efficiency loss is propor-
tional to the input RMS current
squared and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the
reduction of the input ripple current in a 2-phase system.
The required amount of input capacitance is further
reduced by the factor, 2, due to the effective increase in
the frequency of the current pulses.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (
V
OUT
) is determined by:
V
I
ESR
fC
OUT
RIPPLE
OUT
+
1
16
APPLICATIO S I FOR ATIO
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Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
DUTY FACTOR (V
OUT
/V
IN
)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
170989 F04
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
2-PHASE
1-PHASE
15
LTC1709-8/LTC1709-9
Where f = operating frequency of each stage, C
OUT
=
output capacitance and
I
RIPPLE
= combined inductor
ripple currents.
The output ripple varies with input voltage since
I
L
is a
function of input voltage. The output ripple will be less than
50mV at max V
IN
with
I
L
= 0.4I
OUT(MAX)
/2 assuming:
C
OUT
required ESR < 4(R
SENSE
) and
C
OUT
> 1/(16f)(R
SENSE
)
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally com-
pensate the switching regulator loop using the I
TH
pin(OPTI-LOOP compensation) allows a much wider se-
lection of output capacitor types. OPTI-LOOP compensa-
tion effectively removes constraints on output capacitor
ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo and the Panasonic
SP surface mount types have the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON type capacitors is recommended to reduce
the inductance effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur-
face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D
series. Consult the manufacturer for other specific recom-
mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.
INTV
CC
Regulator
An internal P-channel low dropout regulator produces 5V
at the INTV
CC
pin from the V
IN
supply pin. The INTV
CC
regulator powers the drivers and internal circuitry of the
LTC1709. The INTV
CC
pin regulator can supply up to 50mA
peak and must be bypassed to power ground with a
minimum of 4.7
F tantalum or electrolytic capacitor. An
additional 1
F ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta-
neous currents required by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1709 to be
exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTV
CC
pin. When the voltage applied to the EXTV
CC
pin
is less than 4.7V, all of the INTV
CC
load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (I
IN
)(V
IN
INTV
CC
) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC1709 V
IN
current is limited to less than 24mA from a 24V supply:
T
J
= 70
C + (24mA)(24V)(85
C/W) = 119
C
Use of the EXTV
CC
pin reduces the junction temperature
to:
T
J
= 70
C + (24mA)(5V)(85
C/W) = 80.2
C
The input supply current should be measured while the
controller is operating in continuous mode at maximum
V
IN
and the power dissipation calculated in order to
prevent the maximum junction temperature from being
exceeded.
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16
LTC1709-8/LTC1709-9
Figure 5a. Secondary Output Loop with EXTV
CC
Connection
Figure 5b. Capacitive Charge Pump for EXTV
CC
EXTV
CC
Connection
The LTC1709 contains an internal P-channel MOSFET
switch connected between the EXTV
CC
and INTV
CC
pins.
When the voltage applied to EXTV
CC
rises above
4.7V, the
internal regulator is turned off and an internal switch
closes, connecting the EXTV
CC
pin to the INTV
CC
pin
thereby supplying internal and MOSFET gate driving power
to the IC. The switch remains closed as long as the voltage
applied to EXTV
CC
remains above 4.5V. This allows the
MOSFET driver and control power to be derived from the
output during normal operation (4.7V < V
EXTVCC
< 7V) and
from the internal regulator when the output is out of
regulation (start-up, short-circuit). Do not apply greater
than 7V to the EXTV
CC
pin and ensure that EXTV
CC
< V
IN
+
0.3V when using the application circuits shown.
If an
external voltage source is applied to the EXTV
CC
pin when
the V
IN
supply is not present, a diode can be placed in
series with the LTC1709's V
IN
pin and a Schottky diode
between the EXTV
CC
and the V
IN
pin, to prevent current
from backfeeding V
IN
.
Significant efficiency gains can be realized by powering
INTV
CC
from the output, since the V
IN
current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTV
CC
pin directly to V
OUT
. How-
ever, for 3.3V and other lower voltage regulators, addi-
tional circuitry is required to derive INTV
CC
power from the
output.
The following list summarizes the four possible connec-
tions for EXTV
CC:
1. EXTV
CC
left open (or grounded). This will cause INTV
CC
to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.
2. EXTV
CC
connected directly to V
OUT
. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTV
CC
connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTV
CC
providing it is compatible with the MOSFET
gate drive requirements.
4. EXTV
CC
connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTV
CC
to an output-
derived voltage which has been boosted to greater than
4.7V but less than 7V. This can be done with either the
inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.
Topside MOSFET Driver Supply (C
B
,D
B
) (Refer to
Functional Diagram)
External bootstrap capacitors C
B1
and C
B2
connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor C
B
in the
Functional Diagram is charged though diode D
B
from
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1709 F05a
V
IN
TG1
N-CH
1N4148
N-CH
BG1
PGND
LTC1709
SW1
EXTV
CC
OPTIONAL EXTV
CC
CONNECTION
5V < V
SEC
< 7V
T1
R
SENSE
V
SEC
V
OUT
V
IN
+
C
IN
+
1
F
+
C
OUT
1709 F05b
V
IN
TG1
N-CH
N-CH
BG1
PGND
LTC1709
SW1
EXTV
CC
L1
R
SENSE
BAT85
BAT85
BAT85
0.22
F
V
OUT
V
IN
+
C
IN
+
+
C
OUT
VN2222LL
17
LTC1709-8/LTC1709-9
INTV
CC
when the SW pin is low. When the topside MOSFET
turns on, the driver places the C
B
voltage across the gate-
source of the desired MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage,
SW, rises to V
IN
and the BOOST pin rises to V
IN
+ V
INTVCC
.
The value of the boost capacitor C
B
needs to be 30 to 100
times that of the total input capacitance of the topside
MOSFET(s). The reverse breakdown of D
B
must be greater
than V
IN(MAX).
The final arbiter when defining the best gate drive ampli-
tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.
Output Voltage
The LTC1709 has a true remote voltage sense capablity.
The sensing connections should be returned from the load
back to the differential amplifier's inputs through a com-
mon, tightly coupled pair of PC traces. The differential
amplifier corrects for DC drops in both the power and
ground paths. The differential amplifier output signal is
divided down and compared with the internal precision
0.8V voltage reference by the error amplifier.
Output Voltage Programming
The output voltage is digitally programmed as defined in
Table 1 using the VID0 to VID4 logic input pins. The VID
logic inputs program a precision, 0.25% internal feedback
resistive divider. The LTC1709-8 has an output voltage
range of 1.30V to 3.5V in 50mV and 100mV steps. The
LTC1709-9 has an output voltage range of 1.10V to 1.85V
in 25mV steps.
Between the ATTENOUT
pin and ground is a variable
resistor, R1, whose value is controlled by the five VID input
pins (VID0 to VID4). Another resistor, R2, between the
ATTENIN and the ATTENOUT pins completes the resistive
divider. The output voltage is thus set by the ratio of
(R1 + R2) to R1.
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Table 1. VID Output Voltage Programming
LTC1709-8
LTC1709-9
VID4
VID3
VID2
VID1
VID0
VRM8.4
VRM9.0
0
0
0
0
0
2.05V
1.850V
0
0
0
0
1
2.00V
1.825V
0
0
0
1
0
1.95V
1.800V
0
0
0
1
1
1.90V
1.775V
0
0
1
0
0
1.85V
1.750V
0
0
1
0
1
1.80V
1.725V
0
0
1
1
0
1.75V
1.700V
0
0
1
1
1
1.70V
1.675V
0
1
0
0
0
1.65V
1.650V
0
1
0
0
1
1.60V
1.625V
0
1
0
1
0
1.55V
1.600V
0
1
0
1
1
1.50V
1.575V
0
1
1
0
0
1.45V
1.550V
0
1
1
0
1
1.40V
1.525V
0
1
1
1
0
1.35V
1.500V
0
1
1
1
1
1.30V
1.475V
1
0
0
0
0
3.50V
1.450V
1
0
0
0
1
3.40V
1.425V
1
0
0
1
0
3.30V
1.400V
1
0
0
1
1
3.20V
1.375V
1
0
1
0
0
3.10V
1.350V
1
0
1
0
1
3.00V
1.325V
1
0
1
1
0
2.90V
1.300V
1
0
1
1
1
2.80V
1.275V
1
1
0
0
0
2.70V
1.250V
1
1
0
0
1
2.60V
1.225V
1
1
0
1
0
2.50V
1.200V
1
1
0
1
1
2.40V
1.175V
1
1
1
0
0
2.30V
1.150V
1
1
1
0
1
2.20V
1.125V
1
1
1
1
0
2.10V
1.100V
1
1
1
1
1
No_CPU/
No_CPU/
Shutdown*
Shutdown*
*Represents codes without a defined output voltage as specified in Intel
specifications. The LTC1709 interprets these codes as a valid input and
produces an output voltage as follows:
LTC1709-8 (11111) = 2V
LTC1709-9 (11111) = 1.075V
18
LTC1709-8/LTC1709-9
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Figure 6. RUN/SS Pin Interfacing
The time for the output current to ramp up is then:
t
V
V
A
C
s F C
IRAMP
SS
SS
=
-
=
(
)
3
1 5
1 2
1 25
.
.
.
/
By pulling the RUN/SS pin below 0.8V the LTC1709 is put
into low current shutdown (I
Q
< 40
A). The RUN/SS pins
can be driven directly from logic as shown in Figure 6.
Diode D1 in Figure 6 reduces the start delay but allows
C
SS
to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
3.3V OR 5V
RUN/SS
V
IN
INTV
CC
RUN/SS
D1
D1*
C
SS
R
SS
*
C
SS
R
SS
*
170989 F06
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, C
SS
, is used initially to limit the inrush
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value after C
SS
reaches 4.1V, C
SS
begins discharging on the assumption
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of the C
SS
, the controller will be shut down until the
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:
t
LO1
(C
SS
0.6V)/(1.2
A) = 5 10
5
(C
SS
)
Each VID digital input is pulled up by a 40k resistor in
series with a diode from V
BIAS
. Therefore, it must be
grounded to get a digital low input, and can be either
floated or connected to V
BIAS
to get a digital high input. The
series diode is used to prevent the digital inputs from
being damaged or clamped if they are driven higher than
V
BIAS
. The digital inputs accept CMOS voltage levels.
V
BIAS
is the supply voltage for the VID section. It is
normally connected to INTV
CC
but can be driven from
other sources. If it is driven from another source, that
source
must be in the range of 2.7V to 5.5V and must be
alive prior to enabling the LTC1709.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) Run/Shut-
down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources' surge
currents by gradually increasing the controller's current
limit I
TH(MAX)
. The latchoff timer prevents very short,
extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5
A) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.
An internal 1.2
A current source charges up the soft-start
capacitor, C
SS
.
When the voltage on RUN/SS reaches
1.5V, the controller is permitted to start operating. As the
voltage on RUN/SS increases from 1.5V to 3.0V, the
internal current limit is increased from 25mV/R
SENSE
to
75mV/R
SENSE
. The output current limit ramps up slowly,
taking an additional 1.4s/
F to reach full current. The
output current thus ramps up slowly, reducing the starting
surge current required from the input power supply. If
RUN/SS has been pulled all the way to ground there is a
delay before starting of approximately:
t
V
A
C
s F C
DELAY
SS
SS
=
=
(
)
1 5
1 2
1 25
.
.
.
/
19
LTC1709-8/LTC1709-9
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC1709 is 140kHz to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range,
f
H
, is equal to the capture range,
f
C:
f
H
=
f
C
=
0.5 f
O
(150kHz-300kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
0SC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f
0SC
, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C
LP
holds the voltage. The
LTC1709 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin.
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If the overload occurs after start-up, the voltage on C
SS
will
continue charging and will provide additional time before
latching off:
t
LO2
(C
SS
3V)/(1.2
A) = 2.5 10
6
(C
SS
)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R
SS
, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit con-
dition. When deriving the 5
A current from V
IN
as in the
figure, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTV
CC
, as in Figure 6,
eliminates any extra supply current during shutdown
while eliminating the INTV
CC
loading from preventing
controller start-up.
Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
The value of the soft-start capacitor C
SS
may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
)(10
-4
)(R
SENSE
)
The minimum recommended soft-start capacitor of C
SS
=
0.1
F will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC1709 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is
50% around the
center frequency f
O
. A voltage applied to the PLLFLTR pin
Figure 7. Phase-Locked Loop Block Diagram
EXTERNAL
OSC
2.4V
R
LP
10k
C
LP
OSC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PHASE
DETECTOR
PLLIN
1709 F07
PLLFLTR
50k
20
LTC1709-8/LTC1709-9
The loop filter components (C
LP
, R
LP
) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
=10k and C
LP
is 0.01
F to
0.1
F.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC1709 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
t
V
V
f
ON MIN
OUT
IN
( )
<
( )
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1709 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC1709 is generally less
than 200ns. However, as the peak sense voltage de-
creases, the minimum on-time gradually increases. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement.
As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
OUT(MAX)
at V
IN(MAX)
.
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursion under worst-case transient load-
ing conditions. The open-loop DC gain of the control loop
is reduced depending upon the maximum load step speci-
fications. Voltage positioning can easily be added to the
LTC1709 by loading the I
TH
pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can be
reduced for a particular application. A complete explana-
tion is included in Design Solutions 10 or the LTC1736
data sheet. (See www.linear-tech.com)
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I
TH
R
C
R
T1
INTV
CC
C
C
1709 F08
LTC1709
R
T2
Figure 8. Active Voltage Positioning Applied to the LTC1709
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1709 circuits: 1) I
2
R losses, 2) Topside
MOSFET transition losses, 3) INTV
CC
regulator current
and 4) LTC1709 V
IN
current (including loading on the
differential amplifier output).
21
LTC1709-8/LTC1709-9
1) I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
SENSE
,
but is "chopped" between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of L,
R
SENSE
and ESR to obtain I
2
R losses. For example, if each
R
DS(ON)
= 10m
, R
L
= 10m
, and R
SENSE
= 5m
, then the
total resistance is 25m
. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
OUT
for the same external components
and output power level. The combined effects of increas-
ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
3) INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
CC
to
ground. The resulting dQ/dt is a current out of INTV
CC
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
= (Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch input
from an output-derived source will scale the V
IN
current
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
CC
current results in approxi-
mately 3mA of V
IN
current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
4) The V
IN
current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the differential
amplifier output. V
IN
current typically results in a small
(<0.1%) loss.
Other "hidden" losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these "system" level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and a very low ESR at
the switching frequency. A 50W supply will typically
require a minimum of 200
F to 300
F of capacitance
having a maximum of 10m
to 20m
of ESR. The
LTC1709 2-phase architecture typically halves this input
capacitance requirement over competing solutions. Other
losses including Schottky conduction losses during dead-
time and inductor core losses generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
OUT
shifts by an
amount equal to
I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
(
I
LOAD
) also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
The
availability of the I
TH
pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
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22
LTC1709-8/LTC1709-9
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The I
TH
external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop gain and phase. An output current pulse of 20% to
80% of full-load current having a rise time of <2
s will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is
better to look at the Ith pin signal which is in the feedback
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the
same factor that C
C
is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera-
tion. But before you connect, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery, and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straightfor-
ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LT1709 has a maximum input
voltage of 36V, most applications will be limited to 30V by
the MOSFET BV
DSS
.
APPLICATIO S I FOR ATIO
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Figure 9. Automotive Application Protection
V
IN
170989 F09
12V
50A I
PK
RATING
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
LTC1709
23
LTC1709-8/LTC1709-9
Design Example
As a design example, assume V
IN
= 5V (nominal), V
IN
= 5.5V
(max), V
OUT
= 1.8V, I
MAX
= 20A, T
A
= 70
C and f = 300kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQSET pin
to the INTV
CC
pin for 300kHz operation. The minimum
inductance for 30% ripple current is:
L
V
f
I
V
V
V
kHz
A
V
V
H
OUT
OUT
IN
( )
-
(
)( )( )
-
1
1 8
300
30
10
1
1 8
5 5
1 35
.
%
.
.
.
A 1.5
H inductor will produce 27% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 11.4A. The minimum on-
time occurs at maximum V
IN
:
t
V
V f
V
V
kHz
s
ON MIN
OUT
IN
( )
=
=
( )(
)
=
1 8
5 5
300
1 1
.
.
.
The R
SENSE
resistors value can be calculated by using the
maximum current sense voltage specification with some
accomodation for tolerances:
R
mV
A
SENSE
=
50
11 4
0 004
.
.
The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
R
DS(ON)
= 0.013
, C
RSS
= 300pF. At maximum input
voltage with T
J
(estimated) = 110
C at an elevated ambient
temperature:
P
V
V
C
C
V
A
pF
kHz
W
MAIN
=
( )
+
( )
-
(
)
[
]
+
( ) ( )( )
(
)
=
1 8
5 5
10
1
0 005 110
25
0 013
1 7 5 5
10
300
300
0 65
2
2
.
.
.
.
.
.
.
The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50
C junction tem-
perature rise is:
P
V
V
V
A
W
SYNC
=
-
( ) ( )
(
)
=
5 5
1 8
5 5
10
1 48 0 013
1 29
2
.
.
.
.
.
.
A short-circuit to ground will result in a folded back current
of about:
I
mV
ns
V
H
A
SC
=
+
( )
=
25
0 004
1
2
200
5 5
1 5
6 6
.
.
.
.
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50
C junction temperature
rise is:
P
V
V
V
A
mW
SYNC
=
-
( ) ( )
(
)
=
5 5
1 8
5 5
6 6
1 48 0 013
564
2
.
.
.
.
.
.
which is less than half of the normal, full-load dissipation.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.
The duty factor for this application is:
DF
V
V
V
V
O
IN
=
=
=
1 8
5
0 36
.
.
Using Figure 4, the RMS ripple current will be:
I
INRMS
= (20A)(0.23) = 4.6A
RMS
An input capacitor(s) with a 4.6A
RMS
ripple current rating
is required.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure 3
along with the calculated duty factor. The output ripple in
APPLICATIO S I FOR ATIO
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24
LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
W
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continuous mode will be highest at the maximum input
voltage since the duty factor is < 50%. The maximum
output current ripple is:
I
V
fL
at
D F
I
V
kHz
H
A
V
m
A
mV
COUT
OUT
COUTMAX
RMS
OUTRIPPLE
RMS
RMS
=
( )
=
(
)
( )
=
=
(
)
=
0 3
33
1 8
300
1 5
0 3
1 2
20
1 2
24
.
%
.
.
.
.
.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1709. These items are also illustrated graphically in
the layout diagram of Figure 10. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1709 signal ground pin should return to the () plate
of C
OUT
separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and () plates of C
IN
, which should have
as short lead lengths as possible.
2) Does the LTC1709 V
OS
+
pin connect to the point of
load? Does the LTC1709 V
OS
pin connect to the load
return?
3) Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE
+
and SENSE
pin pairs should be as close as
possible to the LTC1709. Ensure accurate current sensing
with Kelvin connections at the current sense resistor.
4) Does the (+) plate of C
IN
connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Is the INTV
CC
1
F ceramic decoupling capacitor con-
nected closely between
INTV
CC
and the power ground pin?
This capacitor carries the MOSFET driver peak currents. A
small value is recommended to allow placement immedi-
ately adjacent to the IC.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1709.
7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
The diagram in Figure 10 illustrates all branch currents in
a 2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
"loops" just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the "noise" generated by a switching regula-
tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the negative plate(s)
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the negative plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur-
rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
25
LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
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Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
R
L
V
OUT
C
OUT
+
D1
L1
SW1
R
SENSE1
V
IN
C
IN
R
IN
+
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
L2
SW2
170989 F10
R
SENSE2
Figure 11. Single and 2-Phase Current Waveforms
I
CIN
SW V
I
COUT
I
CIN
SW1 V
DUAL PHASE
SINGLE PHASE
SW2 V
I
COUT
RIPPLE
1709 F11
I
L1
I
L2
Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by,
and the effective ripple frequency is increased by the
number of phases used. Figure 11 graphically illustrates
the principle.
26
LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
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The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output
voltage. The worst-case RMS ripple current for a two stage
design results in peak outputs of 1/4 and 3/4 of input
voltage. When the RMS current is calculated, higher
effective duty factor results and the peak current levels are
divided as long as the currents in each stage are balanced.
Refer to Application Note 19 for a detailed description of
how to calculate RMS current for the single stage switch-
ing regulator. Figures 3 and 4 help to illustrate how the
input and output currents are reduced by using an addi-
tional phase. The input current peaks drop in half and the
frequency is doubled for this 2-phase converter. The input
capacity requirement is thus reduced theoretically by a
factor of four! Ceramic input capacitors with their
unbeatably low ESR characteristics can be used.
Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.
An interesting result of the 2-phase solution is that the V
IN
which produces worst-case ripple current for the input
capacitor, V
OUT
= V
IN
/2, in the single phase design pro-
duces zero input current ripple in the 2-phase design.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
OUT
/L discharge current
term from the stage that has its bottom MOSFET on
subtracts current from the (V
IN
- V
OUT
)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current is:
I
V
fL
D
D
D
RIPPLE
OUT
=
-
-
( )
-
+
2
1 2
1
1 2
1
where D is duty factor.
The input and output ripple frequency is increased by the
number of stages used, reducing the output capacity
requirements. When V
IN
is approximately equal to 2(V
OUT
)
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
27
LTC1709-8/LTC1709-9
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
G36 SSOP 1098
0.13 0.22
(0.005 0.009)
0
8
0.55 0.95
(0.022 0.037)
5.20 5.38**
(0.205 0.212)
7.65 7.90
(0.301 0.311)
1 2 3 4 5 6 7 8 9 10 11 12
14 15 16 17 18
13
12.67 12.93*
(0.499 0.509)
25
26
22 21 20 19
23
24
27
28
29
30
31
32
33
34
35
36
1.73 1.99
(0.068 0.078)
0.05 0.21
(0.002 0.008)
0.65
(0.0256)
BSC
0.25 0.38
(0.010 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
28
LTC1709-8/LTC1709-9
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000
170989i LT/TP 0500 4K PRINTED IN USA
TYPICAL APPLICATIO
U
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators POR, Auxiliary Regulator
LTC1438-ADJ
Dual Synchronous Controller with Auxiliary Regulator
POR, External Feedback Divider
LTC1538-AUX
Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator
Auxiliary Regulator, 5V Standby
LTC1539
Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator
5V Standby, POR, Low-Battery, Aux Regulator
LTC1436A-PLL
High Efficiency Low Noise Synchronous Step-Down Switching Regulator
Adaptive Power
TM
Mode, 24-Pin SSOP
LTC1628/LTC1628-PG Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
Constant Frequency, Standby, 5V and 3.3V LDOs
LTC1629/LTC1629-PG PolyPhase High Efficiency Controllers
Expandable Up to 12 Phases, G-28, Up to 120A
LTC1929
2-Phase High Efficiency Controller
Adjustable Output Up to 40A, G-28
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Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
500kHz, 25MHz GBW
LTC1708-PG
Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator
1.3V
V
OUT
3.5V, Current Mode Ensures
with 5-Bit VID and Power Good Indication
Accurate Current Sharing, 3.5V
V
IN
36V
LTC1709
High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator
1.3V
V
OUT
3.5V, Current Mode Ensures
with 5-Bit VID and Fault Coupling Control
Accurate Current Sharing, 3.5V
V
IN
36V
LTC1735
High Efficiency Synchronous Step-Down Controller
Burst Mode
TM
Operation, 16-Pin Narrow SSOP,
Fault Protection, 3.5V
V
IN
36V
LTC1736
High Efficiency Synchronous Step-Down Controller with 5-Bit VID
Output Fault Protection, Power Good, GN-24,
3.5V
V
IN
36V, 0.925V
V
OUT
2V
Adaptive Power and Burst Mode are trademarks of Linear Technology Corporation.
Figure 12. 1.3V to 2.5V/20A CPU Power Supply with Active Voltage Positioning
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RUNN/SS
SENSE1
+
SENSE1
EAIN
PLLFLTR
PLLIN
NC
I
TH
SGND
V
DIFFOUT
V
OS
V
OS
+
SENSE2
SENSE2
+
ATTENOUT
ATTENIN
VID0
VID1
NC
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
PGOOD
V
BIAS
VID4
VID3
VID2
1000pF
0.22
F
LTC1709-8
M1
M2
D1
MBRS140T3
D2
MBRS140T3
V
IN
5V TO 28V
V
OUT
1.3V TO 3.5V
20A
SWITCHING FREQUENCY = 200kHz
C
IN
: 5A RIPPLE CURRENT RATING REQUIRED
C
OUT
: 4
180
F/4V PANASONIC SP
L1 TO L2: 1.5
H SUMIDA CEP125-1R5MC
M1 TO M4: FAIRCHILD FDS7760A
10
F
0.1
F
5V (OPT)
470pF
VID INPUTS
1000pF
100pF
3.3nF
INTV
CC
0.1
F
47k
15k
10k
2.7k
51k
0.22
F
0.1
F
PGOOD
10
100k
10
C
IN
47
F 35V
0.004
0.004
M3
L2
M4
170989 F12
C
OUT
+
+
L1
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