1
LTC2401/LTC2402
1-/2-Channel 24-Bit
Power
No Latency
TM
ADC in MSOP-10
January 2000
s
Weight Scales
s
Direct Temperature Measurement
s
Gas Analyzers
s
Strain-Gage Transducers
s
Instrumentation
s
Data Acquisition
s
Industrial Process Control
No Latency
is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Pseudo Differential Bridge Digitizer
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
2401/LTC2402 are 1- and 2-channel 2.7V to
5.5V micropower 24-bit analog-to-digital converters with
an integrated oscillator, 4ppm INL and 0.6ppm RMS
noise. These ultrasmall devices use delta-sigma technol-
ogy and a new digital filter architecture that settles in a
single cycle. This eliminates the latency found in conven-
tional
converters and simplifies multiplexed applica-
tions.
Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz
2%, or can be driven by an external oscillator for
a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external fre-
quency setting components.
These converters accept an external reference voltage
from 0.1V to V
CC
. With an extended input conversion
range of 12.5% V
REF
to 112.5% V
REF
(V
REF
= FS
SET
ZS
SET
), the LTC2401/LTC2402 smoothly resolve the off-
set and overrange problems of preceding sensors or
signal conditioning circuits.
The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRE
TM
protocols.
s
24-Bit ADC in Tiny MSOP-10 Package
s
1- or 2-Channel Inputs
s
Automatic Channel Selection (Ping-Pong) (LTC2402)
s
Zero Scale and Full Scale Set for Reference
and Ground Sensing
s
4ppm INL, No Missing Codes
s
4ppm Full-Scale Error
s
0.5ppm Offset
s
0.6ppm Noise
s
Internal Oscillator--No External Components Required
s
110dB Min, 50Hz/60Hz Notch Filter
s
Single Conversion Settling Time for
Multiplexed Applications
s
Reference Input Voltage: 0.1V to V
CC
s
Live Zero--Extended Input Range Accommodates
12.5% Overrange and Underrange
s
Single Supply 2.7V to 5.5V Operation
s
Low Supply Current (200
A) and Auto Shutdown
ANALOG
INPUT RANGE
0.12V
REF
TO 1.12V
REF
(V
REF
= FS
SET
ZS
SET
)
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
0V TO FS
SET
100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
1
F
1
10
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
24012 TA01
V
CC
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Final Electrical Specifications
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
V
CC
FS
SET
ZS
SET
SCK
CH0
SDO
F
O
CS
CH1
GND
LTC2402
3-WIRE
SPI INTERFACE
INTERNAL OSCILLATOR
60Hz REJECTION
1
9
2.7V TO 5.5V
8
7
10
6
24012TA02
2
4
3
5
2
LTC2401/LTC2402
ORDER PART NUMBER
Consult factory for Military grade parts.
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ....................... 0.3V to 7V
Analog Input Voltage to GND ....... 0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
T
JMAX
= 125
C,
JA
= 130
C/W
LTC2401CMS
LTC2401IMS
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
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PACKAGE/ORDER I
N
FOR
M
ATIO
N
U
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1
2
3
4
5
V
CC
FS
SET
CH1
CH0
ZS
SET
10
9
8
7
6
F
O
SCK
SDO
CS
GND
TOP VIEW
MS10 PACKAGE
10-LEAD PLASTIC MSOP
Operating Temperature Range
LTC2401/LTC2402C ................................ 0
C to 70
C
LTC2401/LTC2402I ............................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
ORDER PART NUMBER
MS10 PART MARKING
LTC2402CMS
LTC2402IMS
LTMD
LTME
MS10 PART MARKING
LTMB
LTMC
T
JMAX
= 125
C,
JA
= 130
C/W
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
q
24
Bits
No Missing Codes Resolution
0.1V
FS
SET
V
CC
, ZS
SET
= 0V (Note 5)
q
24
Bits
Integral Nonlinearity
FS
SET
= 2.5V, ZS
SET
= 0V (Note 6)
q
2
10
ppm of V
REF
FS
SET
= 5V, ZS
SET
= 0V (Note 6)
q
4
15
ppm of V
REF
Offset Error
2.5V
FS
SET
V
CC
, ZS
SET
= 0V
q
0.5
2
ppm of V
REF
Offset Error Drift
2.5V
FS
SET
V
CC
, ZS
SET
= 0V
0.01
ppm of V
REF
/
C
Full-Scale Error
2.5V
FS
SET
V
CC
, ZS
SET
= 0V
q
4
10
ppm of V
REF
Full-Scale Error Drift
2.5V
FS
SET
V
CC
, ZS
SET
= 0V
0.04
ppm of V
REF
/
C
Total Unadjusted Error
FS
SET
= 2.5V, ZS
SET
= 0V
5
ppm of V
REF
FS
SET
= 5V, ZS
SET
= 0V
10
ppm of V
REF
Output Noise
V
IN
= 0V (Note 13)
3
V
RMS
Normal Mode Rejection 60Hz
2%
(Note 7)
q
110
130
dB
Normal Mode Rejection 50Hz
2%
(Note 8)
q
110
130
dB
Power Supply Rejection, DC
FS
SET
= 2.5V, ZS
SET
= 0V, V
IN
= 0V
100
dB
Power Supply Rejection, 60Hz
2%
FS
SET
= 2.5V, ZS
SET
= 0V, V
IN
= 0V, (Note 7)
110
dB
Power Supply Rejection, 50Hz
2%
FS
SET
= 2.5V, ZS
SET
= 0V, V
IN
= 0V, (Note 8)
110
dB
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
REF
= FS
SET
ZS
SET
. (Notes 3, 4)
CO
N
VERTER CHARACTERISTICS
U
1
2
3
4
5
V
CC
FS
SET
V
IN
NC
ZS
SET
10
9
8
7
6
TOP VIEW
MS10 PACKAGE
10-LEAD PLASTIC MSOP
F
O
SCK
SDO
CS
GND
3
LTC2401/LTC2402
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V
q
2.5
V
CS, F
O
2.7V
V
CC
3.3V
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V
q
0.8
V
CS, F
O
2.7V
V
CC
5.5V
0.6
V
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V (Note 9)
q
2.5
V
SCK
2.7V
V
CC
3.3V (Note 9)
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V (Note 9)
q
0.8
V
SCK
2.7V
V
CC
5.5V (Note 9)
0.6
V
I
IN
Digital Input Current
0V
V
IN
V
CC
q
10
10
A
CS, F
O
I
IN
Digital Input Current
0V
V
IN
V
CC
(Note 9)
q
10
10
A
SCK
C
IN
Digital Input Capacitance
10
pF
CS, F
O
C
IN
Digital Input Capacitance
(Note 9)
10
pF
SCK
V
OH
High Level Output Voltage
I
O
= 800
A
q
V
CC
0.5
V
SDO
V
OL
Low Level Output Voltage
I
O
= 1.6mA
q
0.4
V
SDO
V
OH
High Level Output Voltage
I
O
= 800
A (Note 10)
q
V
CC
0.5
V
SCK
V
OL
Low Level Output Voltage
I
O
= 1.6mA (Note 10)
q
0.4
V
SCK
I
OZ
High-Z Output Leakage
q
10
10
A
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
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SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
q
2.7
5.5
V
I
CC
Supply Current
Conversion Mode
CS = 0V (Note 12)
q
200
300
A
Sleep Mode
CS = V
CC
(Note 12)
q
20
30
A
POWER REQUIRE E TS
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The
q
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
The
q
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
(Note 14)
q
0.125 V
REF
1.125 V
REF
V
FS
SET
Full-Scale Set Range
q
0.1 + ZS
SET
V
CC
V
ZS
SET
Zero-Scale Set Range
q
0
FS
SET
0.1
V
C
S(IN)
Input Sampling Capacitance
10
pF
C
S(REF)
Reference Sampling Capacitance
15
pF
I
IN(LEAK)
Input Leakage Current
CS = V
CC
q
10
1
10
nA
I
REF(LEAK)
Reference Leakage Current
V
REF
= 2.5V, CS = V
CC
q
12
1
12
nA
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
REF
= FS
SET
ZS
SET
. (Note 3)
A ALOG I PUT A D REFERE CE
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LTC2401/LTC2402
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
f
EOSC
External Oscillator Frequency Range
q
2.56
307.2
kHz
t
HEO
External Oscillator High Period
q
0.5
390
s
t
LEO
External Oscillator Low Period
q
0.5
390
s
t
CONV
Conversion Time
F
O
= 0V
q
130.66
133.33
136
ms
F
O
= V
CC
q
156.80
160
163.20
ms
External Oscillator (Note 11)
q
20480/f
EOSC
(in kHz)
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
19.2
kHz
External Oscillator (Notes 10, 11)
f
EOSC
/8
kHz
D
ISCK
Internal SCK Duty Cycle
(Note 10)
45
55
%
f
ESCK
External SCK Frequency Range
(Note 9)
q
2000
kHz
t
LESCK
External SCK Low Period
(Note 9)
q
250
ns
t
HESCK
External SCK High Period
(Note 9)
q
250
ns
t
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
q
1.64
1.67
1.70
ms
External Oscillator (Notes 10, 11)
q
256/f
EOSC
(in kHz)
ms
t
DOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
q
32/f
ESCK
(in kHz)
ms
t
1
CS
to SDO Low Z
q
0
150
ns
t2
CS
to SDO High Z
q
0
150
ns
t3
CS
to SCK
(Note 10)
q
0
150
ns
t4
CS
to SCK
(Note 9)
q
50
ns
t
KQMAX
SCK
to SDO Valid
q
200
ns
t
KQMIN
SDO Hold After SCK
(Note 5)
q
15
ns
t
5
SCK Set-Up Before CS
q
50
ns
t
6
SCK Hold After CS
q
50
ns
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 2.7 to 5.5V unless otherwise specified. Input source
resistance = 0
.
Note 4: Internal Conversion Clock source with the F
O
pin tied
to GND or to V
CC
or to external conversion clock source with
f
EOSC
= 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: F
O
= 0V (internal oscillator) or f
EOSC
= 153600Hz
2%
(external oscillator).
Note 8: F
O
= V
CC
(internal oscillator) or f
EOSC
= 128000Hz
2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f
ESCK
and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation, the
SCK pin has a total equivalent load capacitance C
LOAD
= 20pF.
Note 11: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
F
O
= 0V or F
O
= V
CC
.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values V
REF
> 2.5V, the extended input
of 0.125 V
REF
to 1.125 V
REF
is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V
REF
0.267V + 0.89 V
CC
, the input voltage range is 0.3V to 1.125 V
REF
.
For 0.267V + 0.89 V
CC
< V
REF
V
CC
, the input voltage range is 0.3V
to V
CC
+ 0.3V.
TI I G CHARACTERISTICS
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LTC2401/LTC2402
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin 4) with a 10
F tantalum capacitor in parallel with
0.1
F ceramic capacitor as close to the part as possible.
FS
SET
(Pin 2): Full-Scale Set Input. This pin defines the
full-scale input value. When V
IN
= FS
SET
, the ADC outputs
full scale (FFFFF
H
). The total reference voltage is
FS
SET
ZS
SET
.
CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is 0.125 V
REF
to 1.125 V
REF
. For
V
REF
> 2.5V, the input voltage range may be limited by the
absolute maximum rating of 0.3V to V
CC
+ 0.3V. Conver-
sions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.
ZS
SET
(Pin 5): Zero-Scale Set Input. This pin defines the
zero-scale input value. When V
IN
= ZS
SET
, the ADC
outputs zero scale (00000
H
).
GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single-point grounding system.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = V
CC
), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.
F
O
(Pin 10): Frequency Control Pin. Digital input that
controls the ADC's notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter's
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= 0V), the converter uses its internal oscillator
and the digital filter's first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f
EOSC
/2560.
PI
N
FU
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LTC2401/LTC2402
APPLICATIO S I FOR ATIO
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Output Data Format
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is LOW if the last conversion
was performed on CH0 and HIGH for CH1.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero
code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
V
IN
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2401/LTC2402 Status Bits
Bit 31
Bit 30
Bit 29
Bit 28
Input Range
EOC
CH0/CH1
SIG
EXR
V
IN
> V
REF
0
0/1
1
1
0 < V
IN
V
REF
0
0/1
1
0
V
IN
= 0
+
/0
0
0/1
1/0
0
V
IN
< 0
0
0/1
0
1
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 1. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
MSB
EXT
SIG
CH0/CH1
1
2
3
4
5
27
28
32
BIT 0
BIT 27
BIT 4
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
24012 F01
Hi-Z
Figure 1. Output Data Timing
7
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
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falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the 0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from 0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below 0.125 V
REF
, the conversion result is
clamped to the value corresponding to 0.125 V
REF
.
Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing
Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
Table 2. LTC2401/LTC2402 Output Data Format
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Bit 23
...
Bit 4
Bit 3-0
Input Voltage
EOC
CH SELECT
SIG
EXR
MSB
LSB
SUB LSBs*
V
IN
> 9/8 V
REF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
9/8 V
REF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
V
REF
+ 1LSB
0
CH0/CH1
1
1
0
0
0
0
0
...
0
X
V
REF
0
CH0/CH1
1
0
1
1
1
1
1
...
1
X
3/4V
REF
+ 1LSB
0
CH0/CH1
1
0
1
1
0
0
0
...
0
X
3/4V
REF
0
CH0/CH1
1
0
1
0
1
1
1
...
1
X
1/2V
REF
+ 1LSB
0
CH0/CH1
1
0
1
0
0
0
0
...
0
X
1/2V
REF
0
CH0/CH1
1
0
0
1
1
1
1
...
1
X
1/4V
REF
+ 1LSB
0
CH0/CH1
1
0
0
1
0
0
0
...
0
X
1/4V
REF
0
CH0/CH1
1
0
0
0
1
1
1
...
1
X
0
+
/0
0
CH0/CH1
1/0**
0
0
0
0
0
0
...
0
X
1LSB
0
CH0/CH1
0
1
1
1
1
1
1
...
1
X
1/8 V
REF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
V
IN
< 1/8 V
REF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
V
FULL-SCALE ERROR
SENSOR
SENSOR OUTPUT
R
P1
I
EXCITATION
+
V
OFFSET ERROR
+
+
R
P2
24012 F02
Figure 2. Errors Due to Excitation Currents
through the sensor. The wires connecting the sensor to the
ADC form parasitic resistors R
P1
and R
P2
. The excitation
current also flows through parasitic resistors R
P1
and R
P2
,
as shown in Figure 2. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.
In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a full-
scale set input (FS
SET
) and a zero-scale set input
(ZS
SET
). As shown in Figure 3, the FS
SET
pin acts as a zero
input full-scale sense input. Errors due to parasitic resis-
tance R
P1
in series with the half-bridge sensor are
8
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
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00000
H
12.5%
EXTENDED
RANGE
ADC DATA OUT
FFFFF
H
ZS
SET
FS
SET
V
IN
24012 F04
12.5%
EXTENDED
RANGE
Figure 4. Transfer Curve with Zero-Scale and Full-Scale Set
removed by the FS
SET
input to the ADC. The absolute full-
scale output of the ADC (data out = FFFFFF
HEX
) will occur
at V
IN
= V
B
= FS
SET
, see Figure 4. Similarly, the offset errors
due to R
P2
are removed by the ground sense input ZS
SET
.
The absolute zero output of the ADC (data out = 000000
HEX
)
occurs at V
IN
= V
A
= ZS
SET
. Parasitic resistors R
P3
to R
P5
have negligible errors due to the 1nA (typ) leakage current
at pins FS
SET
, ZS
SET
and V
IN
. The wide dynamic input
range ( 300mV to 5.3V) and low noise (0.6ppm RMS)
enable the LTC2401 or the LTC2402 to directly digitize the
output of the bridge sensor.
The LTC2402 is ideal for applications requiring continu-
ous monitoring of two input sensors. As shown in
Figure 5, the LTC2402 can monitor both a thermocouple
temperature probe and a cold junction temperature sen-
sor. Absolute temperature measurements can be
performed with a variety of thermocouples using digital
cold junction compensation.
The selection between CH0 and CH1 is automatic. Initially,
after power-up, a conversion is performed on CH0. For
each subsequent conversion, the input channel selection
Figure 5. Isolated Temperature Measurement
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
THERMOCOUPLE
COLD JUNCTION
ISOLATION
BARRIER
PROCESSOR
CH0
+
1
10
12k
THERMISTOR
100
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
24012 F05
V
CC
LTC2401
FS
SET
GND
SCK
V
IN
SDO
F
O
CS
ZS
SET
3-WIRE
SPI INTERFACE
1
9
8
7
10
24012 F03
2
3
5
R
P2
R
P5
I
DC
= 0
R
P1
V
B
V
A
6
R
P4
I
DC
= 0
I
EXCITATION
R
P3
I
DC
= 0
Figure 3. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense
9
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APPLICATIO S I FOR ATIO
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Figure 6. Embedded Selected Channel Indicator
24012 F06
SCK
SDO
CH1
CH1 DATA OUT
CH0 DATA OUT
EOC
CH0
EOC
is alternated. Embedded within the serial data output is a
status bit indicating which channel corresponds to the
conversion result. If the conversion was performed on
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion
was performed on CH1 (see Figure 6).
There are no extra control or status pins required to
perform the alternating 2-channel measurements. The
LTC2402 only requires two digital signals (SCK and SDO).
This simplification is ideal for isolated temperature mea-
surements or systems where minimal control signals are
available.
Pseudo Differential Applications
Generally, designers choose fully differential topologies
for several reasons. First, the interface to a 4- or 6-wire
bridge is simple (it is a differential output). Second, they
require good rejection of line frequency noise. Third, they
typically look at a small differential signal sitting on a
large common mode voltage; they need accurate
measurements of the differential signal independent of
the common mode input voltage. Many applications
currently using fully differential analog-to-digital con-
verters for any of the above reasons may migrate to a
pseudo differential conversion using the LTC2402.
Direct Connection to a Full Bridge
The LTC2402 interfaces directly to a 4- or 6-wire bridge, as
shown in Figure 7. Like the LTC2401, the LTC2402 in-
cludes a FS
SET
and a ZS
SET
for sensing the excitation
voltage directly across the bridge. This eliminates errors
due to excitation currents flowing through parasitic resis-
tors. The LTC2402 also includes two single ended input
channels which can tie directly to the differential output of
the bridge. The two conversion results may be digitally
subtracted yielding the differential result.
V
CC
LTC2402
FS
SET
ZS
SET
SCK
CH1
SDO
F
O
CS
CH0
GND
3-WIRE
SPI INTERFACE
1
5V
9
8
7
10
24012 F07
2
350
350
350
350
3
4
5
I
DC
= 0
I
EXCITATION
I
DC
= 0
Figure 7. Pseudo Differential Strain Guage Application
10
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The LTC2402's single ended rejection of line frequencies
(
2%) and harmonics is better than 110dB. Since the
device performs two independent single ended conver-
sions each with > 110dB rejection, the overall common
mode and differential rejection is much better than the
80dB rejection typically found in other differential input
delta-sigma converters.
In addition to excellent rejection of line frequency noise,
the LTC2402 also exhibits excellent single ended noise
rejection over a wide range of frequencies due to its 4
th
order sinc filter. Each single ended conversion indepen-
dently rejects high frequency noise (> 60Hz). Care must be
taken to insure noise at frequencies below 15Hz and at
multiples of the ADC sample rate (15,600Hz) are not
present. For this application, it is recommended the
LTC2402 is placed in close proximity to the bridge sensor
in order to reduce the noise injected into the ADC input. By
performing three successive conversions (CH0-CH1-CH0),
the drift and low frequency noise can be measured and
compensated for digitally.
The absolute accuracy (less than 10 ppm total error) of the
LTC2402 enables extremely accurate measurement of
small signals sitting on large voltages. Each of the two
pseudo differential measurements performed by the
LTC2402 is absolutely accurate independent of the com-
mon mode voltage output from the bridge. The pseudo
differential result obtained from digitally subtracting the
two single ended conversion results is accurate to within
the noise level of the device (3
V
RMS
) divided by square
root of 2, independent of the common mode input voltage.
Typically, a bridge sensor outputs 2mV/V full scale. With
a 5V excitation, this translates to a full-scale output of
10mV. Divided by the RMS noise of 4.2
V(= 3
V 1.414),
this circuit yields 2,300 counts with no averaging or
amplification. If more counts are required, several conver-
sions may be averaged (the number of effective counts is
increased by a factor of square root of 2 for each doubling
of averages).
An RTD Temperature Digitizer
RTDs used in remote temperature measurements often
have long lead lengths between the ADC and RTD sensor.
These long lead lengths lead to voltage drops due to
excitation current in the interconnect to the RTD. This
voltage drop can be measured and digitally removed using
the LTC2402 (see Figure 8).
The excitation current (typically 200
A) flows from the
ADC through a long lead length to the remote temperature
sensor (RTD). This current is applied to the RTD, whose
resistance changes as a function of temperature (100
to
400
for 0
C to 800
C). The same excitation current flows
back to the ADC ground and generates another voltage
drop across the return leads. In order to get an accurate
measurement of the temperature, these voltage drops
must be measured and removed from the conversion
result. Assuming the resistance is approximately the same
V
CC
LTC2402
FS
SET
ZS
SET
SCK
CH0
SDO
F
O
CS
CH1
GND
3-WIRE
SPI INTERFACE
1
5V
9
8
7
10
24012 F08
2
4
3
+
V
RTD
P
t
100
5
I
DC
= 0
I
EXCITATION
= 200
A
I
EXCITATION
= 200
A
R2
R1
Figure 8. RTD Remote Temperature Measurement
11
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
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for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
The result of the first conversion on CH0 corresponds to
an input voltage of V
RTD
+ R1 I
EXCITATION.
The result of the
second conversion (CH1) is R1 I
EXCITATION.
Note, the
LTC2402's input range is not limited to the supply rails, it
has underrange capabilities. The device's input range is
300mV to V
REF
+ 300mV. Adding the two conversion
results together, the voltage drop across the RTD's leads
are cancelled and the final result is V
RTD
.
An Isolated, 24-Bit Data Acquisition System
The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.
+
+
F
O
SCK
SDO
CS
GND
V
CC
FS
SET
CH1
CH0
ZS
SET
LTC2402
24012 F09
LT1761-5
GND
10
F
10V
TANT
10
F
10V
TANT
+
10
F
16V
TANT
+
10
F
10V
TANT
10
F
1
F
T1
1/2 BAT54C
1/2 BAT54C
ISOLATION
BARRIER
= LOGIC COMMON
= FLOATING COMMON
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
1k
2
2
1
2
1
1
1
2
2
2
2
10
F
CERAMIC
A
B
Y
Z
RO
RE
DE
DI
V
CC2
ST2
G1
V
CC1
G2
ST1
"SDO"
"SCK"
LOGIC 5V
IN
OUT
SHDN
BYP
LTC1535
Figure 9. Complete, Isolated 24-Bit Data Acquisition System
During power-up, the LTC2402 becomes active at V
CC
=
2.3V, while the isolated side of the LTC1535 must wait for
V
CC2
to reach its undervoltage lockout threshold of 4.2V.
Below 4.2V, the LTC1535's driver outputs Y and Z are in a
high impedance state, allowing the 1k
pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic "0" provided by
the 1k
pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535's driver output Y. The entire power-up sequence,
from the time power is applied to V
CC1
until the LT1761's
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535's
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2402's SDO output
without the need for any external components.
12
LTC2401/LTC2402
24012i LT/TP 0100 4K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/
C Drift, 0.05% Max
LT1025
Micropower Thermocouple Cold Junction Compensator
80
A Supply Current, 0.5
C Initial Accuracy
LTC1043
Dual Precision Instrumentation Switched Capacitor
Precise Charge, Balanced Switching, Low Power
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5
V Offset, 1.6
V
P-P
Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/
C Drift
LTC1391
8-Channel Multiplexer
Low R
ON
: 45
, Low Charge Injection Serial Interface
LT1460
Micropower Series Reference
0.075% Max, 10ppm/
C Max Drift, 2.5V, 5V and 10V Versions,
MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages
LT1461-2.5
Precision Micropower Voltage Reference
50
A Supply Current, 3ppm/
C Drift
LTC2400
24-Bit, No Latency
ADC in SO-8
4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency
ADC
4ppm INL, 10ppm Total Unadjusted Error, 200
A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
PACKAGE I FOR ATIO
U
U
W
Dimensions in inches (millimeters) unless otherwise noted.
MS10 Package
10-Lead Plastic MSOP
(LTC DWG # 05-08-1661)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021
0.006
(0.53
0.015)
0
6
TYP
SEATING
PLANE
0.007
(0.18)
0.040
0.006
(1.02
0.15)
0.009
(0.228)
REF
0.006
0.004
(0.15
0.102)
0.034
0.004
(0.86
0.102)
0.0197
(0.50)
BSC
MSOP (MS10) 1098
1 2 3 4 5
0.193
0.006
(4.90
0.15)
8
9
10
7 6
0.118
0.004*
(3.00
0.102)
0.118
0.004**
(3.00
0.102)
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