LTC2415/LTC2415-1

sn2415 24151fs

××
××
×

Speed Up Version of the LTC2410/LTC2413:

15Hz Output Rate, 50Hz or 60Hz Notch--LTC2415;
13.75Hz Output Rate, Simultaneous 50Hz/60Hz
Notch--LTC2415-1

Differential Input and Differential Reference with
GND to V

Common Mode Range

2ppm INL, No Missing Codes

2.5ppm Gain Error

0.23ppm Noise

Single Conversion Settling Time for Multiplexed
Applications

Internal Oscillator--No External Components
Required

24-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200

A) and Auto Shutdown

The LTC

2415/2415-1 are micropower 24-bit differential

analog to digital converters with integrated oscillator,

2ppm INL, 0.23ppm RMS noise and a 2.7V to 5.5V supply
range. They use delta-sigma technology and provide
single cycle settling time for multiplexed applications.
Through a single pin, the LTC2415 can be configured for
better than 110dB input differential mode rejection at
50Hz or 60Hz

2%, or it can be driven by an external

oscillator for a user defined rejection frequency. The
LTC2415-1 can be configured for better than 87dB input
differential mode rejection over the range of 49Hz to
61.2Hz (50Hz and 60Hz

2% simultaneously). The inter-

nal oscillator requires no external frequency setting com-
ponents.

The converters accept any external differential reference
voltage from 0.1V to V

for flexible ratiometric and

remote sensing measurement configurations. The full-
scale differential input range is from 0.5V

REF

to 0.5V

REF

The reference common mode voltage, V

REFCM

, and the

input common mode voltage, V

INCM

, may be indepen-

dently set anywhere within the GND to V

range of the

LTC2415/LTC2415-1. The DC common mode input rejec-
tion is better than 140dB.

The LTC2415/LTC2415-1 communicate through a flexible
3-wire digital interface which is compatible with SPI and
MICROWIRE

protocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

24-Bit No Latency

ADCs with Differential Input and

Differential Reference

No Latency

is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

= INTERNAL OSC/50Hz REJECTION (LTC2415)
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2415)
= INTERNAL 50Hz/60Hz REJECTION (LTC2415-1)

3-WIRE
SPI INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

2415 TA01

LTC2415/

LTC2415-1

REF

GND

SDO

3-WIRE
SPI INTERFACE

SCK

2415 TA02

1, 7, 8
9, 10,
15, 16

BRIDGE

IMPEDANCE

100

TO 10k

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO S

APPLICATIO S

Direct Sensor Digitizer

Weight Scales

Direct Temperature Measurement

Gas Analyzers

Strain Gage Transducers

Instrumentation

Data Acquisition

Industrial Process Control

6-Digit DVMs

LTC2415/LTC2415-1

sn2415 24151fs

ABSOLUTE AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

ELECTRICAL CHARACTERISTICS

(Notes 1, 2)

ORDER PART NUMBER

Supply Voltage (V

) to GND ....................... 0.3V to 7V

Analog Input Pins Voltage
to GND .................................... 0.3V to (V

+ 0.3V)

Reference Input Pins Voltage
to GND .................................... 0.3V to (V

+ 0.3V)

Digital Input Voltage to GND ........ 0.3V to (V

+ 0.3V)

Digital Output Voltage to GND ..... 0.3V to (V

+ 0.3V)

Operating Temperature Range

LTC2415C/LTC2415-1C ........................... 0

C to 70

LTC2415I/LTC2415-1I ........................ 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

JMAX

= 125

= 95

C/W

LTC2415CGN
LTC2415IGN
LTC2415-1CGN
LTC2415-1IGN

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes)

0.1V

REF

, 0.5 · V

REF

0.5 · V

REF

, (Note 5)

Bits

Integral Nonlinearity

5.5V, REF

= 2.5V, REF

= GND, V

INCM

= 1.25V, (Note 6)

ppm of V

REF

5.5V, REF

= 5V, REF

= GND, V

INCM

= 2.5V, (Note 6)

ppm of V

REF

= 2.5V, REF

= GND, V

INCM

= 1.25V, (Note 6)

ppm of V

REF

Offset Error

2.5V

REF

, REF

= GND,

0.5

GND

= IN

, (Note 14)

Offset Error Drift

2.5V

REF

, REF

= GND,

nV/

GND

= IN

Positive Gain Error

2.5V

REF

, REF

= GND,

2.5

ppm of V

REF

= 0.75REF

, IN

= 0.25 · REF

Positive Gain Error Drift

2.5V

REF

, REF

= GND,

0.03

ppm of V

REF

= 0.75REF

, IN

= 0.25 · REF

Negative Gain Error

2.5V

REF

, REF

= GND,

2.5

ppm of V

REF

= 0.25 · REF

, IN

= 0.75 · REF

Negative Gain Error Drift

2.5V

REF

, REF

= GND,

0.03

ppm of V

REF

= 0.25 · REF

, IN

= 0.75 · REF

Output Noise

5.5V, REF

= 5V, REF

= GND,

1.1

RMS

GND

= IN

, (Note 13)

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

GN PART MARKING

2415
2415I
24151
24151I

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

GND

REF

GND

SCK

SDO

GND

Consult LTC Marketing for parts specified with wider operating temperature ranges.

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

CO VERTER CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Common Mode Rejection DC

2.5V

REF

, REF

= GND,

130

140

GND

= IN

LTC2415/LTC2415-1

sn2415 24151fs

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Absolute/Common Mode IN

Voltage

GND 0.3V

+ 0.3V

Absolute/Common Mode IN

Voltage

GND 0.3V

+ 0.3V

Input Differential Voltage Range

REF

(IN

)

REF

Absolute/Common Mode REF

Voltage

0.1

REF

Absolute/Common Mode REF

Voltage

GND

0.1V

REF

Reference Differential Voltage Range

0.1

(REF

REF

)

(IN

)

Sampling Capacitance

(IN

)

Sampling Capacitance

(REF

)

REF

Sampling Capacitance

(REF

)

REF

Sampling Capacitance

DC_LEAK

(IN

)

DC Leakage Current

CS = V

, IN

= GND

DC_LEAK

(IN

)

DC Leakage Current

CS = V

, IN

= GND

DC_LEAK

(REF

)

REF

DC Leakage Current

CS = V

, REF

= 5V

DC_LEAK

(REF

)

REF

DC Leakage Current

CS = V

, REF

= GND

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Note 3)

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CO VERTER CHARACTERISTICS

A ALOG I PUT A

D REFERE CE

Input Common Mode Rejection

2.5V

REF

, REF

= GND,

140

60Hz

2% (LTC2415)

GND

= IN

, (Note 7)

Input Common Mode Rejection

2.5V

REF

, REF

= GND,

140

50Hz

2% (LTC2415)

GND

= IN

, (Note 8)

Input Normal Mode Rejection

(Note 7)

110

140

60Hz

2% (LTC2415)

Input Normal Mode Rejection

(Note 8)

110

140

50Hz

2% (LTC2415)

Input Common Mode Rejection

2.5V

REF

, REF

= GND,

140

49Hz to 61.2Hz (LTC2415-1)

GND

= IN

, (Note 7)

Input Normal Mode Rejection

= GND

49Hz to 61.2Hz (LTC2415-1)

Input Normal Mode Rejection

External Oscillator

External Clock f

EOSC

/2560

14%

(LTC2415-1)

Input Normal Mode Rejection

External Oscillator

110

140

External Clock f

EOSC

/2560

(LTC2415-1)

Reference Common Mode

2.5V

REF

, GND

REF

2.5V,

130

140

Rejection DC

REF

= 2.5V, IN

= IN

= GND

Power Supply Rejection, DC

REF

= V

, REF

= GND, IN

= IN

= GND

100

Power Supply Rejection, 60Hz

2% REF

= 2.5V, REF

= GND, IN

= IN

= GND, (Note 7)

120

Power Supply Rejection, 50Hz

2% REF

= 2.5V, REF

= GND, IN

= IN

= GND, (Note 8)

120

LTC2415/LTC2415-1

sn2415 24151fs

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

5.5

Supply Current

Conversion Mode

CS = 0V (Note 12)

200

300

Sleep Mode

CS = V

(Note 12)

The

denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T

= 25

C. (Note 3)

The

denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T

= 25

C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

High Level Input Voltage

2.7V

5.5V

2.5

CS, F

2.7V

3.3V

2.0

Low Level Input Voltage

4.5V

5.5V

0.8

CS, F

2.7V

5.5V

0.6

High Level Input Voltage

2.7V

5.5V (Note 9)

2.5

SCK

2.7V

3.3V (Note 9)

2.0

Low Level Input Voltage

4.5V

5.5V (Note 9)

0.8

SCK

2.7V

5.5V (Note 9)

0.6

Digital Input Current

CS, F

Digital Input Current

(Note 9)

SCK

Digital Input Capacitance

CS, F

Digital Input Capacitance

(Note 9)

SCK

High Level Output Voltage

= 800

0.5

SDO

Low Level Output Voltage

= 1.6mA

0.4

SDO

High Level Output Voltage

= 800

A (Note 10)

0.5

SCK

Low Level Output Voltage

= 1.6mA (Note 10)

0.4

SCK

Hi-Z Output Leakage

SDO

DIGITAL I PUTS A D DIGITAL OUTPUTS

POWER REQUIRE E TS

LTC2415/LTC2415-1

sn2415 24151fs

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: V

= 2.7 to 5.5V unless otherwise specified.

REF

= REF

REF

, V

REFCM

= (REF

+ REF

)/2;

= IN

, V

INCM

= (IN

+ IN

)/2.

Note 4: F

pin tied to GND or to V

or to external conversion clock

source with f

EOSC

= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.

Note 7: F

= 0V (internal oscillator) or f

EOSC

= 153600Hz

(external oscillator).

Note 8: F

= V

(internal oscillator) or f

EOSC

= 128000Hz

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

ESCK

and is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the F

pin. The external

oscillator frequency, f

EOSC

, is expressed in kHz.

Note 12: The converter uses the internal oscillator.
F

= 0V or F

= V

Note 13: The output noise includes the contribution of the internal
calibration operations.

Note 14: Refer to Offset Accuracy and Drift in the Applications
Information section.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

EOSC

External Oscillator Frequency Range

2.56

2000

kHz

HEO

External Oscillator High Period

0.25

390

LEO

External Oscillator Low Period

0.25

390

CONV

Conversion Time (LTC2415)

= 0V

65.43

66.77

68.1

= V

78.52

80.12

81.72

External Oscillator (Note 11)

10278/f

EOSC

(in kHz)

Conversion Time (LTC2415-1)

= 0V

71.3

72.8

74.3

External Oscillator (Note 11)

10278/f

EOSC

(in kHz)

ISCK

Internal SCK Frequency

Internal Oscillator (Note 10), LTC2415

19.2

kHz

Internal Oscillator (Note 10), LTC2415-1

17.5

kHz

External Oscillator (Notes 10, 11)

EOSC

kHz

ISCK

Internal SCK Duty Cycle

(Note 10)

ESCK

External SCK Frequency Range

(Note 9)

2000

kHz

LESCK

External SCK Low Period

(Note 9)

250

HESCK

External SCK High Period

(Note 9)

250

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 10, 12), LTC2415

1.64

1.67

1.70

Internal Oscillator (Notes 10, 12), LTC2415-1

1.80

1.83

1.86

External Oscillator (Notes 10, 11)

256/f

EOSC

(in kHz)

DOUT_ESCK

External SCK 32-Bit Data Output Time (Note 9)

32/f

ESCK

(in kHz)

to SDO Low Z

200

to SDO High Z

200

to SCK

(Note 10)

200

to SCK

(Note 9)

KQMAX

SCK

to SDO Valid

220

KQMIN

SDO Hold After SCK

(Note 5)

SCK Set-Up Before CS

SCK Hold After CS

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (Note 3)

TI I G CHARACTERISTICS

LTC2415/LTC2415-1

sn2415 24151fs

(V)

2.5 2 1.5 1 0.5 0

0.5

1.5

2.5

TUE (ppm OF V

REF

)

2415 G01

106.5

106.0

105.5

105.0

104.5

104.0

103.5

= 5V

REF

= 5V

INCM

= 2.5V

REF

= 5V

REF

= GND

= 90

= 25

= 45

(V)

1.25

0.75

0.25

0.75

1.25

TUE (ppm OF V

REF

)

2415 G02

215

213

211

209

207

205

= 5V

REF

= 2.5V

INCM

= 1.25V

REF

= 2.5V

REF

= GND

= 90

= 45

= 25

(V)

1.25

0.75

0.25

0.75

1.25

TUE (ppm OF V

REF

)

2415 G03

125

121

117

113

109

105

= 2.7V

REF

= 2.5V

INCM

= 1.25V

REF

= 2.5V

REF

= GND

= 45

= 25

= 90

(V)

2.5 2 1.5 1 0.5 0

0.5

1.5

2.5

INL ERROR (ppm OF V

REF

)

2415 G04

1.5

1.0

0.5

1.0

1.5

= 5V

REF

= 5V

INCM

= 2.5V

REF

= 5V

REF

= GND

= 25

= 45

= 90

(V)

1.25

0.75

0.25

0.75

1.25

INL ERROR (ppm OF V

REF

)

2415 G05

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

= 5V

REF

= 2.5V

INCM

= 1.25V

REF

= 2.5V

REF

= GND

= 45

= 25

= 90

(V)

1.25

0.75

0.25

0.75

1.25

INL ERROR (ppm OF V

REF

)

2415 G05

= 2.7V

REF

= 2.5V

INCM

= 1.25V

REF

= 2.5V

REF

= GND

= 90

= 45

= 25

OUTPUT CODE (ppm OF V

REF

)

105.5

104.8

104

103.3

102.5

NUMBER OF READINGS (%)

2415 G07

GAUSSIAN
DISTRIBUTION
m = 103.5ppm

= 0.27ppm

10,000 CONSECUTIVE
READINGS
V

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= GND

= 25

OUTPUT CODE (ppm OF V

REF

)

105

104.5

104

103.5

103

NUMBER OF READINGS (%)

2415 G08

10,000 CONSECUTIVE
READINGS
V

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= 460800Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 104.0ppm

= 0.25ppm

OUTPUT CODE (ppm OF V

REF

)

202

199.5

197

194.5

192

NUMBER OF READINGS (%)

2415 G09

10,000 CONSECUTIVE

READINGS

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= 1075200Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 199.0ppm

= 0.9ppm

Total Unadjusted Error Over
Temperature (V

= 5V,

REF

= 5V)

Total Unadjusted Error Over
Temperature (V

= 5V,

REF

= 2.5V)

Total Unadjusted Error Over
Temperature (V

= 2.7V,

REF

= 2.5V)

Integral Nonlinearity Over
Temperature (V

= 5V,

REF

= 5V)

Integral Nonlinearity Over
Temperature (V

= 5V,

REF

= 2.5V)

Integral Nonlinearity Over
Temperature (V

= 2.7V,

REF

= 2.5V)

Noise Histogram
(Output Rate = 15Hz,
V

= 5V, V

REF

= 5V)

Noise Histogram
(Output Rate = 45Hz,
V

= 5V, V

REF

= 5V)

Noise Histogram
(Output Rate = 105Hz,
V

= 5V, V

REF

= 5V)

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2415/LTC2415-1

sn2415 24151fs

OUTPUT CODE (ppm OF V

REF

)

212

210.5

209

207.5

206

NUMBER OF READINGS (%)

2415 G10

10,000 CONSECUTIVE
READINGS
V

= 5V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= GND

= 25

GAUSSIAN
DISTRIBUTION
m = 209.2ppm

= 0.56ppm

OUTPUT CODE (ppm OF V

REF

)

211.5

210.5

209.5

208.5

207.5

NUMBER OF READINGS (%)

2415 G11

10,000 CONSECUTIVE
READINGS
V

= 5V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= 460800Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 209.3ppm

= 0.49ppm

OUTPUT CODE (ppm OF V

REF

)

210

207

204

201

198

NUMBER OF READINGS (%)

2415 G12

10,000 CONSECUTIVE

READINGS

= 5V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= 1075200Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 206.5ppm

= 1.07ppm

OUTPUT CODE (ppm OF V

REF

)

116

114.5

113

111.5

110

NUMBER OF READINGS (%)

2415 G13

10,000 CONSECUTIVE
READINGS
V

= 2.7V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= GND

= 25

GAUSSIAN
DISTRIBUTION
m = 113.1ppm

= 0.59ppm

OUTPUT CODE (ppm OF V

REF

)

112

110.9

109.8

108.6

107.5

NUMBER OF READINGS (%)

2415 G14

10,000 CONSECUTIVE
READINGS
V

= 2.7V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= 460800Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 109.8ppm

= 0.50ppm

OUTPUT CODE (ppm OF V

REF

)

25.5

16.5

NUMBER OF READINGS (%)

2415 G15

10,000 CONSECUTIVE
READINGS
V

= 2.7V

REF

= 2.5V

= 0V

REF

= 2.5V

REF

= GND

= 1.25V

= 1075200Hz

= 25

GAUSSIAN
DISTRIBUTION
m = 20.5ppm

= 1.90ppm

OUTPUT CODE (ppm OF V

REF

)

103

103.5

104

104.5

105

NUMBER OF READINGS (%)

2415 G16

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= GND

= 25

GAUSSIAN
DISTRIBUTION
m = 103.9ppm

= 0.27ppm

TIME (HRS)

5 10 15 20 25 30 35 40 45 50 55 60

ADC READINGS (ppm OF V

REF

)

2415 G17

101.0

101.5

102.0

102.5

103.0

103.5

104.0

104.5

105.0

105.5

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= GND

= 25

INPUT DIFFERENTIAL VOLTAGE (V)

2.5 2 1.5 1 0.5 0

0.5

1.5

2.5

RMS NOISE (ppm OF V

REF

)

2415 G18

0.5

0.4

0.3

0.2

0.1

= 5V

REF

= 5V

INCM

= 2.5V

REF

= 5V

REF

= GND

= 25

Noise Histogram
(Output Rate = 15Hz,
V

= 5V, V

REF

= 2.5V)

Noise Histogram
(Output Rate = 45Hz,
V

= 5V, V

REF

= 2.5V)

Noise Histogram
(Output Rate = 105Hz,
V

= 5V, V

REF

= 2.5V)

Noise Histogram
(Output Rate = 15Hz,
V

= 2.7V, V

REF

= 2.5V)

Noise Histogram
(Output Rate = 45Hz,
V

= 2.7V, V

REF

= 2.5V)

Noise Histogram
(Output Rate = 105Hz,
V

= 2.7V, V

REF

= 2.5V)

Long-Term Histogram
(60Hrs)

Consecutive ADC Readings vs
Time

RMS Noise vs Input Differential
Voltage

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2415/LTC2415-1

sn2415 24151fs

TEMPERATURE (

100

RMS NOISE (nV)

2415 G20

1400

1250

1100

950

800

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= GND

(V)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

RMS NOISE (nV)

2415 G21

1560

1520

1480

1440

1400

1360

1320

1280

REF

= 2.5V

REF

= 2.5V

REF

= GND

= 25

REF

(V)

0.5

1.5

2.5

3.5

4.5

RMS NOISE (nV)

2415 G22

1600

1400

1200

1000

800

= 5V

REF

= GND

= 25

INCM

(V)

0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G23

103.0

103.4

103.8

104.2

104.6

105.0

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

= V

INCM

= V

INCM

= GND

= 25

TEMPERATURE (

100

OFFSET ERROR (ppm OF V

REF

)

2415 G24

103.8

104.0

104.2

104.4

104.6

= 5V

= 0V

REF

= 5V

REF

= GND

= 2.5V

= GND

(V)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G25

110

130

150

170

190

210

230

REF

= 2.5V

REF

= 2.5V

REF

= GND

= 25

AND V

REF

(V)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

OFFSET ERROR (ppm OF V

REF

)

2415 G26

103.2

103.6

104.0

104.4

104.8

105.2

REF

= GND

= 25

TEMPERATURE (

45 30 15

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G27

= 5V

REF

= 5V

REF

= GND

= 2.5V

= GND

TYPICAL PERFOR A CE CHARACTERISTICS

INCM

(V)

0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

RMS NOISE (nV)

2415 G19

1800

1600

1400

1200

1000

= V

INCM

= V

INCM

= GND

= 25

= 5V

REF

= 5V

= 0V

REF

= 5V

REF

= GND

RMS Noise vs V

INCM

RMS Noise vs Temperature (T

)

RMS Noise vs V

REF

Offset Error vs V

INCM

Offset Error vs Temperature (T

)

Offset Error vs V

and V

REF

+ Full-Scale Error vs
Temperature (T

)

LTC2415/LTC2415-1

sn2415 24151fs

TYPICAL PERFOR A CE CHARACTERISTICS

(V)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G28

REF

= 2.5V

REF

= 2.5V

REF

= GND

= 1.25V

= GND

= 25

REF

(V)

0.5

1.5

2.5

3.5

4.5

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G29

= 5V

REF

= V

REF

= GND

= 0.5 · REF

= GND

= 25

TEMPERATURE (

45 30 15

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G30

= 5V

REF

= 5V

REF

= GND

= 2.5V

= GND

(V)

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G31

REF

= 2.5V

REF

= 2.5V

REF

= GND

= 1.25V

= GND

= 25

REF

(V)

0.5

1.5

2.5

3.5

4.5

FULL-SCALE ERROR (ppm OF V

REF

)

2415 G32

= 5V

REF

= V

REF

= GND

= 0.5 · REF

= GND

= 25

FREQUENCY AT V

(Hz)

100

150

200

250

REJECTION (dB)

2415 G33

100

120

= 4.1V DC + 1.4V AC

REF

= 2.5V

REF

= GND

= IN

= GND

= 25

FREQUENCY AT V

(Hz)

100

10000

1000000

REJECTION (dB)

2415 G34

100

120

REF

= 2.5V

REF

= GND

= IN

= GND

= 25

FREQUENCY AT V

(Hz)

15200

15300

15400

15500

REJECTION (dB)

2415 G35

100

120

= 4.1V DC + 0.7V AC

REF

= 2.5V

REF

= GND

= IN

= GND

= 25

+Full-Scale Error vs V

REF

Full-Scale Error vs
Temperature (T

)

 Full-Scale Error vs V

REF

PSRR vs Frequency at V

TEMPERATURE (

45 30 15

SUPPLY CURRENT (

2415 G36

220

210

200

190

180

170

160

150

140

REF

= V

REF

= GND

= V

= GND

CS = GND
SCK = SDO = N/C

= 5.5V

= 4.1V

= 2.7V

Conversion Current vs
Temperature (T

)

LTC2415/LTC2415-1

sn2415 24151fs

GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and V

decoupling. Connect each one of these pins to a

ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.

(Pin 2): Positive Supply Voltage. Bypass to GND

(Pin 1) with a 10

F tantalum capacitor in parallel with

0.1

F ceramic capacitor as close to the part as possible.

REF

(Pin 3), REF

(Pin 4): Differential Reference Input.

The voltage on these pins can have any value between GND
and V

as long as the reference positive input, REF

, is

maintained more positive than the reference negative
input, REF

, by at least 0.1V.

(Pin 5), IN

(Pin 6): Differential Analog Input. The

voltage on these pins can have any value between
GND 0.3V and V

+ 0.3V. Within these limits the

converter bipolar input range (V

= IN

) extends

from 0.5 · (V

REF

) to 0.5 · (V

REF

). Outside this input range

the converter produces unique overrange and underrange
output codes.

CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.

SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V

) the SDO pin is in a

high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.

PI FU CTIO S

TYPICAL PERFOR A CE CHARACTERISTICS

OUTPUT DATA RATE (READINGS/SEC)

10 20 30 40 50 60 70 80 90 100

SUPPLY CURRENT (

2415 G37

1000

900

800

700

600

500

400

300

200

100

= 5V

REF

= 5V

REF

= GND

= EXT OSC

CS = GND
SCK =N/C
SDO = N/C

TEMPERATURE (

45 30 15

SUPPLY CURRENT (

2415 G38

REF

= V

REF

= GND

= V

= GND

CS = V

SCK = SDO = N/C

= 5.5V

= 4.1V

= 2.7V

Conversion Current vs Output
Data Rate

Sleep Current vs
Temperature (T

)

LTC2415/LTC2415-1

sn2415 24151fs

FU CTIO AL BLOCK DIAGRA

Figure 1. Functional Block Diagram

AUTOCALIBRATION

AND CONTROL

DAC

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

ADC

GND

SDO

SCK

REF

(INT/EXT)

2415 FD

(Pin 14): Frequency Control Pin. Digital input that

controls the ADC's notch frequencies and conversion
time. When the F

pin is connected to V

(LTC2415 only),

the converter uses its internal oscillator and the digital
filter first null is located at 50Hz. When the F

pin is

connected to GND (F

= OV), the converter uses its internal

oscillator and the digital filter first null is located at 60Hz
(LTC2415) or simultaneous 50Hz/60Hz (LTC2415-1).
When F

is driven by an external clock signal with a

frequency f

EOSC

, the converter uses this signal as its

system clock and the digital filter first null is located at a
frequency f

EOSC

/2560.

PI FU CTIO S

TEST CIRCUITS

1.69k

SDO

2415 TA03

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

1.69k

SDO

2415 TA04

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 2. LTC2415 State Transition Diagram

CONVERTER OPERATION

Converter Operation Cycle

The LTC2415/LTC2415-1 are low power, delta-sigma ana-
log-to-digital converters with an easy to use 3-wire serial
interface (see Figure 1). Their operation is made up of
three states. The converter operating cycle begins with the
conversion, followed by the sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock (SCK) and chip select
(CS).

is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.

Through timing control of the CS and SCK pins, the
LTC2415/LTC2415-1 offer several flexible modes of op-
eration (internal or external SCK and free-running conver-
sion modes). These various modes do not require pro-
gramming configuration registers; moreover, they do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2415/LTC2415-1 incorporate a
highly accurate on-chip oscillator. This eliminates the
need for external frequency setting components such as
crystals or oscillators. Clocked by the on-chip oscillator,
the LTC2415 achieves a minimum of 110dB rejection at
the line frequency (50Hz or 60Hz

2%), while the

LTC2415-1 achieves a minimum of 87db rejection at 50Hz

2% and 60Hz

2% simultaneously.

Ease of Use

The LTC2415/LTC2415-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.

CONVERT

SLEEP

DATA OUTPUT

2415 F02

TRUE

FALSE CS = LOW

AND

SCK

Initially, the LTC2415/LTC2415-1 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude if CS is HIGH. The part
remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.

Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

The LTC2415/LTC2415-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of full-scale readings with respect to time,
supply voltage change and temperature drift.

Unlike the LTC2410 and LTC2413, the LTC2415 and
LTC2415-1 do not perform an offset calibration every
conversion cycle. This enables the LTC2415/LTC2415-1
to double their output rate while maintaining line frequency
rejection. The initial offset of the LTC2415/LTC2415-1 is
within 2mV independent of V

REF

. Based on the LTC2415/

LTC2415-1 new modulator architecture, the temperature
drift of the offset is less then 0.01ppm/

C. More informa-

tion on the LTC2415/LTC2415-1 offset is described in the
Offset Accuracy and Drift section of this data sheet.

Power-Up Sequence

The LTC2415/LTC2415-1 automatically enter an internal
reset state when the power supply voltage V

drops

below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)

When the V

voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2415/LTC2415-1 start a normal conversion
cycle and follow the succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device if the power supply
voltage is restored within the operating range (2.7V to
5.5V) before the end of the POR time interval.

Reference Voltage Range

These converters accept a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF

and REF

pins covers the entire range

from GND to V

. For correct converter operation, the

REF

pin must always be more positive than the REF

pin.

The LTC2415/LTC2415-1 can accept a differential refer-
ence voltage from 0.1V to V

. The converter output noise

is determined by the thermal noise of the front-end cir-
cuits, and as such, its value in nanovolts is nearly constant
with reference voltage. A decrease in reference voltage will
not significantly improve the converter's effective resolu-
tion. On the other hand, a reduced reference voltage will
improve the converter's overall INL performance. A re-
duced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external F

signal) at substantially higher output

data rates (see the Output Data Rate section).

Input Voltage Range

The analog input is truly differential with an absolute/
common mode range for the IN

and IN

input pins

extending from GND 0.3V to V

+ 0.3V. Outside

these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2415/LTC2415-1 con-
vert the bipolar differential input signal, V

= IN

from FS = 0.5 · V

REF

to +FS = 0.5 · V

REF

where V

REF

. Outside this range, the converters indicate

the overrange or the underrange condition using distinct
output codes.

Input signals applied to IN

and IN

pins may extend by

300mV below ground and above V

. In order to limit any

fault current, resistors of up to 5k may be added in series
with the IN

and IN

pins without affecting the perfor-

mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. The effect of the
series resistance on the converter accuracy can be evalu-
ated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if V

REF

= 5V.

This error has a very strong temperature dependency.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Output Data Format

The LTC2415/LTC2415-1 serial output data stream is 32
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 24 bits
are the conversion result, MSB first. The remaining 5 bits
are sub LSBs beyond the 24-bit level that may be included
in averaging or discarded without loss of resolution. The
third and fourth bit together are also used to indicate an
underrange condition (the differential input voltage is
below FS) or an overrange condition (the differential
input voltage is above +FS).

Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.

Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V

is >0, this bit is HIGH. If V

is <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2415/LTC2415-1 Status Bits

Bit 31

Bit 30 Bit 29 Bit 28

Input Range

EOC

DMY

SIG

MSB

0.5 · V

REF

< 0.5 · V

REF

0.5 · V

REF

< 0V

< 0.5 · V

REF

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.

Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.

In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.

As long as the voltage on the IN

and IN

pins is maintained

within the 0.3V to (V

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any
differential input voltage V

from FS = 0.5 · V

REF

+FS = 0.5 · V

REF

. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below FS, the conversion result is clamped to the value
corresponding to FS 1LSB.

Offset Accuracy and Drift

Unlike the LTC2410/LTC2413 and the entire LTC2400 fam-
ily, the LTC2415/LTC2415-1 do not perform an offset
calibration every cycle. The reason for this is to increase the
data output rate while maintaining line frequency rejection.

While the initial accuracy of the LTC2415/LTC2415-1
offset is within 2mV (see Figure 4) several unique proper-
ties of the LTC2415/LTC2415-1 architecture nearly elimi-
nate the drift of the offset error with respect to temperature
and supply.

As shown in Figure 5, the offset variation with temperature
is less than 0.6ppm over the complete temperature range
of 50

C to 100

C. This corresponds to a temperature drift

of 0.004ppm/

LTC2415/LTC2415-1

sn2415 24151fs

Table 2. LTC2415/LTC2415-1 Output Data Format

Differential Input Voltage

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

...

Bit 0

EOC

DMY

SIG

MSB

0.5 · V

REF

...

0.5 · V

REF

** 1LSB

...

0.25 · V

REF

...

0.25 · V

REF

** 1LSB

...

1LSB

...

0.25 · V

REF

...

0.25 · V

REF

** 1LSB

...

0.5 · V

REF

...

* < 0.5 · V

REF

...

*The differential input voltage V

= IN

**The differential reference voltage V

REF

= REF

REF

Figure 3. Output Data Timing

APPLICATIO S I FOR ATIO

MSB

SIG

"0"

BIT 0

BIT 27

BIT 5

LSB

BIT 28

BIT 29

BIT 30

SDO

SCK

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2415 F03

Hi-Z

(V)

2.5

OFFSET (ppm)

100

150

200

250

3.0

3.5

4.0

4.5

2415 F04

5.0

5.5

REF

= 2.5V

= 25

PART NO.1

PART NO.2

PART NO.3

TEMPERATURE (

OFFSET ERROR (ppm OF V

REF

)

103.8

104.0

104.2

104.4

104.6

2415 F05

100

AND V

REF

(V)

2.7

OFFSET ERROR (ppm OF V

REF

)

103.0

103.5

104.0

104.5

105.0

105.5

3.5

4.3

4.7

2415 F06

3.1

3.9

5.1

5.5

= 5V

REF

= 5V

REF

= 5V

REF

= GND

= 0V

= GND

=100

= 50

=25

Figure 4. Offset vs V

Figure 5. Offset vs Temperature

Figure 6. Offset vs V

REF

= V

)

While the variation in offset with supply voltage is propor-
tional to V

(see Figure 4), several characteristics of this

variation can be used to eliminate the effects. First, the
variation with respect to supply voltage is linear. Second,
the magnitude of the offset error decreases with de-
creased supply voltage. Third, the offset error increases

with increased reference voltage with an equal and oppo-
site magnitude to the supply voltage variation. As a result,
by tying V

to V

REF

, the variation with supply can be

nearly eliminated, see Figure 6. The variation with supply
is less than 2ppm over the entire 2.7V to 5.5V supply
range.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Frequency Rejection Selection LTC2415 (F

)

The LTC2415 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and its harmon-
ics for 50Hz

2% or 60Hz

2%. For 60Hz rejection, F

should be connected to GND while for 50Hz rejection the F

pin should be connected to V

The selection of 50Hz or 60Hz rejection can also be made by
driving F

to an appropriate logic level. A selection change

during the sleep or data output states will not disturb the
converter operation. If the selection is made during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected.

When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2415 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F

pin and turns off the internal oscillator. The

frequency f

EOSC

of the external signal must be at least

2560Hz (1Hz notch frequency) to be detected. The external
clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and low
periods t

HEO

and t

LEO

are observed.

While operating with an external conversion clock of a
frequency f

EOSC

, the LTC2415 provides better than 110dB

normal mode rejection in a frequency range f

EOSC

/2560

4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from f

EOSC

/2560

is shown in Figure 7a.

Whenever an external clock is not present at the F

pin, the

converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2415
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external serial
clock. If the change occurs during the conversion state, the
result of the conversion in progress may be outside speci-
fications but the following conversions will not be affected.
If the change occurs during the data output state and the
converter is in the Internal SCK mode, the serial clock duty
cycle may be affected but the serial data stream will remain
valid.

Table 3a summarizes the duration of each state and the
achievable output data rate as a function of F

Frequency Rejection Selection LTC2415-1 (F

)

The LTC2415-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz as shown in Figure 7b. For simultaneous 50Hz/60Hz
rejection, F

should be connected to GND.

In order to achieve 87dB normal mode rejection of 50Hz

2% and 60Hz

2%, two consecutive conversions must be

averaged. By performing a continuous running average of
the two most current results, both simultaneous rejection
is achieved and a 2

increase in throughput is realized

relative to the LTC2413 (see Normal Mode Rejection, Ouput
Rate and Running Averages sections of this data sheet).

When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be synchronized with an outside source, the
LTC2415-1 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F

pin and turns off the internal

oscillator. The frequency f

EOSC

of the external signal must

be at least 2560Hz to be detected. The external clock signal
duty cycle is not significant as long as the minimum and
maximum specifications for the high and low periods, t

HEO

and t

LEO

, are observed.

While operating with an external conversion clock of a
frequency f

EOSC

, the LTC2415-1 provides better than

110dB normal mode rejection in a frequency range f

EOSC

2560

4%. The normal mode rejection as a function of the

input frequency deviation from f

EOSC

/2560 is shown in

Figure 7a and Figure 7c shows the normal mode rejection
with running averages included.

Whenever an external clock is not present at the F

pin the

converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2415-1
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Table 3a. LTC2415 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

= LOW, (60Hz Rejection)

66.6ms, Output Data Rate

15 Readings/s

= HIGH, (50Hz Rejection)

80ms, Output Data Rate

12.4 Readings/s

External Oscillator

= External Oscillator with Frequency 10278/f

EOSC

s, Output Data Rate

EOSC

/10278 Readings/s

EOSC

kHz (f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock F

= LOW/HIGH, (Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.67ms (32 SCK cycles)

= External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

EOSC

ms (32 SCK cycles)

Frequency f

EOSC

kHz

External Serial Clock with Frequency f

SCK

kHz

As Long As CS = LOW But Not Longer Than 32/f

SCK

ms (32 SCK cycles)

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

REJECTION (dB)

2415 F07a

100

110

120

130

140

Table 3b. LTC2415-1 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

= LOW

72.8ms, Output Data Rate

14 Readings/s

Simultaneous 50Hz/60Hz Rejection

External Oscillator

= External Oscillator with Frequency 10278/f

EOSC

s, Output Data Rate

EOSC

/10278 Readings/s

EOSC

kHz (f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock F

= LOW (Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.83ms (32 SCK cycles)

= External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

EOSC

ms (32 SCK cycles)

Frequency f

EOSC

kHz

External Serial Clock with Frequency f

SCK

kHz

As Long As CS = LOW But Not Longer Than 32/f

SCK

ms (32 SCK cycles)

Figure 7c. LTC2415/LTC2415-1
Normal Mode Rejection When Using
an External Oscillator of Frequency
f

EOSC

with Running Averages

Figure 7b. LTC2415-1 Normal Mode
Rejection When Using an Internal
Oscillator with Running Averages

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

NORMAL MODE REECTION RATIO (dB)

2415 F07b

100

120

130

140

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

EOSC

/2560(%)

NORMAL MODE REJECTION (dB)

2415 F07c

100

105

110

115

120

125

130

135

140

Figure 7a. LTC2415/LTC2415-1 Normal Mode
Rejection When Using an External Oscillator
of Frequency f

EOSC

without Running Averages

state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.

Table 3b summarizes the duration of each state and the
achievable output data rate as a function of F

Serial Interface Pins

The LTC2415/LTC2415-1 transmit the conversion results
and receive the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.

LTC2415/LTC2415-1

sn2415 24151fs

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2415/LTC2415-1 create their own se-
rial clock by dividing the internal conversion clock by 8. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversion status and to enable the data output transfer as
described in the previous sections.

In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2415/LTC2415-1 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).

Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F

. Tying a

capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor's
value, see Figures 15 to 17.

SERIAL INTERFACE TIMING MODES

The LTC2415/LTC2415-1 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (F

LOW or F

= HIGH) or an external oscillator connected to

the F

pin. Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.

Table 4. LTC2415/LTC2415-1 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 8, 9

External SCK, 2-Wire I/O

External

SCK

Figure 10

Internal SCK, Single Cycle Conversion

Internal

Figures 11, 12

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 13

Internal SCK, Autostart Conversion

Internal

EXT

Internal

Figure 14

APPLICATIO S I FOR ATIO

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 8. External Serial Clock, Single Cycle Operation

EOC

BIT 31

SDO

SCK

(EXTERNAL)

TEST EOC

SUB LSB

MSB

SIG

BIT 0

LSB

BIT 5

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

2415 F08

CONVERSION

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

Hi-Z

TEST EOC

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

2.7V TO 5.5V

LTC2415/

LTC2415-1

3-WIRE
SPI INTERFACE

The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the sleep state once the con-
version is complete. While in the sleep state, if CS is high,
the LTC2415/LTC2415-1 power consumption is reduced
by an order of magnitude

When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen while CS is LOW. Data is shifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 9. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 10. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.

The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V

exceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 9. External Serial Clock, Reduced Data Output Length

SDO

SCK

(EXTERNAL)

DATA OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

2415 F09

MSB

SIG

BIT 8

BIT 27

BIT 9

BIT 28

BIT 29

BIT 30

EOC

BIT 31

BIT 0

EOC

Hi-Z

TEST EOC

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

3-WIRE
SPI INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion enters the sleep state. On the
falling edge of EOC, the conversion result is loaded into an
internal static shift register. The device remains in the
sleep state until the first rising edge of SCK. Data is shifted
out the SDO pin on each falling edge of SCK enabling
external circuitry to latch data on the rising edge of SCK.
EOC can be latched on the first rising edge of SCK. On the
32nd falling edge of SCK, SDO goes HIGH (EOC = 1)
indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.

When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the sleep state, CS must be pulled HIGH
before the first rising edge of SCK. In the internal SCK
timing mode, SCK goes HIGH and the device begins
outputting data at time t

EOCtest

after the falling edge of CS

(if EOC = 0) or t

EOCtest

after EOC goes LOW (if CS is LOW

during the falling edge of EOC). The value of t

EOCtest

is 23

(LTC2415), 26

s (LTC2415-1) if the device is using its

internal oscillator (F

= logic LOW or HIGH). If F

is driven

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)

Figure 11. Internal Serial Clock, Single Cycle Operation

EOC

BIT 31

SDO

SCK

(EXTERNAL)

MSB

SIG

BIT 0

LSB

BIT 5

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

2415 F10

CONVERSION

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

2-WIRE
INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

SDO

SCK

(INTERNAL)

MSB

SIG

BIT 0

LSB

BIT 5

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2415 F11

EOCtest

10k

Hi-Z

TEST EOC

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

3-WIRE
SPI INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

LTC2415/LTC2415-1

sn2415 24151fs

new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2415/LTC2415-1 internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2415/LTC2415-1 internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CS, the device is switched to the external
SCK timing mode. By adding an external 10k pull-up
resistor to SCK, this pin goes HIGH once the external driver
goes Hi-Z. On the next CS falling edge, the device will
remain in the internal SCK timing mode.

APPLICATIO S I FOR ATIO

Figure 12. Internal Serial Clock, Reduced Data Output Length

SDO

SCK

(INTERNAL)

> t

EOCtest

MSB

SIG

BIT 8

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA OUTPUT

CONVERSION

SLEEP

2415 F12

EOCtest

10k

TEST EOC

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

3-WIRE
SPI INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

by an external oscillator of (LTC2415-1) frequency f

EOSC

then t

EOCtest

is 3.6/f

EOSC

. If CS is pulled HIGH before time

EOCtest

, the device remains in the sleep state. The conver-

sion result is held in the internal static shift register.

If CS remains LOW longer than t

EOCtest

, the first rising

edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 12. On the rising edge of CS, the device
aborts the data output state and immediately initiates a

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 13. Internal Serial Clock, Continuous Operation

SDO

SCK

(INTERNAL)

LSB

MSB

SIG

BIT 5

BIT 0

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2415 F13

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

2-WIRE
INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t

EOCtest

), the internal pull-up is activated.

For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 2-Wire I/O,
Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V

exceeds 2.2V. An internal

weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).

During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 14. Internal Serial Clock, Autostart Operation

SDO

Hi-Z

SCK

(INTERNAL)

GND

2415 F14

BIT 0

SIG

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

EOC

BIT 31

REF

SCK

SDO

GND

1, 7, 8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

0.5V

REF

TO 0.5V

REF

2-WIRE
INTERFACE

2.7V TO 5.5V

LTC2415/

LTC2415-1

EXT

= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)

Internal Serial Clock, Autostart Conversion

This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.

While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 14. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 15 and 16. Once the
voltage at CS falls below an internal threshold (

1.4V), the

device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 17 shows the average supply current as a function
of capacitance on CS.

It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode, the analog voltage on the CS pin cannot be ob-
served without disturbing the converter operation using a
regular oscilloscope probe. When using this configura-
tion, it is important to minimize the external leakage
current at the CS pin by using a low leakage external
capacitor and properly cleaning the PCB surface.

The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 15. CS Capacitance vs t

SAMPLE

Figure 16. CS Capacitance vs Output Rate

Figure 17. CS Capacitance vs Supply Current

CAPACITANCE ON CS (pF)

1000

10000

2415 F15

100

100000

SAMPLE

(SEC)

= 5V

= 3V

CAPACITANCE ON CS (pF)

SAMPLE RATE (Hz)

1000

100000

2415 F16

100

10000

= 5V

= 3V

CAPACITANCE ON CS (pF)

SUPPLY CURRENT (

RMS

)

100

150

200

250

300

100

1000

10000

2415 F17

100000

= 5V

= 3V

66.6ms and the conversion time of the LTC2413 is 146ms,
while the LTC2415-1 is 73ms. In systems where the SDO
pin is monitored for the end-of-conversion signal (SDO
goes low once the conversion is complete) these two
devices can be interchanged. In cases where SDO is not
monitored, a wait state is inserted between conversions,
the duration of this wait state must be greater than 66.6ms
for the LTC2415, greater than 133ms for the LTC2410,
greater than 146ms for the LTC2413 and greater than
73ms for the LTC2415-1.

PRESERVING THE CONVERTER ACCURACY

The LTC2415/LTC2415-1 are designed to reduce as much
as possible conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-
quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.

Digital Signal Levels

The LTC2415/LTC2415-1 digital interface is easy to use.
Its digital inputs (F

, CS and SCK in External SCK mode of

operation) accept standard TTL/CMOS logic levels and the
internal hysteresis receivers can tolerate edge rates as slow
as 100

s. However, some considerations are required to

take advantage of the exceptional accuracy and low supply
current of this converter.

The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during conversion.

While a digital input signal is in the range 0.5V to
(V

0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,
when any one of the digital input signals (F

, CS and SCK

in External SCK mode of operation) is within this range, the
LTC2415/LTC2415-1 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [V

< 0.4V and

> (V

0.4V)].

During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2415/

Timing Compatibility with the LTC2410/LTC2413

All timing modes described above are identical with re-
spect to the LTC2410/LTC2413 and LTC2415/LTC2415-1,
with one exception. The conversion time of the LTC2410
is 133ms while the conversion time of the LTC2415 is

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

LTC2415-1 pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can oc-
cur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2415/LTC2415-1. For reference, on a regular FR-4
board, signal propagation velocity is approximately
183ps/inch for internal traces and 170ps/inch for surface
traces. Thus, a driver generating a control signal with a
minimum transition time of 1ns must be connected to the
converter pin through a trace shorter than 2.5 inches. This
problem becomes particularly difficult when shared con-
trol lines are used and multiple reflections may occur. The
solution is to carefully terminate all transmission lines
close to their characteristic impedance.

Parallel termination near the LTC2415/LTC2415-1 pins
will eliminate this problem but will increase the driver
power dissipation. A series resistor between 27

and 56

placed near the driver or near the LTC2415/LTC2415-1
pins will also eliminate this problem without additional
power dissipation. The actual resistor value depends upon
the trace impedance and connection topology.

An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter's sensitivity to ground currents.

Particular attention must be given to the connection of the
F

signal when the LTC2415/LTC2415-1 are used with an

external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this fre-
quency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F

signal trace and the converter

input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F

signal trace and the input/reference sig-

nals. When the F

signal is parallel terminated near the

converter, substantial AC current is flowing in the loop
formed by the F

connection trace, the termination and the

ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F

signal as well as the loop area for

the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the LTC2415/LTC2415-1
converters are directly connected to a network of sampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 18.

For a simple approximation, the source impedance R

driving an analog input pin (IN

, IN

, REF

or REF

) can be

considered to form, together with R

and C

(see

Figure 18), a first order passive network with a time
constant

= (R

+ R

) · C

. The converter is able to

sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant

. The sampling process on the

four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.

When using the internal oscillator (F

= LOW or HIGH), the

LTC2415's front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13

s sampling period and

the LTC2415-1's front end is clocked at 69900Hz corre-
sponding to 14.2

s. Thus, for settling errors of less than

1ppm, the driving source impedance should be chosen
such that

s/14 = 920ns (LTC2415) and

<14.2

14 = 1.01

s (LTC2415-1).. When an external oscillator of

frequency f

EOSC

is used, the sampling period is 2/f

EOSC

and, for a settling error of less than 1ppm,

0.14/f

EOSC

Input Current

If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit

Figure 19. An RC Network at IN

and IN

Figure 21. FS Error vs R

SOURCE

at IN

or IN

(Small C

)

Figure 20. +FS Error vs R

SOURCE

at IN

or IN

(Small C

)

I IN

I REF

where

AVG

INCM

REFCM

AVG

INCM

REFCM

AVG

REF

INCM

REFCM

REF

AVG

REF

INCM

REFCM

REF

( )

= -

( )

= -

0 5

1 5

0 5

1 5

0 5

:
:

REF

INTERNAL OSCILLATOR

Hz Notch F

LOW

INTERNAL OSCILLATOR

Hz Notch F

HIGH

EXTERNAL OSCILLATOR

REF

REFCM

INCM

EOSC

(

)

(

)

(

)

3 61

4 32

0 555 10

3 97

LTC2415

INTERNAL OSCILLATOR

Hz Notch F

LOW

(

)

LTC2415 -1

2415 F19

INCM

+ 0.5V

SOURCE

LTC2415/

LTC2415-1

PAR

20pF

INCM

0.5V

SOURCE

PAR

20pF

SOURCE

(

)

100

10k

100k

+FS ERROR (ppm OF V

REF

)

2415 F20

= 5V

REF

= 5V

REF

= GND

= 5V

= 2.5V

= GND

= 25

= 0.01

= 0.001

= 100pF

= 0pF

SOURCE

(

)

100

10k

100k

FS ERROR (ppm OF V

REF

)

2415 F21

= 5V

REF

= 5V

REF

= GND

= 2.5V

= GND

= 25

= 0.01

= 0.001

= 100pF

= 0pF

REF

(TYP)

20k

LEAK

(TYP)

20k

18pF
(TYP)

(TYP)

20k

LEAK

REF

2415 F18

LEAK

SWITCHING FREQUENCY
f

= 76800Hz INTERNAL

OSCILLATOR (LTC2415)
(F

= LOW OR HIGH)

= 69900Hz INTERNAL

OSCILLATOR (LTC2415-1)
(F

= LOW)

= 0.5 · f

EOSC

EXTERNAL OSCILLATOR

REF

(TYP)

20k

incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 18 shows the
mathematical expressions for the average bias currents
flowing through the IN

and IN

pins as a result of the

sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed
using the test circuit of Figure 19. The C

PAR

capacitor

includes the LTC2415/LTC2415-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 20 and 21. A careful
implementation can bring the total input capacitance (C

+ C

PAR

) closer to 5pF thus achieving better performance

than the one predicted by Figures 20 and 21. For simplic-
ity, two distinct situations can be considered.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

For relatively small values of input capacitance (C

0.01

F), the voltage on the sampling capacitor settles

almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C

will deteriorate the converter offset and gain

performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C

are unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the
LTC2415/LTC2415-1 can maintain their exceptional accu-
racy while operating with relative large values of source
resistance as shown in Figures 20 and 21. These mea-
sured results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small C

values, the settling on IN

and IN

occurs

almost independently and there is little benefit in trying to
match the source impedance for the two pins.

Larger values of input capacitors (C

> 0.01

F) may be

required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F

= LOW (internal oscillator and 60Hz notch), the

typical differential input resistance is 1.8M

(LTC2415),

1.97M

(LTC2415-1) which will generate a gain error of

approximately 0.28ppm for each ohm of source resis-
tance driving IN

or IN

. For the LTC2415, when F

= HIGH

(internal oscillator and 50Hz notch), the typical differential
input resistance is 2.16M

which will generate a gain

error of approximately 0.23ppm for each ohm of source
resistance driving IN

or IN

. When F

is driven by an

external oscillator with a frequency f

EOSC

(external conver-

sion clock operation), the typical differential input resis-
tance is 0.28 · 10

EOSC

and each ohm of

source resistance driving IN

or IN

will result in

1.78 · 10

· f

EOSC

ppm gain error. The effect of the source

resistance on the two input pins is additive with respect to
this gain error. The typical +FS and FS errors as a function
of the sum of the source resistance seen by IN

and IN

for

large values of C

are shown in Figures 22 and 23.

In addition to this gain error, an offset error term may also
appear. The offset error is proportional to the mismatch
between the source impedance driving the two input pins
IN

and IN

and with the difference between the input and

reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C

capacitor

values, it is advisable to carefully match the source imped-
ance seen by the IN

and IN

pins. When F

= LOW

(internal oscillator and 60Hz notch), every 1

mismatch

in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F

= HIGH (internal oscillator and 50Hz

notch), every 1

mismatch in source impedance trans-

forms a full-scale common mode input signal into a
differential mode input signal of 0.23ppm. When F

driven by an external oscillator with a frequency f

EOSC

every 1

mismatch in source impedance transforms a

full-scale common mode input signal into a differential
mode input signal of 1.78 · 10

· f

EOSC

ppm. Figure 24

shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN

and IN

pins when large C

values are

used.

If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.

The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/

C) are

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 22. +FS Error vs R

SOURCE

at IN

or IN

(Large C

)

Figure 23. FS Error vs R

SOURCE

at IN

or IN

(Large C

)

Figure 24. Offset Error vs Common Mode Voltage
(V

INCM

= IN

) and Input Source Resistance Imbalance

(

= R

SOURCEIN

+ R

SOURCEIN

) for Large C

Values (C

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

+FS ERROR (ppm OF V

REF

)

2415 F22

300

240

180

120

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

= 0.01

= 0.1

= 1

F, 10

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2415 F23

120

180

240

300

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

= 0.01

= 0.1

= 1

F, 10

INCM

(V)

0.5

1.5

2.5

3.5

4.5

OFFSET ERROR (ppm OF V

REF

)

2415 F24

120

100

120

= GND

= 25

SOURCEIN

= 500

= 10

= 5V

REF

= 5V

REF

= GND

= IN

= V

INCM

= +400

= +200

= +100

= 0

= 100

= 200

= 400

used for the external source impedance seen by IN

and

, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (

10nA max), results

in a small offset shift. A 100

source resistance will create

a 0.1

V typical and 1

V maximum offset voltage.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 25. +FS Error vs R

SOURCE

at REF

or REF

(Small C

)

Figure 26. FS Error vs R

SOURCE

at REF

or REF

(Small C

)

Figure 27. +FS Error vs R

SOURCE

at REF

and REF

(Large C

REF

)

Figure 28. FS Error vs R

SOURCE

at REF

and REF

(Large C

REF

)

SOURCE

(

)

100

10k

100k

+FS ERROR (ppm OF V

REF

)

2415 F25

= 5V

REF

= 5V

REF

= GND

= 5V

= 2.5V

= GND

= 25

REF

= 0.01

REF

= 0.001

REF

= 100pF

REF

= 0pF

SOURCE

(

)

100

10k

100k

FS ERROR (ppm OF V

REF

)

2415 F26

= 5V

REF

= 5V

REF

= GND

= 2.5V

= GND

= 25

REF

= 0.01

REF

= 0.001

REF

= 100pF

REF

= 0pF

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2415 F27

180

270

360

450

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

REF

= 0.01

REF

= 0.1

REF

= 1

F, 10

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2415 F28

450

360

270

180

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

REF

= 0.01

REF

= 0.1

REF

= 1

F, 10

Reference Current

In a similar fashion, the LTC2415/LTC2415-1 sample the
differential reference pins REF

and REF

transferring

small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situa-
tions.

For relatively small values of the external reference capaci-
tors (C

REF

< 0.01

F), the voltage on the sampling capacitor

settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C

REF

will deteriorate the converter offset and

gain performance without significant benefits of reference

filtering and the user is advised to avoid them.

Larger values of reference capacitors (C

REF

> 0.01

F) may

be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. For the LTC2415,
when F

= LOW (internal oscillator and 60Hz notch), the

typical differential reference resistance is 1.3M

which

will generate a gain error of approximately 0.38ppm for
each ohm of source resistance driving REF

or REF

When F

= HIGH (internal oscillator and 50Hz notch), the

typical differential reference resistance is 1.56M

which

will generate a gain error of approximately 0.32ppm for
each ohm of source resistance driving REF

or REF

. For

the LTC2415-1, the typical differential reference resis-

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 29. INL vs Differential Input Voltage (V

= IN

 IN

) and Reference

Source Resistance (R

SOURCE

at REF

and REF

for Large C

REF

Values (C

REF

INDIF

REFDIF

0.5 0.40.30.20.1 0

0.1 0.2 0.3 0.4 0.5

INL (ppm OF V

REF

)

= 5V

REF+ = 5V
REF = GND
V

INCM

= 0.5 · (IN

+ IN

) = 2.5V

= GND

REF

= 10

= 25

SOURCE

= 1000

SOURCE

= 500

SOURCE

= 100

2415 F29

tance is 1.43M

. When F

is driven by an external

oscillator with a frequency f

EOSC

(external conversion

clock operation), the typical differential reference resis-
tance is 0.20 · 10

EOSC

and each ohm of source

resistance driving REF

or REF

will result in

2.47 · 10

· f

EOSC

ppm gain error. The effect of the source

resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and FS errors
for various combinations of source resistance seen by the
REF

and REF

pins and external capacitance C

REF

connected to these pins are shown in Figures 25, 26, 27
and 28.

In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F

= LOW (internal oscillator and 60Hz notch), every

100

of source resistance driving REF

or REF

translates

into about 1.34ppm additional INL error. For the LTC2415,
when F

= HIGH (internal oscillator and 50Hz notch), every

100

of source resistance driving REF

or REF

translates

into about 1.1ppm additional INL error; and for the
LTC2415-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100

of source resistance leads to an

additional 1.22ppm of additional INL error. When F

driven by an external oscillator with a frequency f

EOSC

every 100

of source resistance driving REF

or REF

translates into about 8.73 · 10

· f

EOSC

ppm additional INL

error. Figure 26 shows the typical INL error due to the
source resistance driving the REF

or REF

pins when

large C

REF

values are used. The effect of the source

resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF

and REF

pins does not help the

gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF

and

REF

pins rather than to try to match it.

The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/

C) are used for the external source impedance

seen by REF

and REF

, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.

In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(

10nA max), results in a small gain error. A 100

source

resistance will create a 0.05

V typical and 0.5

V maxi-

mum full-scale error.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

FREQUENCY AT V

(Hz)

120

REJECTION (dB)

100

150

200

2415 F30

250

= 5V

REF

= 5V

= 2.5V

= 0

INPUT FREQUENCY

2415 F31

100

120

140

REJECTION (dB)

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

REJECTION (dB)

2415 F32

100

110

120

130

140

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

NORMAL MODE REECTION RATIO (dB)

2415 F33

100

120

130

140

INPUT FREQUENCY (Hz)

100

120

140

160

180

200

220

NORMAL MODE REJECTION (dB)

2415 F34

100

120

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

IN(P-P)

= 5V

= 25

MEASURED DATA
CALCULATED DATA

Figure 34. Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 100% of Full Scale

Figure 30. Rejection vs Frequency at V

Figure 31. Rejection vs Frequency at V

Figure 32. Rejection vs Frequency at V

Figure 33. Normal Mode Rejection
when Using an Internal Oscillator

Normal Mode Rejection, Output Rate and Running
Averages

The LTC2415/LTC2415-1 both contain an identical Sinc

digital filter (see Figures 30 and 31) which offers excellent
line frequency noise rejection. For the LTC2415, a notch
frequency of either 50Hz or 60Hz (see Figure 32) is user
selectable by tying pin F

high or Low, respectively. On the

other hand, the LTC2415-1 offers simultaneous rejection
of 50Hz and 60Hz by tying F

low. This sets the notch

frequency to approximately 55Hz (see Figure 32).

At a notch frequency of 55Hz, the LTC2415-1 rejects 50Hz

2% and 60Hz

2% better than 72dB. In order to achieve

better than 87dB rejection of both 50Hz and 60Hz

2%, a

running average can be performed. By averaging two
consecutive ADC readings, a Sinc

notch is combined with

the Sinc

digital filter yielding the frequency response

shown in Figures 33 and 34. In order to preserve the 2

output rate, adjacent results are averaged with the follow-
ing algorithm:

Result 1 = average (sample 0, sample 1)

Result 2 = average (sample 1, sample 2)

Result 3 = average (sample 2, sample 3)

...

Result N = average (sample n-1, sample n)

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Figure 36. Connecting the LTC2415/LTC2415-1 to a 68HC11 MCU Using the SPI Serial Interface

2415 F35

REF

1, 7, 8, 9,
10, 15, 16

A0
A1

LTC2415/

LTC2415-1

GND

TO OTHER

DEVICES

74HC4052

Figure 35. Use a Differential Multiplexer to Expand Channel Capability

LTC2415/

LTC2415-1

SCK

SDO

SCK (PD4)

MISO (PD2)

SS (PD5)

68HC11

2415 F36

Sample Driver for LTC2415/LTC2415-1 SPI Interface

Figure 35 shows the use of an LTC2415/LTC2415-1 with
a differential multiplexer. This is an inexpensive multi-
plexer that will contribute some error due to leakage if
used directly with the output from the bridge, or if
resistors are inserted as a protection mechanism from
overvoltage. Although the bridge output may be within the
input range of the A/D and multiplexer in normal opera-
tion, some thought should be given to fault conditions
that could result in full excitation voltage at the inputs to
the multiplexer or ADC. The use of amplification prior to
the multiplexer will largely eliminate errors associated
with channel leakage developing error voltages in the
source impedance.

The LTC2415/LTC2415-1 have a very simple serial inter-
face that makes interfacing to microprocessors and
microcontrollers very easy.

The listing in Figure 38 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring
it for SPI data transfer between the controller and the
LTC2415/LTC2415-1. Figure 36 shows the simple 3-wire
SPI connection.

The code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result.
This is followed by initializing PORT D's SPI configuration.
The program then enters the main sequence. It activates
the LTC2415/LTC2415-1 serial interface by setting the SS
output low, sending a logic low to CS. It next waits in a loop
for a logic low on the data line, signifying end-of-conver-
sion. After the loop is satisfied, four SPI transfers are
completed, retrieving the conversion. The main sequence
ends by setting SS high. This places the LTC2415/
LTC2415-1 serial interface in a high impedance state and
initiates another conversion.

The performance of the LTC2415/LTC2415-1 can be
verified using the demonstration board DC291A, see
Figure 40 for the schematic. This circuit uses the
computer's serial port to generate power and the SPI
digital signals necessary for starting a conversion and
reading the result. It includes a Labview application
software program (see Figure 39) which graphically cap-
tures the conversion results. It can be used to determine
noise performance, stability and with an external source,
linearity. As exemplified in the schematic, the LTC2415/
LTC2415-1 are extremely easy to use. This demonstra-
tion board and associated software is available by con-
tacting Linear Technology.

LTC2415/LTC2415-1

sn2415 24151fs

APPLICATIO S I FOR ATIO

Correlated Double Sampling with the
LTC2415/LTC2415-1

Figure 37 shows the LTC2415/LTC2415-1 in a correlated
double sampling circuit that achieves a noise floor of
under 100nV. In this scheme, the polarity of the bridge is
alternated every other sample and the result is the average
of a pair of samples of opposite sign. This technique has
the benefit of canceling any fixed DC error components in
the bridge, amplifiers and the converter, as these will
alternate in polarity relative to the signal. Offset voltages
and currents, thermocouple voltages at junctions of dis-
similar metals and the lower frequency components of 1/f
noise are virtually eliminated.

The LTC2415/LTC2415-1 have the virtue of being able to
digitize an input voltage that is outside the range defined
by the reference, thereby providing a simple means to
implement a ratiometric example of correlated double
sampling.

This circuit uses a bipolar amplifier (LT1219--U1 and U2)
that has neither the lowest noise nor the highest gain. It
does, however, have an output stage that can effectively
suppress the conversion spikes from the LTC2415/
LTC2415-1. The LT1219 is a C-Load

stable amplifier

that, by design, needs at least 0.1

F output capacitance to

remain stable. The 0.1

F ceramic capacitors at the out-

puts (C1 and C2) should be placed and routed to minimize
lead inductance or their effectiveness in preventing enve-
lope detection in the input stage will be reduced. Alterna-
tively, several smaller capacitors could be placed so that
lead inductance is further reduced. This is a consideration
because the frequency content of the conversion spikes
extends to 50MHz or more. The output impedance of
most op amps increases dramatically with frequency but
the effective output impedance of the LT1219 remains
low, determined by the ESR and inductance of the capaci-

tors above 10MHz. The conversion spikes that remain at
the output of other bipolar amplifiers pass through the
feedback network and often overdrive the input of the
amplifier, producing envelope detection. RFI may also be
present on the signal lines from the bridge; C3 and C4
provide RFI suppression at the signal input, as well as
suppressing transient voltages during bridge commuta-
tion.

The wideband noise density of the LT1219 is 33nV

Hz,

seemingly much noisier than the lowest noise amplifiers.
However, in the region just below the 1/f corner that is not
well suppressed by the correlated double sampling, the
average noise density is similar to the noise density of
many low noise amplifiers. If the amplifier is rolled off
below about 1500Hz, the total noise bandwidth is deter-
mined by the converter's Sinc

filter at about 12Hz. The

use of correlated double sampling involves averaging
even numbers of samples; hence, in this situation, two
samples would be averaged to give an input-referred
noise level of about 100nV

RMS

Level shift transistors Q4 and Q5 are included to allow
excitation voltages up to the maximum recommended for
the bridge. In the case shown, if a 10V supply is used, the
excitation voltage to the bridge is 8.5V and the outputs of
the bridge are above the supply rail of the ADC. U1 and U2
are also used to produce a level shift to bring the outputs
within the input range of the converter. This instrumenta-
tion amplifier topology does not require well-matched
resistors in order to produce good CMRR. However, the
use of R2 requires that R3 and R6 match well, as the
common mode gain is approximately 12dB. If the bridge
is composed of four equal 350

resistors, the differential

component associated with mismatch of R3 and R6 is
nearly constant with either polarity of excitation and, as
with offset, its contribution is canceled.

C-Load is a trademark of Linear Technology Corporation.

LTC2415/LTC2415-1

sn2415 24151fs

TYPICAL APPLICATIO S

************************************************************
* This example program transfers the LTC2415/LTC2415-1 32-bit output *
* conversion result into four consecutive 8-bit memory locations. *
************************************************************
*68HC11 register definition
PORTD

EQU

$1008

Port D data register

" , , SS* ,CSK ;MOSI,MISO,TxD ,RxD"

DDRD

EQU

$1009

Port D data direction register

SPSR

EQU

$1028

SPI control register

"SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0"

SPSR

EQU

$1029

SPI status register

"SPIF,WCOL, ,MODF; , , , "

SPDR

EQU

$102A

SPI data register; Read-Buffer; Write-Shifter

*
* RAM variables to hold the LTC2415/LTC2415-1's 32 conversion result
*
DIN1

EQU

$00

This memory location holds the LTC2415/LTC2415-1's bits 31 - 24

DIN2

EQU

$01

This memory location holds the LTC2415/LTC2415-1's bits 23 - 16

DIN3

EQU

$02

This memory location holds the LTC2415/LTC2415-1's bits 15 - 08

DIN4

EQU

$03

This memory location holds the LTC2415/LTC2415-1's bits 07 - 00

*
**********************
* Start GETDATA Routine *
**********************
*

ORG

$C000

Program start location

INIT1

LDS

#$CFFF

Top of C page RAM, beginning location of stack

LDAA

#$2F

,,1,0;1,1,1,1

, , SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X

STAA

PORTD

Keeps SS* a logic high when DDRD, bit 5 is set

LDAA

#$38

,,1,1;1,0,0,0

STAA

DDRD

SS*, SCK, MOSI are configured as Outputs

MISO, TxD, RxD are configured as Inputs

*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output

LDAA

#$50

STAA

SPCR

The SPI is configured as Master, CPHA = 0, CPOL = 0

and the clock rate is E/2

(This assumes an E-Clock frequency of 4MHz. For higher E-

Clock frequencies, change the above value of $50 to a value

that ensures the SCK frequency is 2MHz or less.)

GETDATA PSHX

PSHY
PSHA
LDX

#$0

The X register is used as a pointer to the memory locations

that hold the conversion data

LDY

#$1000

BCLR

PORTD, Y %00100000

This sets the SS* output bit to a logic

low, selecting the LTC2415/LTC2415-1

LTC2415/LTC2415-1

sn2415 24151fs

TYPICAL APPLICATIO S

********************************************
* The next short loop waits for the *
* LTC2415/LTC2415-1's conversion to finish before *
* starting the SPI data transfer *
********************************************
*
CONVEND LDAA

PORTD

Retrieve the contents of port D

ANDA

#%00000100

Look at bit 2

Bit 2 = Hi; the LTC2415/LTC2415-1's conversion is not

complete

Bit 2 = Lo; the LTC2415/LTC2415-1's conversion is complete

BNE

CONVEND

Branch to the loop's beginning while bit 2 remains
high

*
*
********************
* The SPI data transfer *
********************
*
TRFLP1

LDAA

#$0

Load accumulator A with a null byte for SPI transfer

STAA

SPDR

This writes the byte in the SPI data register and starts

the transfer

WAIT1

LDAA

SPSR

This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register

BPL

WAIT1

The SPIF (SPI transfer complete flag) bit is the SPSR's MSB

and is set to one at the end of an SPI transfer. The branch

will occur while SPIF is a zero.

LDAA

SPDR

Load accumulator A with the current byte of LTC2415/LTC2415-1 data
that was just received

STAA

0,X

Transfer the LTC2415/LTC2415-1's data to memory

INX

Increment the pointer

CPX

#DIN4+1 Has the last byte been transferred/exchanged?

BNE

TRFLP1

If the last byte has not been reached, then proceed to the

next byte for transfer/exchange

BSET

PORTD,Y %00100000 This sets the SS* output bit to a logic high,

de-selecting the LTC2415/LTC2415-1

PULA

Restore the A register

PULY

Restore the Y register

PULX

Restore the X register

RTS

Figure 38. This is an Example of 68HC11 Code That Captures the LTC2415/LTC2415-1
Conversion Results Over the SPI Serial Interface Shown in Figure 40

LTC2415/LTC2415-1

sn2415 24151fs

PACKAGE DESCRIPTIO

GN16 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.007 0.0098

(0.178 0.249)

0.053 0.068

(1.351 1.727)

0.008 0.012

(0.203 0.305)

0.004 0.0098

(0.102 0.249)

0.0250

(0.635)

BSC

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

16 15 14 13

0.189 0.196*

(4.801 4.978)

12 11 10 9

0.009

(0.229)

REF

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PCB LAYOUT A D FIL

Bottom Layer

LTC2415/LTC2415-1

sn2415 24151fs

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001

LT/TP 0202 2K · PRINTED IN USA

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0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency

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LTC2410

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ADC with Differential Inputs in MSOP

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LTC2413

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20-Bit, No Latency

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Figure 40. 24-Bit A/D Demo Board Schematic

JP4

JUMPER

DB9

2415 F40

J1
V

EXT

BAV74LT1

C4
100

16V

OUT

GND

LT1236ACN8-5

U3E

74HC14

U3F

74HC14

U3B

74HC14

U3A

74HC14

U3C

74HC14

U3D

74HC14

C3
10

35V

OUT

GND

LT1460ACN8-2.5

C1
10

35V

C2
22

25V

C6
0.1

C5
10

35V

J2
GND

GND

REF

BANANA JACK

REF

BANANA JACK

EXT

BANANA JACK

J10

GND

BANANA JACK

51k

R6
3k

Q1
MMBT3904LT1

49.9

R7
22k

R8
51k

REF

SCK

SDO

GND

GND GND GND

JP3

JUMPER

C7
0.1

BYPASS CAP

FOR U3

NOTES:
INSTALL JUMBER JP1 AT PIN 1 AND PIN 2
INSTALL JUMBER JP2 AT PIN 1 AND PIN 2
INSTALL JUMBER JP3 AT PIN 1 AND PIN 2

JP5
JUMPER

JP1

JUMPER

JP2

JUMPER

R2
3

LTC2415/

LTC2415-1

TYPICAL APPLICATIO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2415CGN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2415CGN