LTC2604/LTC2614/LTC2624

2604f

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

Quad 16-Bit Rail-to-Rail DACs

in 16-Lead SSOP

The LTC

2604/LTC2614/LTC2624 are quad 16-,14- and

12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in
16-lead narrow SSOP packages. These parts have sepa-
rate reference inputs for each DAC. They have built-in
high performance output buffers and are guaranteed
monotonic.

These parts establish advanced performance standards
for output drive, crosstalk and load regulation in single-
supply, voltage output multiples.

The parts use a simple SPI/MICROWIRE

compatible

3-wire serial interface which can be operated at clock
rates up to 50MHz. Daisy-chain capability and a hardware
CLR function are included.

The LTC2604/LTC2614/LTC2624 incorporate a power-
on reset circuit. During power-up, the voltage outputs
rise less than 10mV above zero scale; and after power-
up, they stay at zero scale until a valid write and update
take place.

Smallest Pin Compatible Quad 16-Bit DAC:

LTC2604: 16-Bits
LTC2614: 14-Bits
LTC2624: 12-Bits

Guaranteed 16-Bit Monotonic Over Temperature

Separate Reference Inputs for each DAC

Wide 2.5V to 5.5V Supply Range

Low Power Operation: 250

A per DAC at 3V

Individual DAC Power-Down to 1

A, Max

Ultralow Crosstalk Between DACs (<5

High Rail-to-Rail Output Drive (

15mA)

Double Buffered Digital Inputs

16-Lead Narrow SSOP Package

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

Differential Nonlinearity (LTC2604)

, LTC and LT are registered trademarks of Linear Technology Corporation.

GND

REF LO

REF A

OUTA

OUTB

REF B

CS/LD

SCK

REF D

OUT D

OUT C

REF C

SDO

SDI

2604 BD

DAC A

DAC D

DAC B

DAC C

DECODE

CONTROL

LOGIC

32-BIT SHIFT REGISTER

CLR

INPUT

DAC

INPUT

DAC

CODE

16384

32768

49152

65535

ERROR (LSB)

2604 TA01

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

MICROWIRE is a trademark of National Semiconductor Corp.

LTC2604/LTC2614/LTC2624

2604f

PSR

Power Supply Rejection

= 5V

10%

= 3V

10%

OUT

DC Output Impedance

REF

= V

= 5V, Midscale; 15mA

OUT

15mA

0.025

0.15

REF

= V

= 2.5V, Midscale; 7.5mA

OUT

7.5mA

0.030

0.15

BSOLUTE

ORDER PART

NUMBER

PACKAGE/ORDER I FOR ATIO

JMAX

= 125

= 150

C/W

(Note 1)

Any Pin to GND ........................................... 0.3V to 6V
Any Pin to V

............................................ 6V to 0.3V

Maximum Junction Temperature ......................... 125

Operating Temperature Range

LTC2604/LTC2614/LTC2624C ............... 0

C to 70

LTC2604/LTC2614/LTC2624I ............ 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................ 300

GN PART MARKING

ELECTRICAL C

HARA TERISTICS

LTC2604CGN
LTC2604IGN
LTC2614CGN
LTC2614IGN
LTC2624CGN
LTC2624IGN

Consult LTC Marketing for parts specified with wider operating temperature ranges.

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

GND

REF LO

REF A

OUT A

OUT B

REF B

CS/LD

SCK

REF D

OUT D

OUT C

REF C

CLR

SDO

SDI

2604
2604I
2614

2614I
2624
2624I

The

denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T

= 25

C. REF A = REF B = REF C = REF D = 4.096V (V

= 5V), REF A = REF B = REF C = REF D = 2.048V (V

= 2.5V),

REF LO = 0V, V

OUT

unloaded, unless otherwise noted.

LTC2604/LTC2614/LTC2624

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LTC2624

LTC2614

LTC2604

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC Performance

Resolution

Bits

Monotonicity

(Note 2)

Bits

DNL

Differential Nonlinearity

(Note 2)

0.5

LSB

INL

Integral Nonlinearity

(Note 2)

0.9

LSB

Load Regulation

REF

= V

= 5V, Midscale

OUT

= 0mA to 15mA Sourcing

0.025 0.125

0.1

0.5

0.3

LSB/mA

OUT

= 0mA to 15mA Sinking

0.025 0.125

0.1

0.5

0.3

LSB/mA

REF

= V

= 2.5V, Midscale

OUT

= 0mA to 7.5mA Sourcing

0.05

0.25

0.2

0.7

LSB/mA

OUT

= 0mA to 7.5mA Sinking

0.05

0.25

0.2

0.7

LSB/mA

ZSE

Zero-Scale Error

1.5

Offset Error

(Note 7)

1.5

Temperature

Coefficient

Gain Error

0.1

0.7

0.1

0.7

0.1

0.7

%FSR

Gain Temperature

ppm/

Coefficient

LTC2604/LTC2614/LTC2624

2604f

The

denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T

= 25

C. REF A = REF B = REF C = REF D = 4.096V (V

= 5V), REF A = REF B = REF C = REF D = 2.048V (V

= 2.5V),

REF LO = 0V, V

OUT

unloaded, unless otherwise noted.

ELECTRICAL C

HARA TERISTICS

LTC2604/LTC2614/LTC2624

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LTC2624

LTC2614

LTC2604

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

AC Performance

Settling Time (Note 8)

0.024% (

1LSB at 12 Bits)

0.006% (

1LSB at 14 Bits)

0.0015% (

1LSB at 16 Bits)

Settling Time for

0.024% (

1LSB at 12 Bits)

2.7

1LSB Step (Note 9)

0.006% (

1LSB at 14 Bits)

4.8

0.0015% (

1LSB at 16 Bits)

5.2

Voltage Output Slew Rate

0.80

Capacitive Load Driving

1000

Glitch Impulse

At Midscale Transition

nV · s

Multiplying Bandwidth

180

kHz

Output Voltage Noise

At f = 1kHz

120

nV/

Density

At f = 10kHz

100

nV/

Output Voltage Noise

0.1Hz to 10Hz

P-P

DC Crosstalk (Note 4)

Due to Full Scale Output Change (Note 5)

Due to Load Current Change

V/mA

Due to Powering Down (per Channel)

3.5

Short-Circuit Output Current

= 5.5V, V

REF

= 5.5V

Code: Zero Scale; Forcing Output to V

Code: Full Scale; Forcing Output to GND

= 2.5V, V

REF

= 2.5V

Code: Zero Scale; Forcing Output to V

7.5

Code: Full Scale; Forcing Output to GND

7.5

Reference Input

Input Voltage Range

Resistance

Normal Mode

128

160

Capacitance

REF

Reference Current, Power Down Mode

All DACs Powered Down

0.001

Power Supply

Positive Supply Voltage

For Specified Performance

2.5

5.5

Supply Current

= 5V (Note 3)

1.3

= 3V (Note 3)

1.6

All DACs Powered Down (Note 3) V

= 5V

0.35

All DACs Powered Down (Note 3) V

= 3V

0.10

Digital I/O

Digital Input High Voltage

= 2.5V to 5.5V

2.4

= 2.5V to 3.6V

2.0

Digital Input Low Voltage

= 4.5V to 5.5V

0.8

= 2.5V to 5.5V

0.6

Digital Output High Voltage

Load Current = 100

0.4

Digital Output Low Voltage

Load Current = +100

0.4

Digital Input Leakage

= GND to V

Digital Input Capacitance

(Note 6)

LTC2604/LTC2614/LTC2624

2604f

TI I G CHARACTERISTICS

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

to code

1, where N is the resolution and k

is given by k

= 0.016(2

REF

rounded to the nearest whole code. For V

REF

= 4.096V and N = 16,

= 256, linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V

Note 4: DC crosstalk is measured with V

= 5V and V

REF

= 4.096V, with

the measured DAC at midscale, unless otherwise noted.

Note 5: R

= 2k

to GND or V

Note 6: Guaranteed by design and not production tested.

Note 7: Inferred from measurement at code 256 (LTC2604), code 64
(LTC2614) or code 16 (LTC2624), and at full scale.

Note 8: V

= 5V, V

REF

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scate to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 9: V

= 5V, V

REF

= 4.096V. DAC is stepped 1LSB between half scale

and half scale 1. Load is 2k in parallel with 200pF to GND.

Current Limiting

Load Regulation

Offset Error vs Temperature

(LTC2604/LTC2614/LTC2624)

The

denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T

= 25

C. REF A = REF B = REF C = REF D = 4.096V (V

= 5V), REF A = REF B = REF C = REF D = 2.048V (V

= 2.5V),

REF LO = 0V, V

OUT

unloaded, unless otherwise noted.

OUT

(mA)

40 30 20 10

OUT

(V)

2604 G01

0.10

0.08

0.06

0.04

0.02

0.04

0.06

0.08

0.10

REF

= V

= 5V

REF

= V

= 3V

REF

= V

= 5V

REF

= V

= 3V

CODE = MIDSCALE

OUT

(mA)

OUT

(mV)

2604 G02

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

REF

= V

= 5V

CODE = MIDSCALE

REF

= V

= 3V

TEMPERATURE (

OFFSET ERROR (mV)

2604 G03

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2604/LTC2614/LTC2624

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

= 2.5V to 5.5V

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

SCK Low Time

CS/LD Pulse Width

LSB SCK High to CS/LD High

CS/LD Low to SCK High

SDO Propagation Delay from SCK Falling Edge

LOAD

= 10pF

= 4.5V to 5.5V

= 2.5V to 5.5V

CLR Pulse Width

CS/LD High to SCK Positive Edge

SCK Frequency

50% Duty Cycle

MHz

LTC2604/LTC2614/LTC2624

2604f

TYPICAL PERFOR A CE CHARACTERISTICS

TEMPERATURE (

ZERO-SCALE ERROR (mV)

2604 G04

2.5

2.0

1.5

1.0

0.5

TEMPERATURE (

GAIN ERROR (%FSR)

2604 G05

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

OFFSET ERROR (mV)

2604 G06

(V)

2.5

3.5

4.5

5.5

GAIN ERROR (%FSR)

2604 G07

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

(nA)

2604 G08

450

400

350

300

250

200

150

100

2.5

s/DIV

OUT

0.5V/DIV

2604 G09

REF

= V

= 5V

1/4-SCALE TO 3/4-SCALE

Gain Error vs Temperature

Offset Error vs V

Zero-Scale Error vs Temperature

Shutdown vs V

Large-Signal Settling

Gain Error vs V

Midscale Glitch Impulse

Power-On Reset Glitch

Headroom at Rails vs Output
Current

OUT

10mV/DIV

CS/LD

5V/DIV

2.5

s/DIV

2604 G10

12nV-s TYP

OUT

10mV/DIV

250

s/DIV

2604 G11

1V/DIV

4mV PEAK

OUT

(mA)

OUT

(V)

2604 G12

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

5V SOURCING

3V SOURCING

3V SINKING

5V SINKING

(LTC2604/LTC2614/LTC2624)

LTC2604/LTC2614/LTC2624

2604f

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Logic Voltage

Exiting Power-Down to Midscale

Hardware CLR

(LTC2604/LTC2614/LTC2624)

Multiplying Frequency Response

Output Voltage Noise,
0.1Hz to 10Hz

Short-Circuit Output Current vs
V

OUT

(Sinking)

Short-Circuit Output Current vs
V

OUT

(Sourcing)

LOGIC VOLTAGE (V)

0.5

1.5

2.5

3.5

4.5

(mA)

2604 G13

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

= 5V

SWEEP SCK, SDI
AND CS/LD
0V TO V

2.5

s/DIV

OUT

0.5V/DIV

CS/LD

5V/DIV

2604 G14

= 5V

REF

= 2V

DACs A-C IN
POWER-DOWN MODE

OUT

1V/DIV

s/DIV

2604 G15

CLR

5V/DIV

FREQUENCY (Hz)

2604 G16

10k

100k

= 5V

REF

(DC) = 2V

REF

(AC) = 0.2V

P-P

CODE = FULL SCALE

OUT

V/DIV

SECONDS

2604 G17

1V/DIV

10mA/DIV

0mA

2604 G18

= 5.5V

REF

= 5.6V

CODE = 0
V

OUT

SWEPT 0V TO V

1V/DIV

10mA/DIV

0mA

2604 G19

= 5.5V

REF

= 5.6V

CODE = FULL SCALE
V

OUT

SWEPT V

TO 0V

LTC2604/LTC2614/LTC2624

2604f

(LTC2604)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

DNL vs Temperature

INL vs V

REF

DNL vs V

REF

Settling to

1LSB

Settling of Full-Scale Step

TYPICAL PERFOR A CE CHARACTERISTICS

CODE

16384

32768

49152

65535

INL (LSB)

2604 G20

= 5V

REF

= 4.096V

CODE

16384

32768

49152

65535

DNL (LSB)

2604 G21

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

TEMPERATURE (

INL (LSB)

2604 G22

= 5V

REF

= 4.096V

INL (POS)

INL (NEG)

TEMPERATURE (

DNL (LSB)

2604 G23

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

DNL (POS)

DNL (NEG)

REF

(V)

INL (LSB)

2604 G24

= 5.5V

INL (POS)

INL (NEG)

REF

(V)

DNL (LSB)

2604 G25

1.5

1.0

0.5

1.0

1.5

= 5.5V

DNL (POS)

DNL (NEG)

s/DIV

2604 G26

OUT

100

V/DIV

CS/LD

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

9.7

s/DIV

2604 G27

OUT

100

V/DIV

CS/LD

2V/DIV

= 5V, V

REF

= 4.096V

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
SETTLING TO

1LSB

12.3

LTC2604/LTC2614/LTC2624

2604f

(LTC2614)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to

1LSB

Differential Nonlinearity (DNL)

Settling to

1LSB

(LTC2624)

TYPICAL PERFOR A CE CHARACTERISTICS

CODE

4096

8192

12288

16383

INL (LSB)

2604 G28

= 5V

REF

= 4.096V

CODE

4096

8192

12288

16383

DNL (LSB)

2604 G29

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

s/DIV

2604 G30

OUT

100

V/DIV

CS/LD

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

8.9

CODE

1024

2048

3072

4095

INL (LSB)

2604 G31

2.0

1.5

1.0

0.5

1.0

1.5

2.0

= 5V

REF

= 4.096V

CODE

1024

2048

3072

4095

DNL (LSB)

2604 G32

= 5V

REF

= 4.096V

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

s/DIV

2604 G33

OUT

1mV/DIV

CS/LD

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

6.8

Integral Nonlinearity (INL)

CTIO

GND (Pin 1): Analog Ground.

REF LO (Pin 2): Reference Low. The voltage at this pin sets
the zero scale (ZS) voltage of all DACs. The voltage range
is 0

REF LO

2.5V.

REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Reference
Voltage Inputs for each DAC. REF x sets the full scale
voltage of the DACs. 0V

REF x

OUT A

to V

OUT D

(Pins 4, 5, 13, 14): DAC Analog Voltage

Outputs. The output range is from REF LO to REF x.

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
into the register. When CS/LD is taken high, SCK is
disabled and the specified command (see Table 1) is
executed.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.

SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK. The
LTC2604/LTC2614/LTC2624 accepts input word lengths
of either 24 or 32 bits.

LTC2604/LTC2614/LTC2624

2604f

CTIO

BLOCK DIAGRA

SDO (Pin 10): Serial Interface Data Output. The serial
output of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32 SCK
rising edges before being output at the next falling edge.
This pin is used for daisy-chain operation.

GND

REF LO

REF A

OUTA

OUTB

REF B

CS/LD

SCK

REF D

OUT D

OUT C

REF C

SDO

SDI

2604 BD

DAC A

DAC D

DAC B

DAC C

DECODE

CONTROL

LOGIC

32-BIT SHIFT REGISTER

CLR

INPUT

DAC

INPUT

DAC

SDI

SDO

CS/LD

SCK

2604 F01

TI I G DIAGRA

Figure 1

CLR (Pin 11): Asynchronous Clear Input. A logic low at this
level-triggered input clears all registers and causes the
DAC voltage outputs to drop to 0V. CMOS and TTL-
compatible.

(Pin 16): Supply Voltage Input. 2.5V

5.5V.

LTC2604/LTC2614/LTC2624

2604f

Table 1.

COMMAND*

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

No Operation

ADDRESS (n)*

DAC A

DAC B

DAC C

DAC D

All DACs

OPERATIO

only be transferred to the device when the CS/LD signal is
low.The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.

The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.

While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don't-care bits are transferred to the device first, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy-
chain operation, and is also available to accommodate
microprocessors which have a minimum word width of 16
bits (2 bytes).

Power-On Reset

The LTC2604/LTC2614/LTC2624 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable.

For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2604/
LTC2614/LTC2624 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range 0.3V

REF x

+ 0.3V (see Absolute

Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V

(Pin 16) is in

transition.

Transfer Function

The digital-to-analog transfer function is

REF x REFLO

REFLO

OUT IDEAL

(

)

[

]

where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF A,
REF B, REF C and REF D (Pins 3, 6, 12 and 15).

Serial Interface

The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits
(LTC2604, LTC2614 and LTC2624 respectively). Data can

*Command and address codes not shown are reserved and should not be used.

LTC2604/LTC2614/LTC2624

2604f

OPERATIO

INPUT WORD (LTC2604)

INPUT WORD (LTC2614)

INPUT WORD (LTC2624)

Daisy-Chain Operation

The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.

The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a "daisy chain" series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the first instruction addresses the last device in the
chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.

In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the first
device as the data input. When the data transfer is com-
plete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.

COMMAND

ADDRESS

DATA (16 BITS)

C0 A3 A2 A1

D13

D14

D15

D12 D11 D10 D9

D7 D6

D1 D0

2604 TBL01

MSB

LSB

COMMAND

ADDRESS

DATA (14 BITS + 2 DON'T-CARE BITS)

C0 A3 A2 A1

D13 D12 D11 D10 D9

D7 D6

D1 D0

2604 TBL02

MSB

LSB

COMMAND

ADDRESS

DATA (12 BITS + 4 DON'T-CARE BITS)

C0 A3 A2 A1

D11 D10 D9

D7 D6

D1 D0

2604 TBL03

MSB

LSB

Power-Down Mode

For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high-impedance state, and the
output pins are passively pulled to ground through indi-
vidual 90k resistors. Input- and DAC-register contents are
not disturbed during power-down.

Any channel or combination of channels can be put into
power-down mode by using command 0100

in combina-

tion with the appropriate DAC address, (n). The 16-bit data
word is ignored. The supply current is reduced by approxi-
mately 1/4 for each DAC powered down. The effective
resistance at REF x (pins 3, 6, 12 and 15) are at high-
impedance input (typically > 1G

) when the correspond-

ing DACs are powered down.

Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If less
than four DACs are in a powered-down state prior to the
update command, the power-up delay time is 5

s. If on the

LTC2604/LTC2614/LTC2624

2604f

OPERATIO

other hand, all four DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power up delay time is
12

s (for V

= 5V) or 30

s (for V

= 3V).

Voltage Outputs

Each of the four rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier's ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.

DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers' DC output
impedance is 0.025

when driving a load well away from

the rails.

When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
30

typical channel resistance of the output devices; e.g.,

when sinking 1mA, the minimum output voltage = 30

1mA = 25mV. See the graph Headroom at Rails vs Output
Current in the Typical Performance Characteristics
section.

The amplifiers are stable driving capacitive loads of up to
1000pF.

Board Layout

The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
"signal" and "power" grounds separate.

The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.

Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device's ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. When a zero scale
DAC output voltage of zero is desired, the REFLO pin
(pin 2) should be connected to system star ground.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.

Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale
when the REF pins are tied to V

. If REF x = V

and the

DAC full-scale error (FSE) is positive, the output for the
highest codes limits at V

as shown in Figure 3c. No full-

scale limiting can occur if REF x is less than V

FSE.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

LTC2604/LTC2614/LTC2624

2604f

Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word)

LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don't Care Bits

LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don't Care Bits

D15

D14

D13

D12

D11

D10

CS/LD

SCK

SDI

COMMAND WORD

ADDRESS WORD

DATA WORD

DON'T CARE

D15

D14

D13

D12

D11

D10

SDO

CURRENT

32-BIT

INPUT WORD

2604 F02b

PREVIOUS 32-BIT INPUT WORD

D15

SCK

SDI

SDO

PREVIOUS D14

PREVIOUS D15

D14

OPERATIO

D15

D14

D13

D12

D11

D10

CS/LD

SCK

SDI

COMMAND WORD

ADDRESS WORD

DATA WORD

24-BIT INPUT WORD

2604 F02a

Figure 2b. LTC2604 32-Bit Load Sequence

LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't Care Bits

LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't Care Bits

LTC2604/LTC2614/LTC2624

2604f

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

GN16 (SSOP) 0204

.229 .244

(5.817 6.198)

.150 .157**

(3.810 3.988)

16 15 14 13

.189 .196*

(4.801 4.978)

12 11 10 9

.016 .050

(0.406 1.270)

.015

.004

(0.38

0.10)

TYP

.007 .0098

(0.178 0.249)

.0532 .0688

(1.35 1.75)

.008 .012

(0.203 0.305)

TYP

.004 .0098

(0.102 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 BSC

.0165

.0015

.045

.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:
1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2604/LTC2614/LTC2624

2604f

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.096V

LTC1458L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1654

Dual 14-Bit Rail-to-Rail V

OUT

DAC

Programmable Speed/Power, 3.5

s/750

A, 8

s/450

LTC1655/LTC1655L

Single 16-Bit V

OUT

DAC with Serial Interface in SO-8

= 5V(3V), Low Power, Deglitched

LTC1657/LTC1657L

Parrallel 5V/3V 16-Bit V

OUT

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

LTC1660/LTC1665

Octal 8/10-Bit V

OUT

DAC in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1821

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2

s for 10V Step

LTC2600/LTC2610/LTC2620

Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP

250

A per DAC, 2.5V to 5.5V Supply Range

LTC2602/LTC2612/LTC2622

Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP

300

A per DAC, 2.5V to 5.5V Supply Range

LINEAR TECHNOLOGY CORPORATION 2004

LT/TP 0304 1K · PRINTED IN THE USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

RELATED PARTS

TYPICAL APPLICATIO

Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and

DAC D to Trim for Minimum LO Feedthrough in a Mixer.

I + Q

MODULATOR

Q INPUT

I INPUT

70MHz IN

OUT

10k

20k

0.1

0.01

49.9

ZC830

47pF

10pF

20pF

*ZETEX

(516) 543-7100

OPTIONAL

LTC2604

CS/LD

SCK

SDI

DAC D

DAC B

OPTIONAL

DAC C

DAC A

0.1

20k

100k

2.74k

2.74k
1%

100k

2.74k
1%

2.74k

0.1

2604 F04

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2624

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2624