LTC3832/LTC3832-1

sn3832 3832fs

High Power Step-Down

Synchronous DC/DC Controllers

for Low Voltage Operation

OUT

as Low as 0.6V

High Power Switching Regulator Controller
for 3.3V-5V to 0.6V-3.xV Step-Down Applications

No Current Sense Resistor Required

Low Input Supply Voltage Range: 3V to 8V

Maximum Duty Cycle > 91% Over Temperature

All N-Channel External MOSFETs

Excellent Output Regulation:

1% Over Line, Load

and Temperature Variations

High Efficiency: Over 95% Possible

Adjustable or Fixed 2.5V Output (LTC3832)

Programmable Fixed Frequency Operation: 100kHz to
500kHz

External Clock Synchronization

Soft-Start

Low Shutdown Current: <10

Overtemperature Protection

Available in SO-8 and SSOP-16 Packages

CPU Power Supplies

Multiple Logic Supply Generator

Distributed Power Applications

High Efficiency Power Conversion

The LTC

3832/LTC3832-1 are high power, high effi-

ciency switching regulator controllers optimized for
3.3V-5V to 0.6V-3.xV step-down applications. A preci-
sion internal reference and feedback system provide

1% output regulation over temperature, load current

and line voltage variations. The LTC3832/LTC3832-1 use
a synchronous switching architecture with N-channel
MOSFETs. Additionally, the chip senses output current
through the drain-source resistance of the upper
N-channel MOSFET, providing an adjustable current limit
without a current sense resistor.

The LTC3832/LTC3832-1 operate with an input supply
voltage as low as 3V and with a maximum duty cycle of
>91% over temperature. They include a fixed frequency
PWM oscillator for low output ripple operation. The 300kHz
free-running clock frequency can be externally adjusted or
synchronized with an external signal from 100kHz to 500kHz.
In shutdown mode, the LTC3832 supply current drops to
<10

A. The LTC3832-1 is the SO-8 version without current

limit, frequency adjustment and shutdown functions.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Figure 1. High Efficiency 3.3V to 1V Power Converter

0.01

15k

COMP

GND

/PV

CC2

CC1

LTC3832-1

680pF

0.1

4.7

MBR0520T1

Si9426DY

OUT

1V
9A

3.2

Si9426DY

L1: SUMIDA CDEP105-3R2MC-88
C

OUT

: PANASONIC EEFUEOD271R

OUT

270

3832 F01

0.1

5.1

3V TO 7V

6.49k

4.32k

LOAD CURRENT (A)

EFFICIENCY (%)

100

3832 F01b

= 3.3V

OUT

= 2.5V

OUT

= 1V

Efficiency

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

LTC3832/LTC3832-1

sn3832 3832fs

Supply Voltage

....................................................................... 9V

CC1,2

................................................................ 14V

Input Voltage

, I

MAX

............................................... 0.3V to 14V

SENSE

, SENSE

, FB,

SHDN, FREQSET ....................... 0.3V to V

+ 0.3V

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

Junction Temperature ........................................... 125

Operating Temperature Range (Note 9) .. 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ORDER PART

NUMBER

LTC3832-1ES8

PART MARKING

38321

TOP VIEW

/PV

CC2

COMP

CC1

GND

S8 PACKAGE

8-LEAD PLASTIC SO

JMAX

= 125

= 130

C/ W

ORDER PART

NUMBER

LTC3832EGN

JMAX

= 125

= 130

C/ W

GN PACKAGE

16-LEAD PLASTIC SSOP

TOP VIEW

CC1

PGND

GND

SENSE

SHDN

CC2

MAX

FREQSET

COMP

Consult LTC Marketing for parts specified with wider operating temperature ranges.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

CC1

, PV

CC2

Voltage

(Note 7)

13.2

UVLO

Undervoltage Lockout Voltage

2.4

2.9

Feedback Voltage

COMP

= 1.25V

0.595

0.6

0.605

0.593

0.6

0.607

OUT

Output Voltage

COMP

= 1.25V

2.462

2.5

2.538

2.450

2.5

2.550

OUT

Output Load Regulation

OUT

= 0A to 10A (Note 6)

Output Line Regulation

= 4.75V to 5.25V

0.1

The

denotes specifications that apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. V

, PV

CC1

, PV

CC2

= 5V, unless otherwise noted. (Note 2)

ELECTRICAL CHARACTERISTICS

PART MARKING

3832

LTC3832/LTC3832-1

sn3832 3832fs

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VCC

Supply Current

Figure 2, V

SHDN

= V

0.7

1.6

SHDN

= 0V

PVCC

Supply Current

Figure 2, V

SHDN

= V

(Note 3)

SHDN

= 0V

0.1

OSC

Internal Oscillator Frequency

FREQSET Floating

230

300

360

kHz

SAWL

COMP

at Minimum Duty Cycle

1.2

SAWH

COMP

at Maximum Duty Cycle

2.2

COMPMAX

Maximum V

COMP

= 0V, PV

CC1

= 8V

2.85

OSC

FREQSET

Frequency Adjustment

kHz/

Error Amplifier Open-Loop DC Gain

Measured from FB to COMP,

SENSE

and SENSE

Floating, (Note 4)

Error Amplifier Transconductance

Measured from FB to COMP,

1600

2000

2400

mho

SENSE

and SENSE

Floating, (Note 4)

COMP

Error Amplifier Output Sink/Source Current

100

MAX

Sink Current

IMAX

= V

(Note 10)

MAX

Sink Current Tempco

IMAX

= V

(Note 6)

3300

ppm/

SHDN Input High Voltage

2.4

SHDN Input Low Voltage

0.8

SHDN Input Current

SHDN

= V

0.1

Soft-Start Source Current

= 0V, V

IMAX

= 0V, V

IFB

= V

SSIL

Maximum Soft-Start Sink Current

IMAX

= V

, V

IFB

= 0V,

1.6

In Current Limit

= V

(Note 8), PV

CC1

= 8V

SENSE

SENSE Input Resistance

23.7

SENSEFB

SENSE to FB Resistance

, t

Driver Rise/Fall Time

Figure 2, PV

CC1

= PV

CC2

= 5V (Note 5)

250

NOV

Driver Nonoverlap Time

Figure 2, PV

CC1

= PV

CC2

= 5V (Note 5)

120

250

MAX

Maximum G1 Duty Cycle

Figure 2, V

= 0V (Note 5), PV

CC1

= 8V

The

denotes specifications that apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. V

, PV

CC1

, PV

CC2

= 5V, unless otherwise noted. (Note 2)

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.

Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3832 operating frequency, operating voltage and the external FETs
used.

Note 4: The open-loop DC gain and transconductance from the SENSE

and SENSE

pins to COMP pin will be (A

)(0.6/2.5) and (g

)(0.6/2.5)

respectively.

Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.

Note 6: Guaranteed by design, not subject to test.

Note 7: PV

CC1

must be higher than V

by at least 2.5V for G1 to operate

at 95% maximum duty cycle and for the current limit protection circuit to
be active.

Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.

Note 9: The LTC3832E/LTC3832-1E are guaranteed to meet performance
specifications from 0

C to 70

C. Specifications over the 40

C to 85

operating temperature range are assured by design, characterization and
correlation with statistical process controls.

Note 10: The minimum and maximum limits for I

MAX

over temperature

includes the intentional temperature coefficient of 3300ppm/

C. This

induced temperature coefficient counteracts the typical temperature
coefficient of the external power MOSFET on-resistance. This results in a
relatively flat current limit over temperature for the application.

LTC3832/LTC3832-1

sn3832 3832fs

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

Line Regulation

Output Voltage Temperature Drift

Error Amplifier Transconductance
vs Temperature

Error Amplifier Sink/Source
Current vs Temperature

Error Amplifier Open-Loop Gain
vs Temperature

Oscillator Frequency
vs Temperature

Oscillator Frequency
vs FREQSET Input Current

Oscillator (V

SAWH

 V

SAWL

)

vs External Sync Frequency

TEMPERATURE (

ERROR AMPLIFIER SINK/SOURCE CURRENT (

180

3830 G05

120

200

160

140

100

125

EXTERNAL SYNC FREQUENCY (kHz)

100

0.5

SAWH

SAWL

(V)

0.6

0.8

0.9

1.0

1.5

1.2

200

300

3832 G09

0.7

1.3

1.4

1.1

400

500

= 25

OUTPUT CURRENT (A)

OUT

(V)

2.49

2.50

2.51

3832 G01

2.48

2.47

2.46

2.52

2.53

2.54

= 25

REFER TO FIGURE 12

SUPPLY VOLTAGE (V)

(V)

(mV)

0.601

0.603

0.605

3832 G02

0.599

0.597

0.600

0.602

0.604

0.598

0.596

0.595

= 25

TEMPERATURE (

ERROR AMPLIFIER TRANSCONDUCTANCE (

mho)

2300

3832 G03

2000

1800

1700

1600

2400

2200

2100

1900

100

125

TEMPERATURE (

2.45

OUT

(V)

OUT

(mV)

2.46

2.48

2.49

2.50

2.55

2.52

3832 G04

2.47

2.53

2.54

2.51

100

125

REFER TO FIGURE 12
OUTPUT = NO LOAD

TEMPERATURE (

ERROR AMPLIFIER OPEN-LOOP GIAN (dB)

3832 G06

100

125

TEMPERATURE (

OSCILLATOR FREQUENCY (kHz)

280

340

350

360

3832 G07

260

320

300

270

330

240

250

310

290

100

125

FREQSET FLOATING

FREQSET INPUT CURRENT (

700

600

500

400

300

200

100

3832 G08

OSCILLATOR FREQUENCY (kHz)

= 25

LTC3832/LTC3832-1

sn3832 3832fs

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum G1 Duty Cycle
vs Temperature

MAX

Sink Current

vs Temperature

Output Overcurrent Protection

Output Current Limit Threshold
vs Temperature

Soft-Start Source Current
vs Temperature

Soft-Start Sink Current
vs (V

IFB

 V

IMAX

)

Undervoltage Lockout Threshold
Voltage vs Temperature

Operating Supply Current

vs Temperature

Supply Current

vs Oscillator Frequency

TEMPERATURE (

MAXIMUM G1 DUTY CYCLE (%)

100

3832 G10

100

125

= 0V

REFER TO FIGURE 3

TEMPERATURE (

MAX

SINK CURRENT (

3832 G11

100

125

TEMPERATURE (

SOFT-START SOURCE CURRENT (

3830 G14

100

125

IFB

IMAX

(mV)

150

SOFT-START SINK CURRENT (mA)

0.75

1.00

1.25

3832 G15

0.50

0.25

125

100

1.50

1.75

2.00

= 25

TEMPERATURE (

2.0

UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)

2.1

2.3

2.4

2.5

3.0

2.7

3832 G16

2.2

2.8

2.9

2.6

100

125

TEMPERATURE (

OPERATING SUPPLY CURRENT (mA)

0.8

1.4

1.5

1.6

3832 G17

0.6

1.2

1.0

0.7

1.3

0.5

0.4

1.1

0.9

100

125

FREQSET FLOATING

OSCILLATOR FREQUENCY (kHz)

SUPPLY CURRENT (mA)

200

400

500

3832 G18

100

300

= 25

G1 AND G2 LOADED

WITH 6800pF,
PV

CC1,2

= 12V

G1 AND G2

LOADED

WITH 1000pF,

CC1,2

= 5V

G1 AND G2

LOADED

WITH 6800pF,

CC1,2

= 5V

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

1.0

2.0

3.0

0.5

1.5

2.5

3832 G12

= 25

REFER TO FIGURE 12

TEMPERATURE (

OUTPUT CURRENT LIMIT (A)

3832 G13

100

125

REFER TO FIGURE 12 AND NOTE 10 OF
THE ELECTRICAL CHARACTERISTICS

LTC3832/LTC3832-1

sn3832 3832fs

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current

vs Gate Capacitance

G1 Rise/Fall Time
vs Gate Capacitance

Transient Response

PI FU CTIO S

G1 (Pin 1/Pin 1): Top Gate Driver Output. Connect this pin
to the gate of the upper N-channel MOSFET, Q1. This
output swings from PGND to PV

CC1

. It remains low if G2

is high or during shutdown mode.

CC1

(Pin 2/Pin 2): Power Supply Input for G1. Connect

this pin to a potential of at least V

+ V

GS(ON)(Q1)

. This

potential can be generated using an external supply or
charge pump.

PGND (Pin 3/Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques. The LTC3832-1 has PGND and GND tied
together internally at Pin 3.

GND (Pin 4/Pin 3): Signal Ground. All low power internal
circuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3832.

SENSE

, FB, SENSE

(Pins 5, 6, 7/Pin 4): These three

pins connect to the internal resistor divider and input of the
error amplifier. To use the internal divider to set the output
voltage to 2.5V, connect SENSE

to the positive terminal

of the output capacitor and SENSE

to the negative termi-

nal. FB should be left floating. To use an external resistor

divider to set the output voltage, float SENSE

and SENSE

and connect the external resistor divider to FB. The internal
resistor divider is not included in the LTC3832-1.

SHDN (Pin 8/NA): Shutdown. A TTL compatible low level
at SHDN for longer than 100

s puts the LTC3832 into

shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10

A max. A TTL compatible high level at SHDN

allows the part to operate normally. This pin also doubles
as an external clock input to synchronize the internal
oscillator with an external clock. The shutdown function is
disabled in the LTC3832-1.

SS (Pin 9/Pin 5): Soft-Start. Connect this pin to an external
capacitor, C

, to implement a soft-start function. If the

LTC3832 goes into current limit, C

is discharged to

reduce the duty cycle. C

must be selected such that

during power-up, the current through Q1 will not exceed
the current limit level.

COMP (Pin 10/Pin 6): External Compensation. This pin
internally connects to the output of the error amplifier and
input of the PWM comparator. Use a RC + C network at this
pin to compensate the feedback loop to provide optimum
transient response.

(LTC3832/LTC3832-1)

OUT

50mV/DIV

LOAD

2AV/DIV

s/DIV

3832 G21

GATE CAPACITANCE AT G1 AND G2 (nF)

G1 RISE/FALL TIME (ns)

120

160

200

3832 G20

100

140

180

= 25

AT PV

CC1,2

= 12V

AT PV

CC1,2

= 12V

AT PV

CC1,2

= 5V

AT PV

CC1,2

= 5V

GATE CAPACITANCE AT G1 AND G2 (nF)

SUPPLY CURRENT (mA)

3832 G19

= 25

CC1,2

= 12V

CC1,2

= 5V

LTC3832/LTC3832-1

sn3832 3832fs

PI FU CTIO S

FREQSET (Pin 11/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 300kHz.
A resistor from FREQSET to ground speeds up the oscil-
lator; a resistor to V

slows it down.

MAX

(Pin 12/NA): Current Limit Threshold Set. I

MAX

sets

the threshold for the internal current limit comparator. If
I

drops below I

MAX

with G1 on, the LTC3832 goes into

current limit. I

MAX

has an internal 12

A pull-down to GND.

Connect this pin to the main V

supply at the drain of Q1,

through an external resistor to set the current limit thresh-
old. Connect a 0.1

F decoupling capacitor across this

resistor to filter switching noise.

(Pin 13/NA): Current Limit Sense. Connect this pin to

the switching node at the source of Q1 and the drain of Q2
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging I

.This pin is used for

sensing the voltage drop across the upper N-channel
MOSFET, Q1.

(Pin 14/Pin 7): Power Supply Input. All low power

internal circuits draw their supply from this pin. Connect
this pin to a clean power supply, separate from the main
V

supply at the drain of Q1. This pin requires a 4.7

bypass capacitor. The LTC3832-1has V

and PV

CC2

tied

together at Pin 7 and requires a 10

F bypass capacitor to

GND.

CC2

(Pin 15/Pin 7): Power Supply Input for G2. Connect

this pin to the main high power supply.

G2 (Pin 16/Pin 8): Bottom Gate Driver Output. Connect
this pin to the gate of the lower N-channel MOSFET, Q2.
This output swings from PGND to PV

CC2

. It remains low

when G1 is high or during shutdown mode. To prevent
output undershoot during a soft-start cycle, G2 is held low
until G1 first goes high (FFBG in the Block Diagram).

BLOCK DIAGRA

CC1

CC2

PGND

SENSE

REF

+ 10%

18k

5.7k

SENSE

3832 BD

POR

FFBG

ENABLE
G2

PWM

QSS

REF

+ 10%

MAX

ERR

INTERNAL

OSCILLATOR

100

s DELAY

SHDN

FREQSET

COMP

POWER DOWN

DISABLE GATE DRIVE

LOGIC AND

THERMAL SHUTDOWN

2.2V

1.2V

CC1

+ 2.5V

DISABLE
I

LIM

MAX

GND

(LTC3832)

LTC3832/LTC3832-1

sn3832 3832fs

TEST CIRCUITS

FREQSET

COMP

MAX

SHDN

CC2

CC1

6800pF

3832 F02

GND

PGND

SENSE

LTC3832

SENSE

COMP

CC1

CC2

6800pF

0.1

6800pF

G1 RISE/FALL

G2 RISE/FALL

3832 F03

MAX

GND

PGND

LTC3832

Figure 2

Figure 3

BLOCK DIAGRA

(LTC3832-1)

CC1

/PV

CC2

PGND

REF

+ 10%

3832 BD2

POR

FFG2

ENABLE
G2

PWM

QSS

REF

+ 10%

MAX

ERR

INTERNAL

OSCILLATOR

COMP

POWER DOWN

DISABLE GATE DRIVE

THERMAL SHUTDOWN

2.2V

1.2V

CC1

+ 2.5V

APPLICATIO S I FOR ATIO

OVERVIEW

The LTC3832/LTC3832-1 are voltage mode feedback,
synchronous switching regulator controllers (see Block
Diagram) designed for use in high power, low voltage
step-down (buck) converters. They include an onboard
PWM generator, a precision reference trimmed to

0.8%,

two high power MOSFET gate drivers and all necessary

feedback and control circuitry to form a complete switch-
ing regulator circuit. The PWM loop nominally runs at
300kHz.

The LTC3832 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor.

LTC3832/LTC3832-1

sn3832 3832fs

APPLICATIO S I FOR ATIO

Also included in the LTC3832 is an internal soft-start
feature that requires only a single external capacitor to
operate. In addition, the LTC3832 features an adjustable
oscillator that can free run or synchronize to external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection. The
LTC3832-1 does not include current limit, frequency
adjustability, external synchronization and the shutdown
function.

THEORY OF OPERATION

Primary Feedback Loop

The LTC3832/LTC3832-1 sense the output voltage of the
circuit at the output capacitor and feeds this voltage back
to the internal transconductance error amplifier, ERR,
through a resistor divider network. The error amplifier
compares the resistor-divided output voltage to the inter-
nal 0.6V reference and outputs an error signal to the PWM
comparator. This error signal is compared with a fixed
frequency ramp waveform, from the internal oscillator, to
generate a pulse width modulated signal. This PWM signal
drives the external MOSFETs through the G1 and G2 pins.
The resulting chopped waveform is filtered by L

and C

OUT

which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.

MAX Feedback Loop

An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
compares the feedback signal to a voltage 60mV above the
internal reference. If the signal is above the comparator
threshold, the MAX comparator overrides the error ampli-
fier and forces the loop to minimum duty cycle, 0%. To
prevent this comparator from triggering due to noise, the
MAX comparator's response time is deliberately delayed
by two to three microseconds. This comparator helps
prevent extreme output perturbations with fast output
load current transients, while allowing the main feedback
loop to be optimally compensated for stability.

Thermal Shutdown

The LTC3832/LTC3832-1 have a thermal protection cir-
cuit that disables both gate drivers if activated. If the chip
junction temperature reaches 150

C, both G1 and G2 are

pulled low. G1 and G2 remain low until the junction
temperature drops below 125

C, after which, the chip

resumes normal operation.

Soft-Start and Current Limit

The LTC3832 includes a soft-start circuit that is used for
start-up and current limit operation. The LTC3832-1 only
has the soft-start function; the current limit function is
disabled. The SS pin requires an external capacitor, C

to GND with the value determined by the required soft-
start time. An internal 12

A current source is included to

charge C

. During power-up, the COMP pin is clamped to

a diode drop (B-E junction of QSS in the Block Diagram)
above the voltage at the SS pin. This prevents the error
amplifier from forcing the loop to maximum duty cycle.
The LTC3832/LTC3832-1 operate at low duty cycle as the
SS pin rises above 0.6V (V

COMP

1.2V). As SS continues

to rise, QSS turns off and the error amplifier takes over to
regulate the output.

The LTC3832 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
upper MOSFET, Q1, at the I

pin. CC compares the voltage

at I

to the voltage at the I

MAX

pin. As the peak current

rises, the measured voltage across Q1 increases due to the
drop across the R

DS(ON)

of Q1. When the voltage at I

drops below I

MAX

, indicating that Q1's drain current has

exceeded the maximum level, CC starts to pull current out
of C

, cutting the duty cycle and controlling the output

current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between I

and I

MAX

. Under minor overload conditions, the SS pin

falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output

LTC3832/LTC3832-1

sn3832 3832fs

remains at a reduced voltage until the overload is re-
moved. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the R

DS(ON)

of Q1 to measure the output current, the current limiting
circuit eliminates an expensive discrete sense resistor that
would otherwise be required. This helps minimize the
number of components in the high current path.

The current limit threshold can be set by connecting an
external resistor R

IMAX

from the I

MAX

pin to the main V

supply at the drain of Q1. The value of R

IMAX

is determined

by:

IMAX

= (I

LMAX

)(R

DS(ON)Q1

)/I

IMAX

where:

LMAX

= I

LOAD

+ (I

RIPPLE

/2)

LOAD

= Maximum load current

RIPPLE

= Inductor ripple current

(

)(

)

( )

( )( )

OUT

OSC

= LTC3832 oscillator frequency = 300kHz

= Inductor value

DS(ON)Q1

= On-resistance of Q1 at I

LMAX

IMAX

= Internal 12

A sink current at I

MAX

The R

DS(ON)

of Q1 usually increases with temperature. To

keep the current limit threshold constant, the internal
12

A sink current at I

MAX

is designed with a positive

temperature coefficient to provide first order correction
for the temperature coefficient of R

DS(ON)Q1

In order for the current limit circuit to operate properly and
to obtain a reasonably accurate current limit threshold, the
I

IMAX

and I

pins must be Kelvin sensed at Q1's drain and

source pins. In addition, connect a 0.1

F decoupling

capacitor across R

IMAX

to filter switching noise. Other-

wise, noise spikes or ringing at Q1's source can cause the
actual maximum current to be greater than the desired
current limit set point. Due to switching noise and varia-
tion of R

DS(ON)

, the actual current limit trip point is not

highly accurate. The current limiting circuitry is primarily

meant to prevent damage to the power supply circuitry
during fault conditions. The exact current level where the
limiting circuit begins to take effect will vary from unit to
unit as the R

DS(ON)

of Q1 varies. Typically, R

DS(ON)

varies

as much as

40%, and with

33% variation on the

LTC3832's I

MAX

current, this can give a

73% variation on

the current limit threshold.

The R

DS(ON)

is high if the V

applied to the MOSFET is

low. This occurs during power up when PV

CC1

is ramping

up. To prevent the high R

DS(ON)

from activating the current

limit, the LTC3832 will disable the current limit circuit if
PV

CC1

is less than 2.5V above V

. To ensure proper

operation of the current limit circuit, PV

CC1

must be at

least 2.5V above V

when G1 is high. PV

CC1

can go low

when G1 is low, allowing the use of the external charge
pump to power PV

CC1

APPLICATIO S I FOR ATIO

Figure 4. Current Limit Setting

LTC3832

0.1

OUT

3832 F04

OUT

MAX

IMAX

Oscillator Frequency

The LTC3832 includes an onboard current controlled
oscillator that typically free-runs at 300kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 300kHz. Every additional 1

A of current into/out

of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V. The
frequency can be estimated as:

kHz

EXT

FSET

300

1 265

where R

FSET

is a frequency programming resistor con-

nected between FREQSET and the external voltage source
V

EXT

LTC3832/LTC3832-1

sn3832 3832fs

Connecting a 82k resistor from FREQSET to ground
forces 15

A out of the pin, causing the internal oscillator

to run at approximately 450kHz. Forcing an external 20

current into FREQSET cuts the internal frequency to
100kHz. An internal clamp prevents the oscillator from
running slower than about 50kHz. Tying FREQSET to V

forces the chip to run at this minimum speed. The
LTC3832-1 does not have this frequency adjustment
function.

Shutdown

The LTC3832 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN for
more than 100

s forces the LTC3832 into shutdown

mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3832 supply current drops to <10

A, although off-

state leakage in the external MOSFETs may cause the total
V

current to be some what higher, especially at elevated

temperatures. If SHDN returns high, the LTC3832 reruns
a soft-start cycle and resumes normal operation. The
LTC3832-1 does not have this shutdown function.

External Clock Synchronization

The LTC3832 SHDN pin doubles as an external clock
input for applications that require a synchronized clock.
An internal circuit forces the LTC3832 into external
synchronization mode if a negative transition at the SHDN
pin is detected. In this mode, every negative transition on
the SHDN pin resets the internal oscillator and pulls the
ramp signal low, this forces the LTC3832 internal oscil-
lator to lock to the external clock frequency. The LTC3832-1
does not have this external synchronization function.

The LTC3832 internal oscillator can be externally synchro-
nized from 100kHz to 500kHz. Frequencies above 300kHz
can cause a decrease in the maximum obtainable duty
cycle as rise/fall time and propagation delay take up a
larger percentage of the switch cycle. Circuits using these
frequencies should be checked carefully in applications
where operation near dropout is important--like 3.3V to
2.5V converters. The low period of this clock signal must
not be >100

s, or else the LTC3832 enters shutdown

mode.

Figure 5 describes the operation of the conventional
synchronization function. A negative transition at the
SHDN pin forces the internal ramp signal low to restart a
new PWM cycle. Notice that the ramp amplitude is lowered
as the external clock frequency goes higher. The effect of
this decrease in ramp amplitude increases the open-loop
gain of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
back loop to be unstable if the phase margin is insufficient.

To overcome this problem, the LTC3832 monitors the
peak voltage of the ramp signal and adjusts the oscillator
charging current to maintain a constant ramp peak.

APPLICATIO S I FOR ATIO

SHDN

300kHz

FREE RUNNING

RAMP SIGNAL

TRADITIONAL

SYNC METHOD

WITH EARLY

RAMP

TERMINATION

LTC3832

KEEPS RAMP

AMPLITUDE

CONSTANT

UNDER SYNC

RAMP SIGNAL

WITH EXT SYNC

RAMP AMPLITUDE

ADJUSTED

3832 F05

Figure 5. External Synchronization Operation

Input Supply Considerations/Charge Pump

The LTC3832 requires four supply voltages to operate: V

for the main power input, PV

CC1

and PV

CC2

for MOSFET

gate drive and a clean, low ripple V

for the LTC3832

internal circuitry (Figure 6). The LTC3832-1 has the PV

CC2

and V

pins tied together inside the package (Figure 7).

This pin, brought out as V

/PV

CC2

, has the same low

ripple requirements as the LTC3832, but must also be able
to supply the gate drive current to Q2.

LTC3832/LTC3832-1

sn3832 3832fs

In many applications, V

can be powered from V

through an RC filter. This supply can be as low as 3V. The
low quiescent current (typically 800

A) allows the use of

relatively large filter resistors and correspondingly small
filter capacitors. 100

and 4.7

F usually provide ad-

equate filtering for V

. For best performance, connect the

4.7

F bypass capacitor as close to the LTC3832 V

pin as

possible.

Gate drive for the top N-channel MOSFET Q1 is supplied
from PV

CC1

. This supply must be above V

(the main

power supply input) by at least one power MOSFET V

GS(ON)

for efficient operation. An internal level shifter allows PV

CC1

to operate at voltages above V

and V

, up to 14V maxi-

mum. This higher voltage can be supplied with a separate
supply, or it can be generated using a charge pump.

Gate drive for the bottom MOSFET Q2 is provided through
PV

CC2

for the LTC3832 or V

/PV

CC2

for the LTC3832-1.

This supply only needs to be above the power MOSFET
V

GS(ON)

for efficient operation. PV

CC2

can also be driven

from the same supply/charge pump for the PV

CC1

, or it can

be connected to a lower supply to improve efficiency.

APPLICATIO S I FOR ATIO

Figure 8. Tripling Charge Pump

LTC3832

3832 F08

12V
1N5242

0.1

OUT

0.1

CC2

1N5817

CC1

3832 F6

CC2

CC1

OUT

INTERNAL

CIRCUITRY

LTC3832

3832 F7

/PV

CC2

CC1

OUT

INTERNAL

CIRCUITRY

LTC3832-1

Figure 6. LTC3832 Power Supplies

Figure 7. LTC3832-1 Power Supplies

Figure 8 shows a tripling charge pump circuit that can be
used to provide 2V

and 3V

gate drive for the external

top and bottom MOSFETs respectively. These should fully
enhance MOSFETs with 5V logic level thresholds. This
circuit provides 3V

to PV

CC1

while Q1 is ON and

to PV

CC2

where V

is the forward voltage of the

Schottky diodes. The circuit requires the use of Schottky
diodes to minimize forward drop across the diodes at
start-up. The tripling charge pump circuit can rectify any
ringing at the drain of Q2 and provide more than 3V

CC1

; a 12V zener diode should be included from PV

CC1

to PGND to prevent transients from damaging the circuitry
at PV

CC1

or the gate of Q1.

The charge pump capacitors for PV

CC1

refresh when the

G2 pin goes high and the switch node is pulled low by Q2.
The G2 on-time becomes narrow when LTC3832/
LTC3832-1 operates at a maximum duty cycle (95%
typical), which can occur if the input supply rises more
slowly than the soft-start capacitor or if the input voltage
droops during load transients. If the G2 on-time gets so
narrow that the switch node fails to pull completely to
ground, the charge pump voltage may collapse or fail to
start, causing excessive dissipation in external MOSFET,
Q1. This condition is most likely with low V

voltages and

high switching frequencies, coupled with large external
MOSFETs which slow the G2 and switch node slew rates.

The LTC3832/LTC3832-1 overcome this problem by sens-
ing the PV

CC1

voltage when G1 is high. If PV

CC1

is less than

2.5V above V

, the maximum G1 duty cycle is reduced to

70% by clamping the COMP pin at 1.8V (QC in the Block

LTC3832/LTC3832-1

sn3832 3832fs

Diagram). This increases the G2 on-time and allows the
charge pump capacitors to be refreshed.

For applications using an external supply to PV

CC1

, this

supply must also be higher than V

by at least 2.5V to

ensure normal operation.

For applications with a 5V or higher V

supply, PV

CC2

can

be tied to V

if a logic level MOSFET is used. PV

CC1

can be

supplied using a doubling charge pump as shown in
Figure 9. This circuit provides 2V

to PV

CC1

while Q1

is ON.

enhance standard power MOSFETs. Under this condition,
the effective MOSFET R

DS(ON)

may be quite high, raising

the dissipation in the FETs and reducing efficiency. Logic
level FETs are the recommended choice for 5V or lower
voltage systems. Logic level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efficiency.

After the MOSFET threshold voltage is selected, choose the
R

DS(ON)

based on the input voltage, the output voltage,

allowable power dissipation and maximum output current.
In a typical LTC3832 circuit, operating in continuous mode,
the average inductor current is equal to the output load
current. This current flows through either Q1 or Q2 with the
power dissipation split up according to the duty cycle:

DC Q

OUT

( )

(

)

The R

DS(ON)

required for a given conduction loss can now

be calculated by rearranging the relation P = I

DC Q

DS ON Q

MAX Q

LOAD

MAX Q

OUT

LOAD

DS ON Q

MAX Q

LOAD

MAX Q

OUT

LOAD

(

)

(

)

(

)

(

)

(

)

(

)

( ) · (

)

· (

)

(

) · (

)

(

) · (

)

MAX

should be calculated based primarily on required

efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for 3.3V input and 2.5V at 10A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a P

MAX

value of:

(2.5V)(10A/0.9)(0.03) = 0.83W per FET

and a required R

DS(ON)

of:

DS ON Q

(

)

(

)

( .

) · ( .

)

( .

)(

)

( .

) · ( .

)

( .

)(

)

3 3

0 83

2 5

0 011

3 3

0 83

3 3

2 5

0 034

APPLICATIO S I FOR ATIO

LTC3832

3832 F09

12V
1N5242

OUT

0.1

CC2

OPTIONAL

USE FOR V

MBR0530T1

CC1

Figure 9. Doubling Charge Pump

Power MOSFETs

Two N-channel power MOSFETs are required for most
LTC3832 circuits. These should be selected based
primarily on threshold voltage and on-resistance consid-
erations. Thermal dissipation is often a secondary con-
cern in high efficiency designs. The required MOSFET
threshold should be determined based on the available
power supply voltages and/or the complexity of the gate
drive charge pump scheme. In 3.3V input designs where
an auxiliary 12V supply is available to power PV

CC1

and

CC2

, standard MOSFETs with R

DS(ON)

specified at V

= 5V or 6V can be used with good results. The current
drawn from this supply varies with the MOSFETs used
and the LTC3832's operating frequency, but is generally
less than 50mA.

LTC3832 applications that use 5V or lower V

voltage and

a doubling/tripling charge pump to generate PV

CC1

and

CC2

, do not provide enough gate drive voltage to fully

LTC3832/LTC3832-1

sn3832 3832fs

Note that the required R

DS(ON)

for Q2 is roughly three

times that of Q1 in this example. Note also that while the
required R

DS(ON)

values suggest large MOSFETs, the

power dissipation numbers are only 0.83W per device or
less; large TO-220 packages and heat sinks are not neces-
sarily required in high efficiency applications. Siliconix
Si4410DY or International Rectifier IRF7413 (both in
SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semi-
conductor MTD20N03HDL (DPAK) are small footprint
surface mount devices with R

DS(ON)

values below 0.03

at 5V of V

that work well in LTC3832 circuits. Using a

higher P

MAX

value in the R

DS(ON)

calculations generally

decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.

Table 1 highlights a variety of power MOSFETs for use in
LTC3832 applications.

Inductor Selection

The inductor is often the largest component in an LTC3832
design and must be chosen carefully. Choose the inductor
value and type based on output slew rate requirements. The
maximum rate of rise of inductor current is set by the
inductor's value, the input-to-output voltage differential and

the LTC3832's maximum duty cycle. In a typical 3.3V in-
put, 2.5V output application, the maximum rise time will be:

MAX

OUT

· (

)

0 76

where L

is the inductor value in

H. With proper fre-

quency compensation, the combination of the inductor
and output capacitor values determine the transient recov-
ery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
core saturation rating. A 1

H inductor has a 0.76A/

s rise

time in this application, resulting in a 6.6

s delay in

responding to a 5A load current step. During this 6.6

the difference between the inductor current and the output
current is made up by the output capacitor. This action
causes a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1

H to 5

H range for most 3.3V input LTC3832

circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.

Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency

APPLICATIO S I FOR ATIO

Table 1. Recommended MOSFETs for LTC3832 Applications

TYPICAL INPUT

DS(ON)

CAPACITANCE

PARTS

AT 25

C (m

)

RATED CURRENT (A)

ISS

(pF)

(

C/W)

JMAX

(

Siliconix SUD50N03-10

15 at 25

3200

1.8

175

TO-252

10 at 100

Siliconix Si4410DY

10 at 25

2700

150

SO-8

8 at 70

ON Semiconductor MTD20N03HDL

20 at 25

880

1.67

150

DPAK

16 at 100

Fairchild FDS6670A

13 at 25

3200

150

S0-8

Fairchild FDS6680

11.5 at 25

2070

150

SO-8

ON Semiconductor MTB75N03HDL

75 at 25

4025

150

DD PAK

59 at 100

IR IRL3103S

64 at 25

1600

1.4

175

DD PAK

45 at 100

IR IRLZ44

50 at 25

3300

175

TO-220

36 at 100

Fuji 2SK1388

35 at 25

1750

2.08

150

TO-220

Note: Please refer to the manufacturer's data sheet for testing conditions and detailed information.

LTC3832/LTC3832-1

sn3832 3832fs

requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:

RIPPLE

OUT

OSC

(

) · (

)

OSC

= LTC3832 oscillator frequency = 300kHz

= Inductor value

Solving this equation with our typical 3.3V to 2.5V appli-
cation with a 1

H inductor, we get:

( .

) · .

· .

3 3

2 5

300

3 3

kHz

-P

Peak inductor current at 10A load:

10A + (2A/2) = 11A

The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short-circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductors with gradual saturation characteristics are often
the best choice.

Input and Output Capacitors

A typical LTC3832 design places significant demands on
both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3832
draws square waves of current from the input supply at the
switching frequency. The peak current value is equal to the
output load current plus 1/2 the peak-to-peak ripple cur-
rent. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal

to I

OUT

/2. A low ESR input capacitor with an adequate

ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers' ripple cur-
rent ratings are often based on only 2000 hours (3 months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer's speci-
fication is recommended to extend the useful life of the
circuit. Lower operating temperature has the largest effect
on capacitor longevity.

The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3832 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. An 5A load step with a 0.05

ESR output

capacitor results in a 250mV output voltage shift; this is
10% of the output voltage for a 2.5V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capaci-
tor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.

Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC3832 applications. OS-CON
electrolytic capacitors from Sanyo and other manufactur-
ers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. Other capacitors that can be used
include the Sanyo POSCAP and MV-WX series.

A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical

APPLICATIO S I FOR ATIO

LTC3832/LTC3832-1

sn3832 3832fs

LTC3832 application might exhibit 5A input ripple cur-
rent. Sanyo OS-CON capacitors, part number 10SA220M
(220

F/10V), feature 2.3A allowable ripple current at

C; three in parallel at the input (to withstand the input

ripple current) meet the above requirements. Similarly,
Sanyo POSCAP 4TPB470M (470

F/4V) capacitors have a

maximum rated ESR of 0.04

; three in parallel lower the

net output capacitor ESR to 0.013

Feedback Loop Compensation

The LTC3832 voltage feedback loop is compensated at the
COMP pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC +
C network from COMP to GND as shown in Figure 10a.

Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:

OUT

[

]

1 2

(

)(

)

The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:

ESR C

ESR

OUT

[

]

1 2

(

)(

)

The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:

= 1/[2

)(C

)] and

= 1/[2

)(C1)] respectively

Figure 10b shows the Bode plot of the overall transfer
function.

When low ESR output capacitors (Sanyo OS-CON) are
used, the ESR zero can be high enough in frequency that
it provides little phase boost at the loop crossover fre-
quency. As a result, the phase margin becomes
inadequate and the load transient is not optimized. To
resolve this problem, a small capacitor can be connected

APPLICATIO S I FOR ATIO

3832 F10a

LTC3832

REF

SENSE

COMP

ERR

Figure 10a. Compensation Pin Hook-Up

LOOP GAIN

3832 F10b

3832 F10c

ZC2

PC2

ESR

FREQUENCY

20dB/DECADE

= LTC3832 SWITCHING

FREQUENCY

= CLOSED-LOOP CROSSOVER

FREQUENCY

= LTC3832 SWITCHING

FREQUENCY

= CLOSED-LOOP CROSSOVER

FREQUENCY

Figure 10b. Bode Plot of the LTC3832 Overall Transfer Function

Figure 10c. Bode Plot of the LTC3832 Overall
Transfer Function Using a Low ESR Output Capacitor

LTC3832/LTC3832-1

sn3832 3832fs

APPLICATIO S I FOR ATIO

between the top of the resistor divider network and the V

pin to create a pole-zero pair in the loop compensation.
The zero location is prior to the pole location and thus,
phase lead can be added to boost the phase margin at the
loop crossover frequency. The pole and zero locations are
located at:

ZC2

= 1/[2

(R2)(C2)] and

PC2

= 1/[2

(R1||R2)(C2)]

where R1||R2 is the parallel combination resistance of R1
and R2. For low R2/R1 ratios there is not much separa-
tion between f

CZ2

and f

PC2

. In this case, use multiple

capacitors with a high ESR · capacitance product to bring
f

ESR

close to f

. Choose C2 so that the zero is located at

a lower frequency compared to f

and the pole location

is high enough that the closed loop has enough phase
margin for stability. Figure 10c shows the Bode plot using
phase lead compensation around the LTC3832 resistor
divider network.

Although a mathematical approach to frequency compen-
sation can be used, the added complication of input and/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.

Table 2 shows the suggested compensation component
value for 3.3V to 2.5V applications based on Sanyo OS-CON
4SP820M low ESR output capacitors.

Table 2. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 820

F Sanyo OS-CON

4SP820M Output Capacitors

L1 (

OUT

(

)

(nF)

C1 (pF)

C2 (pF)

1.2

1640

9.1

4.7

560

1500

1.2

2460

4.7

330

1500

1.2

4100

3.3

270

1500

2.4

1640

4.7

330

1500

2.4

2460

3.3

220

1500

2.4

4100

2.2

180

1500

4.7

1640

3.3

120

1500

4.7

2460

2.2

100

1500

4.7

4100

2.2

100

1500

Table 3 shows the suggested compensation component
values for 3.3V to 2.5V applications based on 470

F Sanyo

POSCAP 4TPB470M output capacitors.

Table 3. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 470

F Sanyo POSCAP

4TPB470M Output Capacitors

L1 (

OUT

(

)

(

C1 (pF)

1.2

1410

0.0047

100

1.2

2820

0.0018

1.2

4700

0.0015

2.4

1410

0.0033

2.4

2820

0.0022

2.4

4700

0.001

4.7

1410

0.0022

4.7

2820

150

0.0015

4.7

4700

220

0.0015

Table 4 shows the suggested compensation component
values for 3.3V to 2.5V applications based on 1500

Sanyo MV-WX output capacitors.

Table 4. Recommended Compensation Network for 3.3V to 2.5V
Applications Using Multiple Paralleled 1500

F Sanyo MV-WX

Output Capacitors

L1 (

OUT

(

)

(

C1 (pF)

1.2

4500

0.0042

180

1.2

6000

0.0033

120

1.2

9000

0.0033

100

2.4

4500

0.0033

2.4

6000

100

0.0022

2.4

9000

150

0.0022

4.7

4500

120

0.0022

4.7

6000

220

0.0022

4.7

9000

220

0.0015

LAYOUT CONSIDERATIONS

When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3832.
These items are also illustrated graphically in the layout
diagram of Figure 11. The thicker lines show the high
current paths. Note that at 10A current levels or above,
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 10A.

LTC3832/LTC3832-1

sn3832 3832fs

APPLICATIO S I FOR ATIO

1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.

2. The GND and PGND pins should be shorted directly at
the LTC3832. This helps to minimize internal ground dis-
turbances in the LTC3832 and prevent differences in ground
potential from disrupting internal circuit operation. This
connection should then tie into the ground plane at a single
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFET Q2. Do not tie this single point ground in the trace
run between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.

3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!

4. The V

, PV

CC1

and PV

CC2

decoupling capacitors should

be as close to the LTC3832 as possible. The 4.7

F and 1

bypass capacitors shown at V

, PV

CC1

and PV

CC2

will help

provide optimum regulation performance.

5. The (+) plate of C

should be connected as close as

possible to the drain of the upper MOSFET, Q1. An additional
1

F ceramic capacitor between V

and power ground is

recommended.

6. The SENSE and V

pins are very sensitive to pickup from

the switching node. Care should be taken to isolate SENSE
and V

from possible capacitive coupling to the inductor

switching signal. Connecting the SENSE

and SENSE

to the load can significantly improve load regulation.

7. Kelvin sense I

MAX

and I

at Q1's drain and source pins.

CC1

MAX

SENSE

FREQSET

SHDN

COMP

LTC3832

CC2

GND

PGND

GND

100

Q1A

PGND

Q1B

OUT

3832 F11

OUT

4.7

0.1

PGND

Figure 11. Typical Schematic Showing Layout Considerations

LTC3832/LTC3832-1

sn3832 3832fs

Efficiency vs Load Current

Figure 12. Typical 3.3V to 2.5V, 14A Application

MAX

PGND

GND

SENSE

FREQSET

SHDN

COMP

CC2

1N5817

OPTIONAL

1N5817

5.6k

0.1

1.3

: SANYO 6TPB330M

OUT

: SANYO 4TPB470M

D1: MBRS330T3
L

: SUMIDA CDEP105-1R3-MC-S

Q1A, Q1B, Q2: FAIRCHILD FDS6670A

OUT

470

OUT

2.5V
14A

3.3V

3832 F12a

Q1A, Q1B
2 IN PARALLEL

0.1

LTC3832

SHDN

4.7

12V
1N5242

CC1

SENSE

330

C1
180pF

0.01

100

1500pF

18k

LOAD CURRENT (A)

EFFICIENCY (%)

100

10 11

3832 F12b

1 2 3

5 6 7

8 9

12 13 14 15

= 25

= 3.3V

OUT

= 2.5V

REFER TO FIGURE 12

APPLICATIO S I FOR ATIO

LTC3832/LTC3832-1

sn3832 3832fs

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

PACKAGE DESCRIPTIO

GN16 (SSOP) 0502

.229 .244

(5.817 6.198)

.150 .157**

(3.810 3.988)

16 15 14 13

.189 .196*

(4.801 4.978)

12 11 10 9

.016 .050

(0.406 1.270)

.015

.004

(0.38

0.10)

TYP

.007 .0098

(0.178 0.249)

.053 .068

(1.351 1.727)

.008 .012

(0.203 0.305)

.004 .0098

(0.102 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 TYP

.0165

.0015

.045

.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:
1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC3832/LTC3832-1

sn3832 3832fs

PACKAGE DESCRIPTIO

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.016 .050

(0.406 1.270)

.010 .020

(0.254 0.508)

TYP

.008 .010

(0.203 0.254)

SO8 0502

.053 .069

(1.346 1.752)

.014 .019

(0.355 0.483)

TYP

.004 .010

(0.101 0.254)

.050

(1.270)

BSC

N/2

.150 .157

(3.810 3.988)

NOTE 3

.189 .197

(4.801 5.004)

NOTE 3

.228 .244

(5.791 6.197)

.245

MIN

N/2

.160

.005

RECOMMENDED SOLDER PAD LAYOUT

.045

.005

.050 BSC

.030

.005

TYP

INCHES

(MILLIMETERS)

NOTE:
1. DIMENSIONS IN

2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3832/LTC3832-1

sn3832 3832fs

LINEAR TECHNOLOGY CORPORATION 2002

LT/TP 1002 2K · PRINTED IN USA

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Current Mode Ensures Accurate Current Sensing V

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Low Input Voltage, High Power, No R

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Minimum V

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MOSFETs

LTC3831

High Power Synchronous Switching Regulator Controller for

OUT

Tracks 1/2 of V

or External Reference

DDR Memory Termination

No R

SENSE

is a trademark of Linear Technology Corporation.

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

MAX

PGND

GND

SENSE

FREQSET

SHDN

COMP

CC2

MBR0530T1

20k

100

0.1

1.3

: SANYO 6TPB330M

OUT

: SANYO 4TPB470M

: SUMIDA CDEP105-1R3-MC-S

Q1A, Q1B, Q2: ON SEMICONDUCTOR MTD20N03HDL

OUT

470

45k
1%

10k
1%

3.3V
10A

3830 TA02

Q1A, Q1B
2 IN PARALLEL

LTC3832

SHUTDOWN

4.7

CC1

SENSE

330

0.1

C1
180pF

0.01

18k

Typical 5V to 3.3V, 10A Application

TYPICAL APPLICATIO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3832

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3832