LTC6241/LTC6242
1
62412f
Dual/Quad 18MHz, Low
Noise, Rail-to-Rail,
CMOS Op Amps
The LTC
6241/LTC6242 are dual and quad low noise,
low offset, rail-to-rail output, unity gain stable CMOS op
amps that feature 1pA of input bias current. The 0.1Hz to
10Hz noise of only 550nV
P-P
, along with an offset of just
125V make them uncommon among traditional CMOS
op amps. Additionally, noise is guaranteed to be less
than 10nV/Hz at 1kHz. An 18MHz gain bandwidth, and
10V/s slew rate, along with the wide supply range and
low input capacitance, make them perfect for use as fast
signal processing amplifi ers.
These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
range in low supply applications. The input common mode
range extends to the negative supply. They are fully speci-
fi ed on 3V and 5V, and an HV version guarantees operation
on supplies up to 5.5V.
The LTC6241 is available in the 8-pin SO, and for compact
designs it is packaged in the tiny dual fi ne pitch leadless
(DFN) package. The LTC6242 is available in the 16-Pin
SSOP as well as the 5mm 3mm DFN package.
Photo Diode Amplifi ers
Charge Coupled Amplifi ers
Low Noise Signal Processing
Active Filters
Medical Instrumentation
High Impedance Transducer Amplifi er
0.1Hz to 10Hz Noise: 550nV
P-P
Input Bias Current: 1pA (Typ at 25C)
Low Offset Voltage: 125V Max
Low Offset Drift: 2.5V/C Max
Voltage Gain: 124dB Typ
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
2.8V to 6V LTC6241/LTC6242
2.8V to 5.5V LTC6241HV/LTC6242HV
Low Input Capacitance
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
Quad LTC6242 in 16-Pin SSOP and 5mm 3mm
DFN Packages
Low Noise Single-Ended Input to Differential Output Amplifi er
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
+
R2
200k
C1
10pF
C2
10pF
+2.5V
2.5V
6241 TA01a
R4
4.99k
R1
200k
V
IN
V
OUT
+
V
OUT
1/2
LTC6241
+
1/2
LTC6241
C3
10pF
R3
4.99k
C4
10pF
FREQUENCY (Hz)
20
10
NOISE VOLTAGE (nV/
Hz)
30
40
50
60
1
100
1k
100k
6241 TA01b
0
10
10k
T
A
= 25
C
V
S
=
2.5V
V
CM
= 0V
Noise Voltage vs Frequency
LTC6241/LTC6242
2
62412f
Total Supply Voltage (V
+
to V
)
LTC6241/LTC6242
..................................................7V
LTC6241HV/LTC6242HV
.......................................12V
Input Voltage .......................... (V
+
+ 0.3V) to (V
0.3V)
Input Current ........................................................10mA
Output Short Circuit Duration (Note 2) ............ Indefi nite
Operating Temperature Range (Note 3) ... 40C to 85C
(Note 1)
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
Specifi ed Temperature Range (Note 4) .... 40C to 85C
Junction Temperature ........................................... 150C
DHC, DD Package ............................................. 125C
Storage Temperature Range ....................65C to 150C
DHC, DD Package ...............................65C to 125C
Lead Temperature (Soldering, 10 sec) .................. 300C
TOP VIEW
DD PACKAGE
8-LEAD (3mm
3mm) PLASTIC DFN
5
6
7
8
4
3
2
1
OUT A
IN A
+IN A
V
V
+
OUT B
IN B
+IN B
B
A
T
JMAX
= 125C,
JA
= 43C/W
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
1
2
3
4
8
7
6
5
TOP VIEW
V
+
OUT B
IN B
+IN B
OUT A
IN A
+IN A
V
S8 PACKAGE
8-LEAD PLASTIC SO
B
A
T
JMAX
= 150C,
JA
= 190C/W
ORDER PART
NUMBER
DD PART
MARKING*
LTC6241CDD
LTC6241HVCDD
LTC6241IDD
LTC6241HVIDD
LBPD
LBRR
LBPD
LBRR
ORDER PART
NUMBER
S8 PART
MARKING
LTC6241CS8
LTC6241HVCS8
LTC6241IS8
LTC6241HVIS8
6241
6241HV
6241I
241HVI
16
15
14
13
12
11
10
9
17
1
2
3
4
5
6
7
8
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
NC
OUT A
IN A
+IN A
V
+
+IN B
IN B
OUT B
NC
TOP VIEW
DHC16 PACKAGE
16-LEAD (5mm
3mm) PLASTIC DFN
B
A
C
D
T
JMAX
= 125C,
JA
= 43C/W
UNDERSIDE METAL CONNECTED TO V
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
OUT A
IN A
+IN A
V
+
+IN B
IN B
OUT B
NC
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
NC
B
A
C
D
T
JMAX
= 150C,
JA
= 135C/W
ORDER PART
NUMBER
DHC PART
MARKING*
LTC6242CDHC
LTC6242HVCDHC
LTC6242IDHC
LTC6242HVIDHC
6242
6242HV
6242
6242HV
ORDER PART
NUMBER
GN PART
MARKING
LTC6242CGN
LTC6242HVCGN
LTC6242IGN
LTC6242HVIGN
6242
6242HV
6242I
242HVI
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
*The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
LTC6241/LTC6242
3
62412f
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
denotes the
specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at T
A
= 25C. V
S
= 5V, 0V, V
CM
= 2.5V
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 5)
SO-Package
0C to 70C
40C to 85C
40
125
250
300
V
V
V
GN Package
0C to 70C
40C to 85C
50
150
275
300
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
100
550
650
725
V
V
V
V
OS
Match Channel-to-Channel (Note 6)
SO-8 Package
0C to 70C
40C to 85C
40
160
300
375
V
V
V
GN Package
0C to 70C
40C to 85C
50
185
325
400
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
150
650
700
750
V
V
V
TC V
OS
Input Offset Voltage Drift (Note 7)
0.7
2.5
V/C
I
B
Input Bias Current (Notes 5, 8)
1
75
pA
pA
PART NUMBER
AMPS/PACKAGE
SPECIFIED TEMP RANGE
SPECIFIED SUPPLY VOLTAGE
PACKAGE
PART MARKING
LTC6241CS8
2
0C to 70C
3V, 5V
SO-8
6241
LTC6241CDD
2
0C to 70C
3V, 5V
DD
LBPD
LTC6241HVCS8
2
0C to 70C
3V, 5V, 5V
SO-8
6241HV
LTC6241HVCDD
2
0C to 70C
3V, 5V, 5V
DD
LBRR
LTC6241IS8
2
40C to 85C
3V, 5V
SO-8
6241I
LTC6241IDD
2
40C to 85C
3V, 5V
DD
LBPD
LTC6241HVIS8
2
40C to 85C
3V, 5V, 5V
SO-8
241HVI
LTC6241HVIDD
2
40C to 85C
3V, 5V, 5V
DD
LBRR
LTC6242CGN
4
0C to 70C
3V, 5V
GN
6242
LTC6242CDHC
4
0C to 70C
3V, 5V
DHC
6242
LTC6242HVCGN
4
0C to 70C
3V, 5V, 5V
GN
6242HV
LTC6242HVCDHC
4
0C to 70C
3V, 5V, 5V
DHC
6242HV
LTC6242IGN
4
40C to 85C
3V, 5V
GN
6242I
LTC6242IDHC
4
40C to 85C
3V, 5V
DHC
6242
LTC6242HVIGN
4
40C to 85C
3V, 5V, 5V
GN
242HVI
LTC6242HVIDHC
4
40C to 85C
3V, 5V, 5V
DHC
6242HV
AVAILABLE OPTIO S
U
LTC6241/LTC6242
4
62412f
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
denotes the
specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at T
A
= 25C. V
S
= 5V, 0V, V
CM
= 2.5V
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
OS
Input Offset Current (Notes 5, 8)
0.5
75
pA
pA
Input Noise Voltage
0.1Hz to 10Hz
550
nV
P-P
e
n
Input Noise Voltage Density
f = 1kHz
7
10
nV/Hz
i
n
Input Noise Current Density (Note 9)
0.56
fA/Hz
R
IN
Input Resistance
Common Mode
10
12
C
IN
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
0.5
3
pF
pF
V
CM
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CMRR
Common Mode Rejection
0V V
CM
3.5V
80
105
dB
CMRR Match
Channel-to-Channel (Note 6)
76
95
dB
A
VOL
Large Signal Voltage Gain
V
O
= 1V to 4V
R
L
= 10k to V
S
/2
0C to 70C
40C to 85C
425
300
200
1600
V/mV
V/mV
V/mV
V
O
= 1.5V to 3.5V
R
L
= 1k to V
S
/2
0C to 70C
40C to 85C
90
60
50
215
V/mV
V/mV
V/mV
V
OL
Output Voltage Swing Low (Note 10)
No Load
I
SINK
= 1mA
I
SINK
= 5mA
7
40
190
30
75
325
mV
mV
mV
V
OH
Output Voltage Swing High (Note 10)
No Load
I
SOURCE
= 1mA
I
SOURCE
= 5mA
11
45
190
30
75
325
mV
mV
mV
PSRR
Power Supply Rejection
V
S
= 2.8V to 6V, V
CM
= 0.2V
80
104
dB
PSRR Match
Channel-to-Channel (Note 6)
74
100
dB
Minimum Supply Voltage (Note 11)
2.8
V
I
SC
Short-Circuit Current
15
30
mA
I
S
Supply Current per Amplifi er
0C to 70C
40C to 85C
1.8
2.2
2.3
2.4
mA
mA
mA
GBW
Gain Bandwidth Product
Frequency = 20kHz, R
L
= 1k
13
18
MHz
SR
Slew Rate (Note 12)
A
V
= 2, R
L
= 1k
5
10
V/s
FPBW
Full Power Bandwidth (Note 13)
V
OUT
= 3V
P-P
, R
L
= 1k
0.53
1.06
MHz
t
s
Settling Time
V
STEP
= 2V, A
V
= 1, R
L
= 1k, 0.1%
1100
ns
LTC6241/LTC6242
5
62412f
(LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
denotes the
specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at T
A
= 25C. V
S
= 3V, 0V, V
CM
= 1.5V
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 5)
SO-8 Package
0C to 70C
40C to 85C
40
175
275
325
V
V
V
GN Package
0C to 70C
40C to 85C
60
200
275
325
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
100
550
650
725
V
V
V
V
OS
Match Channel-to-Channel (Note 6)
SO-8 Package
0C to 70C
40C to 85C
40
200
325
400
V
V
V
GN Package
0C to 70C
40C to 85C
60
225
325
400
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
150
650
700
750
V
V
V
I
B
Input Bias Current (Notes 5, 8)
1
75
pA
pA
I
OS
Input Offset Current (Notes 5, 8)
0.5
75
pA
pA
V
CM
Input Voltage Range
Guaranteed by CMRR
0
1.5
V
CMRR
Common Mode Rejection
0V V
CM
1.5V
78
100
dB
CMRR Match
Channel-to-Channel (Note 6)
76
95
dB
A
VOL
Large Signal Voltage Gain
V
O
= 1V to 2V
R
L
= 10k to V
S
/2
0C to 70C
40C to 85C
140
100
75
600
V/mV
V/mV
V/mV
V
OL
Output Voltage Swing Low (Note 10)
No Load
I
SINK
= 1mA
3
65
30
110
mV
mV
V
OH
Output Voltage Swing High (Note 10)
No Load
I
SOURCE
= 1mA
4
70
30
120
mV
mV
PSRR
Power Supply Rejection
V
S
= 2.8V to 6V, V
CM
= 0.2V
80
104
dB
PSRR Match
Channel-to-Channel (Note 6)
74
100
dB
Minimum Supply Voltage (Note 11)
2.8
V
I
SC
Short-Circuit Current
3
6
mA
I
S
Supply Current per Amplifi er
0C to 70C
40C to 85C
1.4
1.7
1.8
1.9
mA
mA
mA
GBW
Gain Bandwidth Product
Frequency = 20kHz, R
L
= 1k
12
17
MHz
LTC6241/LTC6242
6
62412f
(LTC6241HV/LTC6242HV)
The
denotes the specifi cations which apply over
the specifi ed temperature range, otherwise specifi cations are at T
A
= 25C. V
S
= 5V, 0V, V
CM
= 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
OS
Input Offset Voltage (Note 5)
SO-8 Package
0C to 70C
40C to 85C
50
175
275
325
V
V
V
GN Package
0C to 70C
40C to 85C
60
200
275
325
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
100
550
650
725
V
V
V
V
OS
Match Channel-to-Channel (Note 6)
SO-8 Package
0C to 70C
40C to 85C
50
200
325
400
V
V
V
GN Package
0C to 70C
40C to 85C
60
225
325
400
V
V
V
DD, DHC Packages
0C to 70C
40C to 85C
150
650
700
750
V
V
V
TC V
OS
Input Offset Voltage Drift (Note 7)
0.7
2.5
V/C
I
B
Input Bias Current (Notes 5, 8)
1
75
pA
pA
I
OS
Input Offset Current (Notes 5, 8)
0.5
75
pA
pA
Input Noise Voltage
0.1Hz to 10Hz
550
nV
P-P
e
n
Input Noise Voltage Density
f = 1kHz
7
10
nV/Hz
i
n
Input Noise Current Density (Note 9)
0.56
fA/Hz
R
IN
Input Resistance
Common Mode
10
12
C
IN
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
0.5
3
pF
pF
V
CM
Input Voltage Range
Guaranteed by CMRR
5
3.5
V
CMRR
Common Mode Rejection
5V V
CM
3.5V
83
105
dB
CMRR Match
Channel-to-Channel (Note 6)
76
95
dB
A
VOL
Large Signal Voltage Gain
V
O
= 3.5V to 3.5V
R
L
= 10k
0C to 70C
40C to 85C
775
600
500
2700
V/mV
V/mV
V/mV
R
L
= 1k
0C to 70C
40C to 85C
150
90
75
360
V/mV
V/mV
V/mV
V
OL
Output Voltage Swing Low (Note 10)
No Load
I
SINK
= 1mA
I
SINK
= 10mA
15
45
360
30
75
550
mV
mV
mV
V
OH
Output Voltage Swing High (Note 10)
No Load
I
SOURCE
= 1mA
I
SOURCE
= 10mA
15
45
360
30
75
550
mV
mV
mV
LTC6241/LTC6242
7
62412f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefi nitely.
Note 3: All versions of the LTC6241/LTC6242 are guaranteed functional
over the temperature range of 40C and 85C.
Note 4: The LTC6241C/LTC6241HVC, LTC6242C/LTC6242HVC are
guaranteed to meet specifi ed performance from 0C to 70C. They are
designed, characterized and expected to meet specifi ed performance from
40C to 85C, but are not tested or QA sampled at these temperatures.
The LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to meet
specifi ed performance from 40C to 85C.
Note 5: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6241/LTC6242; however,
high electrostatic discharge can damage or degrade the device. Use proper
ESD handling precautions.
Note 6: Matching parameters are the difference between the two amplifi ers
A and D and between B and C of the LTC6242; between the two amplifi ers
of the LTC6241. CMRR and PSRR match are defi ned as follows: CMRR
and PSRR are measured in V/V on the matched amplifi ers. The difference
(LTC6241HV/LTC6242HV)
The
denotes the specifi cations which apply over
the specifi ed temperature range, otherwise specifi cations are at T
A
= 25C. V
S
= 5V, 0V, V
CM
= 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PSRR
Power Supply Rejection
V
S
= 2.8V to 11V, V
CM
= 0.2V
85
110
dB
PSRR Match
Channel-to-Channel (Note 6)
82
106
dB
Minimum Supply Voltage (Note 11)
2.8
V
I
SC
Short-Circuit Current
15
35
mA
I
S
Supply Current per Amplifi er
0C to 70C
40C to 85C
2.5
3.2
3.3
3.7
mA
mA
mA
GBW
Gain Bandwidth Product
Frequency = 20kHz, R
L
= 1k
13
18
MHz
SR
Slew Rate (Note 12)
A
V
= 2, R
L
= 1k
5.5
10
V/s
FPBW
Full Power Bandwidth (Note 13)
V
OUT
= 3V
P-P
, R
L
= 1k
0.58
1.06
MHz
t
s
Settling Time
V
STEP
= 2V, A
V
= 1, R
L
= 1k, 0.1%
900
ns
is calculated between the matching sides in V/V. The result is converted
to dB.
Note 7: This parameter is not 100% tested.
Note 8: This specifi cation is limited by high speed automated test
capability. See Typical Characteristics curves for actual typical
performance.
Note 9: Current noise is calculated from the formula: i
n
= (2qI
B
)
1/2
where q = 1.6 10
19
coulomb. The noise of source resistors up to
50G dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 10: Output voltage swings are measured between the output and
power supply rails.
Note 11: Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
Note 12: Slew rate is measured in a gain of 2 with R
F
= 1k and R
G
= 500. On the LTC6241/LTC6242, V
IN
is 1V and V
OUT
slew rate is
measured between 1V and +1V. On the LTC6241HV/LTC6242HV, V
IN
is
2V and V
OUT
slew rate is measured between 2V and +2V.
Note 13: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/2V
P
.
LTC6241/LTC6242
8
62412f
INPUT OFFSET VOLTAGE (
V)
0
NUMBER OF UNITS
10
30
40
50
90
6241 G01
20
60
70
80
70
50
30
10
70
30
50
10
V
S
=
2.5V
SO-8 PACKAGE
INPUT OFFSET VOLTAGE (
V)
0
NUMBER OF UNITS
40
120
6241 G02
20
60
100
80
350 250 150 50
350
150
250
50
V
S
=
2.5V
DD PACKAGE
DISTRIBUTION (
V/C)
0
NUMBER OF UNITS
4
16
14
12
6241 G03
2
6
10
8
1.0 0.6 0.2
0.2
1.8
1.0
1.4
0.6
V
S
=
2.5V
2 LOTS
55
C TO 125C
INPUT COMMON MODE VOLTAGE (V)
0.5
OFFSET VOLTAGE (
V)
300
200
250
150
100
0
50
50
100
150
200
250
300
3.0
6241 G05
0
0.5
1.5
2.5
3.5
1.0
2.0
4.5
4.0
V
S
= 5V, 0V
T
A
= 55
C
T
A
= 125
C
T
A
= 25
C
COMMON MODE VOLTAGE (V)
0
1.0
2.0
3.0
4.0
0.5
1.5
2.5
3.5
4.5 5.0
INPUT BIAS CURRENT (pA)
1000
100
10
1
6241 G06
V
S
= 5V, 0V
T
A
= 85
C
T
A
= 125
C
T
A
= 25
C
COMMON MODE VOLTAGE (V)
0.8 0.6
0.2
0.2
0.6
0.4
0
0.4
0.8 1.0
INPUT BIAS CURRENT (pA)
700
100
200
300
400
500
600
400
300
200
100
0
6241 G07
V
S
= 5V, 0V
T
A
= 85
C
T
A
= 125
C
T
A
= 25
C
LOAD CURRENT (mA)
0.01
OUTPUT LOW SATURATION VOLTAGE (V)
0.1
0.1
10
100
6241 G09
0.001
1
10
1
V
S
= 5V, 0V
T
A
= 125
C
T
A
= 55
C
T
A
= 25
C
TEMPERATURE (
C)
25
45
65
85
105
35
55
75
95
115 125
INPUT BIAS CURRENT (pA)
1000
100
10
1
6241 G08
V
CM
= V
S
/2
V
S
= 5V
V
S
= 10V
TOTAL SUPPLY VOLTAGE (V)
0
2.0
2.5
3.0
6
10
6241 G04
1.5
1.0
2
4
8
12
0.5
0
SUPPLY CURRENT (mA)
3.5
T
A
= 55
C
T
A
= 125
C
T
A
= 25
C
V
OS
Distribution
V
OS
Distribution
V
OS
Temperature Coeffi cient
Distribution
Supply Current vs Supply Voltage
Offset Voltage vs Input Common
Mode Voltage
Input Bias Current vs Common
Mode Voltage
Input Bias Current vs
Common Mode Voltage
Input Bias Current vs Temperature
Output Saturation Voltage vs
Load Current (Output Low)
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
LTC6241/LTC6242
9
62412f
Output Saturation Voltage vs
Load Current (Output High)
Gain Bandwidth and Phase
Margin vs Temperature
Open Loop Gain vs Frequency
Gain Bandwidth and Phase
Margin vs Supply Voltage
Slew Rate vs Temperature
Output Impedance vs Frequency
Common Mode Rejection Ratio vs
Frequency
Channel Separation vs Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
LOAD CURRENT (mA)
OUTPUT HIGH SATURATION VOLTAGE (V)
0.1
0.1
10
100
6241 G10
0.01
1
10
1
V
S
= 5V, 0V
T
A
= 125
C
T
A
= 55
C
T
A
= 25
C
TEMPERATURE (
C)
55 35
5
45
85
15
25
65
105 125
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
70
30
40
50
60
0
10
20
30
40
6241 G12
C
L
= 5pF
R
L
= 1k
PHASE MARGIN
GAIN BANDWIDTH
V
S
=
1.5V
V
S
=
5V
V
S
=
1.5V
V
S
=
5V
TOTAL SUPPLY VOLTAGE (V)
0
4
8
2
6
10
12
GAIN BANDWIDTH (MHz)
PHASE MARGIN (DEG)
70
60
40
50
0
10
20
30
6241 G14
T
A
= 25
C
C
L
= 5pF
R
L
= 1k
PHASE MARGIN
GAIN BANDWIDTH
FREQUENCY (Hz)
10k
100k
10M
1M
100M
GAIN (dB)
PHASE (DEG)
20
0
10
10
20
30
40
50
60
70
80
80
40
60
20
0
20
40
60
80
100
120
6241 G13
C
L
= 5pF
R
L
= 1k
V
CM
= V
S
/2
PHASE
GAIN
V
S
=
1.5V
V
S
=
5V
V
S
=
1.5V
V
S
=
5V
TEMPERATURE (
C)
55 35
5
45
85
15
25
65
105 125
SLEW RATE (V/
s)
4
6
8
10
12
14
16
18
20
6241 G15
A
V
= 2
R
F
= 1k, R
G
= 500
CONDITIONS: SEE NOTE 12
V
S
=
5V RISING
V
S
=
5V FALLING
V
S
=
2.5V FALLING
V
S
=
2.5V RISING
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
)
10k
1M
10M
6241 G16
100k
T
A
= 25
C
V
S
=
2.5V
A
V
= 10
A
V
= 1
0.01
10
10k
1
0.10
100
1k
A
V
= 2
FREQUENCY (Hz)
10k
100k
10M
1M
100M
COMMON MODE REJECTION (dB)
10
0
10
20
30
40
50
60
70
100
90
80
6241 G17
T
A
= 25
C
V
S
=
2.5V
FREQUENCY (Hz)
10k
100k
10M
1M
100M
VOLTAGE GAIN (dB)
120
0
10
20
30
40
50
60
70
110
100
90
80
6241 G18
T
A
= 25
C
V
S
=
2.5V
A
V
= 1
Power Supply Rejection Ratio vs
Frequency
POWER SUPPLY REJECTION RATIO (dB)
90
80
70
60
50
40
30
20
10
0
1k
100k
1M
100M
10k
10M
FREQUENCY (Hz)
6241 G19
T
A
= 25
C
V
S
=
2.5V
POSITIVE SUPPLY
NEGATIVE SUPPLY
LTC6241/LTC6242
10
62412f
Input Capacitance vs Frequency
Minimum Supply Voltage
Output Short Circuit Current vs
Power Supply Voltage
Open Loop Gain
Open Loop Gain
Open Loop Gain
Offset Voltage vs Output Current
Warm-Up Drift vs Time
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
INPUT CAPACITANCE (pF)
16
14
12
10
8
6
4
2
0
1k
100k
1M
100M
10k
10M
FREQUENCY (Hz)
6241 G20
V
S
=
1.5V
C
CM
C
DM
TOTAL SUPPLY VOLTAGE (V)
0
2
6
1
4
8
3
7
5
9
10
CHANGE IN OFFSET VOLTAGE (
V)
100
20
40
60
80
100
80
40
60
20
0
6241 G21
V
CM
= V
S
/2
T
A
= 125
C
T
A
= 55
C
T
A
= 25
C
POWER SUPPLY VOLTAGE (
V)
1.5
2.5
4.5
2.0
3.5
3.0
4.0
5.0
OUTPUT SHORT-CIRCUIT CURRENT (mA)
50
10
20
30
40
50
40
20
30
10
0
6241 G22
SOURCING
SINKING
T
A
= 125
C
T
A
= 125
C
T
A
= 55
C
T
A
= 55
C
T
A
= 25
C
OUTPUT VOLTAGE (V)
0
0.5
2.5
1.5
1.0
2.0
3.0
INPUT VOLTAGE (
V)
120
100
20
40
60
80
0
6241 G23
T
A
= 25
C
V
S
= 3V, 0V
R
L
= 100k
R
L
= 10k
OUTPUT VOLTAGE (V)
0
1
2
5
3
4
INPUT VOLTAGE (
V)
120
100
20
40
60
80
20
0
6241 G24
T
A
= 25
C
V
S
= 5V, 0V
R
L
= 1k
R
L
= 10k
OUTPUT VOLTAGE (V)
5 4
0
2
3
1
5
1
2
3
4
INPUT VOLTAGE (
V)
100
20
40
60
80
60
40
20
0
6241 G25
T
A
= 25
C
V
S
=
5V
R
L
= 1k
R
L
= 10k
OUTPUT CURRENT (mA)
50 40 30 20 10
10
30
20
0
40 50
OFFSET VOLTAGE (
V)
500
400
100
200
300
500
400
300
100
200
0
6241 G26
T
A
= 125
C
T
A
= 55
C
T
A
= 25
C
V
S
=
5V
TIME AFTER POWER UP (s)
0
10
30
20
5
40
60
50
15
35
25
45
55
CHANGE IN OFFSET VOLTAGE (
V)
25
15
20
5
0
10
5
6241 G27
T
A
= 25
C
V
S
=
1.5V
V
S
=
2.5V
V
S
=
5V
FREQUENCY (Hz)
20
10
NOISE VOLTAGE (nV/
Hz)
30
40
50
60
1
100
1k
100k
6241 G28
0
10
10k
T
A
= 25
C
V
S
=
2.5V
V
CM
= 0V
Noise Voltage vs Frequency
LTC6241/LTC6242
11
62412f
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
60
50
40
30
20
10
0
100
1000
6241 G29
R
S
= 50
R
S
= 10
V
S
=
2.5V
A
V
= 1
R
S
1k
1k
C
L
75pF
+
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
60
50
40
30
20
10
0
100
1000
6241 G30
R
S
= 50
R
S
= 10
V
S
=
2.5V
A
V
= 2
R
S
500
1k
C
L
75pF
+
OUTPUT STEP (V)
4
2
3
3
1
0
1
2
4
SETTLING TIME (
s)
3.5
1.5
2.0
2.5
3.0
0
0.5
1.0
6241 G31
10mV
1mV
10mV
1mV
T
A
= 25
C
V
S
=
5V
A
V
= 1
V
OUT
V
IN
1k
+
3.0
1.5
2.0
2.5
0
0.5
1.0
OUTPUT STEP (V)
4
2
3
3
1
0
1
2
4
SETTLING TIME (
s)
6241 G32
10mV
1mV
10mV
1mV
T
A
= 25
C
V
S
=
5V
A
V
= 1
V
OUT
V
IN
1k
+
1k
1k
FREQUENCY (Hz)
10k
100k
1M
10M
OUTPUT VOLTAGE SWINGING (V
P-P
)
10
7
4
1
8
5
2
9
6
3
6241 G33
T
A
= 25
C
V
S
=
5V
HD
2
, HD
3
< 40dBc
A
V
= +2
A
V
= 1
Series Output Resistance and
Overshoot vs Capacitive Load
Series Output Resistance and
Overshoot vs Capacitive Load
Settling Time vs Output Step
(Non-Inverting)
Settling Time vs Output Step
(Inverting)
Maximum Undistorted Output
Signal vs Frequency
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
0.1Hz to 10Hz Voltage Noise
TIME (1s/DIV)
VOLTAGE NOISE (200nV/DIV)
6241 G11
V
S
= 5V, 0V
FREQUENCY (Hz)
1
NOISE CURRENT (pA/
Hz)
10
100
10k
100k
6241 G42
0.1
1k
1000
100
T
A
= 25
C
V
S
=
2.5V
V
CM
= 0V
Noise Current vs Frequency
LTC6241/LTC6242
12
62412f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Distortion vs Frequency
Distortion vs Frequency
FREQUENCY (Hz)
10k
100k
1M
10M
DISTORTION (dBc)
30
60
90
100
50
80
40
70
6241 G34
V
S
=
2.5V
A
V
= 1
V
OUT
= 2V
P-P
R
L
= 1k, 2ND
R
L
= 1k, 3RD
FREQUENCY (Hz)
10k
100k
1M
10M
DISTORTION (dBc)
30
60
90
100
50
80
40
70
6241 G35
V
S
=
5V
A
V
= 1
V
OUT
= 2V
P-P
R
L
= 1k, 2ND
R
L
= 1k, 3RD
Distortion vs Frequency
FREQUENCY (Hz)
10k
100k
1M
10M
DISTORTION (dBc)
30
60
90
100
50
80
40
70
6241 G37
V
S
=
5V
A
V
= 2
V
OUT
= 2V
P-P
R
L
= 1k, 2ND
R
L
= 1k, 3RD
Distortion vs Frequency
FREQUENCY (Hz)
10k
100k
1M
10M
DISTORTION (dBc)
30
60
90
100
50
80
40
70
6241 G36
V
S
=
2.5V
A
V
= 2
V
OUT
= 2V
P-P
R
L
= 1k, 2ND
R
L
= 1k, 3RD
LTC6241/LTC6242
13
62412f
Large Signal Response
Large Signal Response
Output Overdrive Recovery
V
S
=
2.5V
A
V
= 1
R
L
= 1k
6241 G40
0V
V
S
=
2.5V
A
V
= 3
R
L
=
500ns/DIV
6241 G41
0V
0V
V
IN
(1V/DIV)
V
OUT
(2V/DIV)
V
S
=
5V
A
V
= 1
R
L
=
6241 G39
0V
Small Signal Response
V
S
=
2.5V
A
V
= 1
R
L
=
6241 G38
0V
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
LTC6241/LTC6242
14
62412f
APPLICATIO S I FOR ATIO
W
U
U
U
Amplifi er Characteristics
Figure 1 is a simplifi ed schematic of the LTC6241, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Capacitor C1 reduces the unity cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifi er. Capacitor Cm sets the overall
amplifi er gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifi er connected as a voltage
follower. If the negative going input signal is less than
a diode drop below V
, no phase inversion occurs. For
input signals greater than a diode drop below V
, limit the
current to 3mA with a series resistor R
S
to avoid phase
inversion.
ESD
The LTC6241 has reverse-biased ESD protection diodes
on all input and outputs as shown in Figure 1. If these
pins are forced beyond either supply, unlimited current
will fl ow through these diodes. If the current is transient
and limited to one hundred milliamps or less, no damage
to the device will occur.
The amplifi er input bias current is the leakage current of
these ESD diodes. This leakage is a function of the tem-
perature and common mode voltage of the amplifi er, as
shown in the Typical Performance Curves.
Noise
The LTC6241 exhibits exceptionally low 1/f noise in the
0.1Hz to 10Hz region. This 550nV
P-P
noise allows these
op amps to be used in a wide variety of high impedance
low frequency applications, where Zero-Drift amplifi ers
might be inappropriate due to their charge injection.
In the frequency region above 1kHz the LTC6241 also
show good noise voltage performance. In this frequency
region, noise can easily be dominated by the total source
resistance of the particular application. Specifi cally, these
amplifi ers exhibit the noise of a 3.1k resistor, meaning it
is desirable to keep the source and feedback resistance at
or below this value, i.e. R
S
+ R
G
||R
FB
3.1k. Above this
total source impedance, the noise voltage is not dominated
by the amplifi er.
Noise current can be estimated from the expression i
n
=
2qI
B
, where q = 1.6 10
19
coulombs. Equating 4kTRf
and R2qI
B
f shows that for source resistors below 50G
the amplifi er noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
Figure 1. Simplifi ed Schematic
Figure 2. Unity Gain Follower Test Circuit
R2
Q2
6241 F01
V
IN
+
I
TAIL
V
IN
V
O
V
+
V
+
V
V
V
CM
DESD5
DIFFERENTIAL
DRIVE
GENERATOR
BIAS
DESD6
V
+
DESD2
V
+
DESD4
V
DESD1
V
DESD3
R1
Q1
M2
M1
M3
M4
C1
+2.5V
2.5V
6241 F02
+
1/2
LTC6241
R
S
V
IN
V
OUT
V
OUT
AND V
IN
OF FOLLOWER WITH LARGE INPUT OVERDRIVE
V
DD
=
+2.5V
V
SS
=
2.5V
LTC6241/LTC6242
15
62412f
APPLICATIO S I FOR ATIO
W
U
U
U
Proprietary design techniques are used to obtain simul-
taneous low 1/f noise and low input capacitance. Low
input capacitance is important when the amplifi er is used
with high source and feedback resistors. High frequency
noise from the amplifi er tail current source, I
TAIL
in Fig-
ure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifi er of Figure 11 on the last
page of this data sheet shows the noise results from the
LTC6241 and the results of a competitive CMOS amplifi er.
The LTC6241 output is the ideal noise of a 1M resistor
at room temperature, 130nVHz.
Half the Noise
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifi ers the noise
voltage can be lowered by 4, or half as much noise. The
comes about from an RMS summing of uncorrelated
noise sources. This circuit maintains extremely high input
resistance, and has a 250 output resistance. For lower
output resistance, a buffer amplifi er can be added without
infl uencing the noise.
Stability
The good noise performance of these op amps can be at-
tributed to large input devices in the differential pair. Above
several hundred kilohertz, the input capacitance rises and
can cause amplifi er stability problems if left unchecked.
When the feedback around the op amp is resistive (R
F
), a
pole will be created with R
F
, the source resistance, source
capacitance (R
S
, C
S
), and the amplifi er input capacitance.
In low gain confi gurations and with R
F
and R
S
in even
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor C
F
in parallel with R
F
eliminates this problem.
Low Noise Single-Ended Input to Differential Output
Amplifi er
The circuit on the fi rst page of the data sheet is a low noise
single-ended input to differential output amplifi er, with a
200k input impedance. The very low input bias current
of the LTC6241 allows for these large input and feedback
resistors. The 200k resistors, R1 and R2, along with C1
and C2 set the 3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
Figure 3. Parallel Amplifi er Lowers Noise by 2x
Figure 4. Compensating Input Capacitance
+
C
IN
C
S
6241 F04
R
F
R
S
OUTPUT
C
F
10
6241 F03
+
1/4
LTC6242
1k
1k
10
+
1/4
LTC6242
1k
1k
10
+
1/4
LTC6242
1k
1k
10
+
1/4
LTC6242
1k
1k
+2.5
2.5
V
IN
V
O
LTC6241/LTC6242
16
62412f
APPLICATIO S I FOR ATIO
W
U
U
U
phase lead to compensate the phase lag of the second
amplifi er. The op amp's good input offset voltage match
and low input bias current means that the typical differential
output voltage is less than 40V. A noise spectrum plot of
the differential output is shown in Figure 5.
gain of the difference amplifi er is one. An LTC6910-2 PGA
amplifi es the difference amplifi er output with inverting
gains of 1, 2, 4, 8, 16, 32 and 64. The second
LTC6241 op amp is used as an integrator to set the DC
output voltage equal to the LT6650 reference voltage V
REF
.
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
can be set to a voltage from 400mV to V
+
350mV with
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
contribute any signifi cant error to the LT6650 reference
voltage. The LT6650 V
REF
voltage has a maximum error
Figure 5. Differential Output Noise
FREQUENCY (kHz)
0
20
60
10
40
80
30
70
50
90 100
DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/
Hz) 140
60
80
100
120
0
20
40
6241 F05
V
S
=
2.5V
T
A
= 25
C
3dB BW = 80kHz
Achieving Low Input Bias Current
The DD package is leadless and makes contact to the PCB
beneath the package. Solder fl ux used during the attach-
ment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
of the part. All inputs are susceptible because the backside
paddle is connected to V
internally. As the input voltage
changes or if V
changes, a leakage path can be formed
and alter the observed input bias current. For lowest bias
current, use the LTC6241 in the SO-8 and provide a guard
ring around the inputs that are tied to a potential near the
input voltage.
A Digitally Programmable AC Difference Amplifi er
The LTC6241 confi gured as a difference amplifi er, can
be combined with a programmable gain amplifi er (PGA)
to obtain a low noise high speed programmable differ-
ence amplifi er. Figure 6 shows the LTC6241 based as a
single-supply AC amplifi er. One LTC6241 op amp is used
at the circuit's input as a standard four resistor difference
amplifi er. The low bias current and current noise of the
LTC6241 allow the use of high valued input resistors, 100k
or greater. Resistors R1, R2, R3 and R4 are equal and the
Figure 6. Wideband Difference Amplifi er with High
Input Impedance and Digitally Programmable Gain
6241 F06
R4
R3
R2
+
1/2
LTC6241
C1
C2
1
F
0.1
F
8
7
6
5
G2
G1
G0
1
1
2
2
3
4
AGND
OUT
IN
V
V
+
0.1
F
V
+
V
+
R1
R1 = R2 = R3 = R4
V2
V1
R5
1k
1000pF
3
4
5
R6
20k
LTC6910-2
LT6650
V
OUT
V
REF
+
1/2
LTC6241
C3
R7
100
1
F
DIGITAL INPUTS
G1
G2
GO
GAIN
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
V
OUT
= (V1 V2) GAIN + V
REF
(
)
V
R
R
R
k
V
REF
REF
=
+
=
(
)
=
0 4
5
6
1
5 10
5
2
R6 20
.
k
d BANDWIDTH
f
f
f
R
C
HIGH
LOW
HIGH
3
1
2
3
=
=
1
2
7
3
f
GAIN
R
C
LOW
=
LTC6241/LTC6242
17
62412f
of 2% with 1% resistors. The upper 3dB frequency of
the amplifi er is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower 3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower 3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the V
REF
voltage. At the maximum gain setting of
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice V
REF
divided by 64.
Example Design: Design a programmable gain AC differ-
ence amplifi er, with a bandwidth 10Hz to 100kHz, an input
impedance equal or greater than 100k, and an output
DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
b. If the upper 3dB frequency is 100kHz then C1 = 1/(2
R2 f3dB) = 1/(6.28 100k 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower 3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2 R7 f3dB) = 64/(6.28 100k 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
V
REF
= 0.4(R5/R6 + 1), so R5 = R6(2.5V
REF
1). For
R6 = 20k, R5 = 30k
With
V
REF
= 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
APPLICATIO S I FOR ATIO
W
U
U
U
40nVpp Noise, 0.05V/C Drift, Chopped FET
Amplifi er
Figure 7's circuit combines the 5V rail-to-rail performance
of the LTC6241 with a pair of extremely low noise JFETs
confi gured in a chopper based carrier modulation scheme
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799's output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelated to 60Hz, provides excellent immunity to harmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1's square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifi er.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1V offset specifi cation.
The noise measured over a 50 second interval, in Figure 8,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET's die size and current density.
LTC6241/LTC6242
18
62412f
HORIZ = 5s/DIV
6241 F08
VERT = 20nV/DIV
Figure 8. Noise in a 0.1Hz to 10Hz Bandwidth
APPLICATIO S I FOR ATIO
W
U
U
U
+
+
BIAS
10M
1
F
14
15
16
3
2
1
S4
S3
240k
1
F
OUTPUT
A2
LTC6241HV
A1
LTC6241HV
1
F
INPUT
10k
8
7
11
S1
S2
9
6
10
R2
10k
R1
10
NOISE
OFFSET
DRIFT
OPEN-LOOP GAIN
I
= 40nV
P-P
0.1Hz TO 10Hz
= 1
V
= 0.05
V/C
R2
10
= 10
= 500pA
+1
GAIN =
9
0.01
F
1
1
2
2
6241 F07
= 0.1% METAL FILM RESISTOR
= 1% METAL FILM RESISTOR
*
**
= LTC201 QUAD
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
1
F
DIV
R
SET
LTC1799
V
+
74C90
10
18.5kHz
OUT
74C74
2
TO
1
POINTS
TO
2
POINTS
Q
Q
54.2k*
TO LTC201 V
+
PIN
5V
5V
5V
5V
5V
925Hz
TO LTC201 V
PIN
1
F
898
**
5V
5V
898
**
LSK389
3k
499
**
+
+
Figure 7. Ultra Low Noise Chopper Amplifi er
LTC6241/LTC6242
19
62412f
APPLICATIO S I FOR ATIO
W
U
U
U
Low Noise Shock Sensor Amplifi ers
Figures 9 and 10 show the LTC6241 realizing two different
approaches to amplifying signals from a capacitive sensor.
The sensor in both cases is a 770pF piezoelectric shock
sensor accelerometer, which generates charge under
physical acceleration.
Figure 9 shows the classical "charge amplifi er" approach.
The LTC6241 is in the inverting confi guration so the sensor
looks into a virtual ground. All of the charge generated
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the sensor, it will be forced to
100 times what would have been the sensor's open circuit
voltage. So the circuit gain is 100. The benefi t of this ap-
proach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifi er. Hence this circuit is favored for remote
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
MAIN
GAIN-SETTING
ELEMENT IS A
CAPACITOR
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
CABLE HAS
UNKNOWN C
R
f
1G
6241 F09
V
OUT
= 110mV/g
+
1/2
LTC6241
C
f
7.7pF
Figure 9. Classical Inverting Charge Amplifi er
accelerometers where the cable length may vary. Diffi culties
with the circuit are inaccuracy of the gain setting with the
small capacitor, and low frequency cutoff due to the bias
resistor working into the small feedback capacitor.
Figure 10 shows a non-inverting amplifi er approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capaci-
tor. Second, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF sensor, rather
than into a small feedback capacitor, for lower frequency
response. Third, the non-inverting topology can be paral-
leled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasitic capacitance at the input reduces the gain slightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
1G
V
S
+
6241 F10
10k
1k
1k
100
V
OUT
= 110mV/g
V
S
=
1.4V to 5.5V
BW = 0.2Hz to 10kHz
V
OUT
+
1/2
LTC6241HV
V
S
10k
100
+
1/2
LTC6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
Figure 10. Low Noise Non-Inverting Shock Sensor Amplifi er
LTC6241/LTC6242
20
62412f
PACKAGE DESCRIPTIO
U
DHC Package
16-Lead Plastic DFN (5mm 3mm)
(Reference LTC DWG # 05-08-1706)
3.00
0.10
(2 SIDES)
5.00
0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40
0.10
BOTTOM VIEW--EXPOSED PAD
1.65
0.10
(2 SIDES)
0.75
0.05
R = 0.115
TYP
R = 0.20
TYP
4.40
0.10
(2 SIDES)
1
8
16
9
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 0.05
(DHC16) DFN 1103
0.25
0.05
PIN 1
NOTCH
0.50 BSC
4.40
0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65
0.05
(2 SIDES)
2.20
0.05
0.50 BSC
0.65
0.05
3.50
0.05
PACKAGE
OUTLINE
0.25
0.05
LTC6241/LTC6242
21
62412f
PACKAGE DESCRIPTIO
U
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
1
2
3
4
5
6
7
8
.229 .244
(5.817 6.198)
.150 .157**
(3.810 3.988)
16 15 14 13
.189 .196*
(4.801 4.978)
12 11 10 9
.016 .050
(0.406 1.270)
.015
.004
(0.38
0.10)
45
0
8 TYP
.007 .0098
(0.178 0.249)
.0532 .0688
(1.35 1.75)
.008 .012
(0.203 0.305)
TYP
.004 .0098
(0.102 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 .165
.0250 BSC
.0165
.0015
.045
.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC6241/LTC6242
22
62412f
DD Package
8-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1698)
PACKAGE DESCRIPTIO
U
3.00
0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38
0.10
BOTTOM VIEW--EXPOSED PAD
1.65
0.10
(2 SIDES)
0.75
0.05
R = 0.115
TYP
2.38
0.10
(2 SIDES)
1
4
8
5
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 0.05
(DD8) DFN 1203
0.25
0.05
2.38
0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65
0.05
(2 SIDES)
2.15
0.05
0.50
BSC
0.675
0.05
3.5
0.05
PACKAGE
OUTLINE
0.25
0.05
0.50 BSC
LTC6241/LTC6242
23
62412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
PACKAGE DESCRIPTIO
U
.016 .050
(0.406 1.270)
.010 .020
(0.254 0.508)
45
0
8 TYP
.008 .010
(0.203 0.254)
SO8 0303
.053 .069
(1.346 1.752)
.014 .019
(0.355 0.483)
TYP
.004 .010
(0.101 0.254)
.050
(1.270)
BSC
1
2
3
4
.150 .157
(3.810 3.988)
NOTE 3
8
7
6
5
.189 .197
(4.801 5.004)
NOTE 3
.228 .244
(5.791 6.197)
.245
MIN
.160
.005
RECOMMENDED SOLDER PAD LAYOUT
.045
.005
.050 BSC
.030
.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
LTC6241/LTC6242
24
62412f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 0605 500 PRINTED IN USA
1kHz
101kHz
10kHz/DIV
6241 TA02b
0V
30nV/
Hz PER DIV
1kHz
101kHz
6241 TA02c
10kHz/DIV
0V
30nV/
Hz PER DIV
TYPICAL APPLICATIO
U
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1151
15V Zero-Drift Op Amp
Dual High Voltage Operation 18V
LT1792
Low Noise Precision JFET Op Amp
6nV/Hz Noise, 15V Operation
LTC2050
Zero-Drift Op Amp
2.7 Volt Operation, SOT-23
LTC2051/LTC2052
Dual/Quad Zero-Drift Op Amp
Dual/Quad Version of LTC2050 in MS8/GN16 Packages
LTC2054/LTC2055
Single/Dual Zero-Drift Op Amp
Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
Figure 11. Ultralow Noise 1M 150kHz Photodiode Amplifi er
LTC6241 Output Noise Spectrum. 1M Resistor Noise
Dominates; Ideal Performance
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
R2
1.69k
C3
180pF
C1
1500pF
+1.5V
1.5V
1.5V
SFH213FA
OR EQUIVALENT
(
4pF)
6241 TA02a
R
F
1M
R1
866
+
1/2
LTC6241
+
1/2
LTC6241
C2
1500pF
C
F
1pF
1M
TIA
150kHz 3RD ORDER BUTTERWORTH FILTER
R3
2k
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