DB08-000156-00
August 2001
1 of 24
Copyright 2000, 2001 by LSI Logic Corporation. All rights reserved.
G12TM-p Ultra160 SCSI
Transceiver, 160 Mbytes/s
SCSI Bus Transfer Rate
Datasheet
The Ultra160 SCSI
1
transceiver and associated cells provide up to
160 Mbytes/s of on-chip input/output (I/O) signaling for
application-specific integrated circuit (ASIC) chips implemented in the
LSI Logic G12TM-p 0.13
m process technology. An Ultra160 SCSI bus
system built into an ASIC requires the following cell types:
1. SCSI: Small Computer System Interface. The Ultra160 transceiver is compatible with the
ANSI SCSI Parallel Interface-3 (SPI-3) specification.
Cell Type
Name
Function
Transceiver
scsiulvdls33
Differential bidirectional SCSI signaling
Bias
Generator
scsibiasls33
Sets operating level of SCSI transceivers
DIFFSENS
Receiver
scsisensehm
Detects SCSI bus operating mode
ddrvscsi5ls33
ESD-protected I/O pad cell used for the
DIFFSENS input from the SCSI bus
scsivdd
Dedicated 3.3 V power pad cell
scsivss
Dedicated 3.3 V ground pad cell
Power-On-Reset
Signal Generator
scsipora
Sets transceivers to high-impedance
mode at power-up
Support
cornerg12scsi33
SCSI corner cell
pvddioscsi33
3.3 V SCSI I/O power pad cell
pvssioscsils33
3.3 V SCSI I/O ground pad cell
pvddscsi33
1.8 V core power pad cell
pvssscsi33
1.8 V core ground pad cell
dvddscsi33
3.3 V ESD protection cell
dvdd2scsi33
1.8 V ESD protection cell
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G12TM-p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate
DB08-000156-00
August 2001
Copyright 2000, 2001 by LSI Logic Corporation. All rights reserved.
Features and Benefits
General Description
ASIC applications use the on-chip Ultra160
scsiulvdls33
transceivers
to perform various SCSI I/O signaling (
Figure 1
). When combined with
the other required Ultra160 SCSI cells, the transceivers can form
complete SCSI I/O parallel buses. An 8-bit bus, commonly known as a
narrow bus, uses 18
scsiulvdls33
transceivers. A 16-bit bus, also
known as a wide bus, uses 27 transceivers.
Each
scsibiasls33
bias circuit supports up to 30 transceivers. The
scsipora
cell provides a power-on-reset signal for all the transceivers.
The
scsisensehm
cell detects the operating mode of the SCSI bus as
single ended (SE), low-voltage differential (LVD), or high-voltage
differential (HVD).
Note:
Although the
scsisensehm
DIFFSENS receiver can detect
HVD mode on the SCSI bus, the transceiver does not
support HVD mode. This conforms with the ANSI SPI-3
specification, which eliminated this older mode.
Power saving features minimize power consumption. In LVD mode, all
circuits in the Ultra160 SCSI cells supporting SE mode power down. In
SE mode, all circuits supporting LVD mode power down.
The Ultra160 SCSI cells include level translation circuitry, which enables
them to operate at the 3.3 V level in the I/O ring region and at the 1.8 V
160 Mbytes/s maximum burst data transfer rate
40 MHz maximum clocking frequency
Double transition (DT) clocking
Single-ended (SE) and low-voltage differential (LVD) operation
Programmable slew rate for single-ended driver
Programmable drive strength for LVD driver supports ANSI SPI-3
domain validation feature
Receivers autonegate when disabled
G12TM-p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate
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DB08-000156-00
August 2001
Copyright 2000, 2001 by LSI Logic Corporation. All rights reserved.
level in the ASIC core area. Built-in NAND-tree logic gates and IDDTN
control for IDDQ leakage testing enable use of the standard LSI Logic
test methodology.
Figure 1
Sample SCSI Application
The cells are 5-volt tolerant and fail-safe and they protect against voltage
feedthrough as follows:
Voltage Tolerance
Although the I/O signaling normally operates at 3.3 V, external
circuitry can cause higher voltages, typically 5 V, to appear at the
chip I/O pad. Circuit and process techniques ensure that such DC or
transient voltages do not damage the cell circuitry.
Safe from Failure
The cells will not fail if a high voltage persists at the I/O pad even
with the V
DD
supply removed. Under such conditions the cells can
survive without degradation for up to ten years.
HTPLG
IBIAS
SRST
-
+
IB29
IBIAS
Ch
i
and
-
+
scsiulvdls33
scsiulvdls33
scsibiasls33
VDDABIAS
RBIAS
PADM
PADP
PADM
PADP
IB0
Z
PADI
I
HTPLG
Z
PADI
I
Transceiver
Transceiver
Bias
Power-On
Reset
DIFFSENS
scsipora
scsisensehm
ddrvscsi5ls33
DETHI
DETLO
CTRL
HTPLG
VREF
Application
Circuitry
Notes:
ASIC
I/O Pads
DataIN
DataOUT
SCSI
Signals
Control
DIFFSENS
Chi represents the ith channel, where
i = 1 to n and n = number of channels.
Not all signals and connections shown.
Bias
Resistor
Receiver
Other SCSI
Signals
Unused
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G12TM-p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate
DB08-000156-00
August 2001
Copyright 2000, 2001 by LSI Logic Corporation. All rights reserved.
Feedthrough Protection
The Ultra160 SCSI cells limit leakage current at the I/O pad to a
maximum of 20
A. In the absence of a V
DD
supply and with high
voltage applied at the I/O pad, this low leakage current prevents
voltage feedthrough from powering up the ASIC.
scsiulvdls33 Transceiver Cell
The
scsiulvdls33
cell (
Figure 2
) is a multimode or universal circuit that
provides SCSI bidirectional signaling at up to Ultra160 data rates.
Operating in SE or LVD mode, it produces 80 Megatransfers/s using
double-transition clocking at the maximum clocking frequency of 40 MHz.
Across a 16-channel bus, this translates to a maximum burst-data
transfer rate of 160 Mbytes/s.
Figure 2
The scsiulvdls33 Cell
Signal Descriptions
Table 1
describes the
scsiulvdls33
connections.
I
ISEL
CLK
WRB
LVD
ANE
IBIAS
SL2
SL1
SL0
RDB
Z
PI
PO
HTPLG
IDDTN
PADI
scsiulvdls33
PADM (
-
Signal)
PADP (
+
Signal)
I/O Pads
1.8 V
Signals
Note: Power and ground connections not shown.
G12TM-p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate
5 of 24
DB08-000156-00
August 2001
Copyright 2000, 2001 by LSI Logic Corporation. All rights reserved.
Table 1
scsiulvdls33 Connections
Signal
Direction
Description
ANE
IN
Enables active negation in SE mode only:
0 = Passive negation
1 = Active negation
CLK
IN
Clock for latching and synchronizing data input.
Positive edge latches data.
HTPLG
IN
Driver disable control signal. An unbuffered input from the
scsipora
cell.
0 = Normal driver operation
1 = Driver output at high impedance
I
IN
Data input to SE and LVD drivers from ASIC circuitry:
0 = Asserted logical signal
1 = Negated logical signal
IBIAS
IN
Bias current input from the
scsibiasls33
cell.
IDDTN
IN
0 = Power down entire cell
1
1 = Normal mode
ISEL
IN
Selects between direct or latched input (refer to
Figure 3
):
0 = Select I as input
1 = Select I internally latched as input
LVD
IN
Selects signal mode:
0 = SE mode
1 = LVD mode
PI
IN
NAND-tree parametric test input
RDB
IN
0 = Enable receiver
1 = Disable receiver
SL2, SL1, SL0
IN
Sets slew rate for SE mode (refer to
Table 4
). SL2 is the most significant
bit (MSB); SL0 is the least significant bit (LSB).
WRB
IN
0 = Enable SE and LVD drivers
1 = Disable SE and LVD drivers
PADI
OUT
PADM unbuffered. Connects to VREF in
scsipora
cell.
Restricted for use only with SCSI Power-On-Reset.
PADM
IN/OUT
SCSI bus connection for SE signal and LVD
-
signal
PADP
IN/OUT
SCSI bus connection for SE ground and LVD+ signal
PO
OUT
NAND-tree parametric test output
Z
OUT
Received data output to ASIC circuitry from SE and LVD receivers
1. Used for production IDDQ leakage test.
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