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022101

FEATURES

Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source

Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations

Century byte register; i.e., Y2K complaint

Totally nonvolatile with over 10 years of
operation in the absence of power

Precision power-on reset

Programmable watchdog timer and RTC
alarm

BCD coded year, month, date, day, hours,
minutes, and seconds with automatic leap
year compensation valid up to the year 2100

Battery voltage level indicator flag

Power-fail write protection allows for

10%

power supply tolerance

Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time

ORDERING INFORMATION

*DS1557P

(5V)

*DS1557WP (3.3V)
*DS9034PCX (PowerCap

) Required:

must be ordered separately

PIN ASSIGNMENT

PIN DESCRIPTION

A0-A18 -

Address

Input

DQ0-DQ7 -

Data

Input/Outputs

IRQ

\FT

- Interrupt, Frequency Test
Output (Open Drain)

RST

- Power-On Reset Output
(Open Drain)

- Chip Enable

- Output Enable

- Write Enable

- Power Supply Input

GND -

Ground

- No Connection

X1, X2

- Crystal Connection

BAT

- Battery Connection

DESCRIPTION

The DS1557 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC
alarm, watchdog timer, power-on reset, battery monitor, and 512k x 8 non-volatile static RAM. User
access to all registers within the DS1557 is accomplished with a bytewide interface as shown in Figure 1.
The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.

DS1557

4MEG NV Y2KC Timekeeping RAM

www.dalsemi.com

IRQ/FT

A15

A16

RST

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

A17

A14

A13

A12

A11

A10

A18

X1 GND V

BAT

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

DS1557

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The RTC Registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC
information is always maintained.

The DS1557 has interrupt (

IRQ

/FT) and reset (

RST

) outputs which can be used to control CPU activity.

The

IRQ

/FT interrupt output can be used to generate an external interrupt when the RTC Register values

match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery backed state to serve as a system
wake-up. Either the

IRQ

/FT or

RST

outputs can also be used as a CPU watchdog timer, CPU activity is

monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1557 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the

RST

output is used

for this function.

The DS1557 also contains its own power-fail circuitry, which automatically deselects the device when the
V

supply enters an out of tolerance condition. This feature provides a high degree of data security

during unpredictable system operation brought on by low V

levels.

DS1557 BLOCK DIAGRAM Figure 1

DS1557

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DS1557 OPERATING MODES Table 1

DQ0-DQ7

MODE

POWER

HIGH-Z

DESELECT

STANDBY

WRITE

ACTIVE

OUT

READ

ACTIVE

> V

HIGH-Z

READ

ACTIVE

< V

HIGH-Z

DESELECT

CMOS STANDBY

< V

HIGH-Z

DATA

RETENTION

BATTERY

CURRENT

DATA READ MODE

The DS1557 is in the read mode whenever

(chip enable) is low and

(write enable) is high. The

device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t

after the last address input is stable, providing that

and

access times are

satisfied. If

access times are not met, valid data will be available at the latter of chip enable

access (t

CEA

) or at output enable access time (t

OEA

). The state of the data input/output pins (DQ) is

controlled by

and

. If the outputs are activated before t

, the data lines are driven to an

intermediate state until t

. If the address inputs are changed while

and

remain valid, output data

will remain valid for output data hold time (t

) but will then go indeterminate until the next address

access.

DATA WRITE MODE

The DS1557 is in the write mode whenever

and

are in their active state. The start of a write is

referenced to the latter occurring transition of

. The addresses must be held valid throughout

the cycle.

and

must return inactive for a minimum of t

prior to the initiation of a subsequent

read or write cycle. Data in must be valid t

prior to the end of the write and remain valid for t

afterward. In a typical application, the

signal will be high during a write cycle. However,

can be

active provided that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on

will then disable the outputs t

WEZ

after

goes active.

DATA RETENTION MODE

The 5-volt device is fully accessible and data can be written and read only when V

is greater than V

However, when V

is below the power-fail point V

(point at which write protection occurs) the

internal clock registers and SRAM are blocked from any access. When V

falls below the battery switch

point V

(battery supply level), device power is switched from the V

pin to the internal backup lithium

battery. RTC operation and SRAM data are maintained from the battery until V

is returned to nominal

levels.

The 3.3 volt device is fully accessible and data can be written and read only when V

is greater than V

When V

falls below V

, access to the device is inhibited. If V

is less than V

, the device power is

switched from V

to the internal backup lithium battery when V

drops below V

. If V

is greater

than V

, the device power is switched from V

to the internal backup lithium battery when V

drops

below V

. RTC operation and SRAM data are maintained from the battery until V

is returned to

nominal levels.

All control, data, and address signals must be powered down when V

is powered down.

DS1557

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BATTERY LONGEVITY

The DS1557 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the V

supply is not present. The capability of this internal power

supply is sufficient to power the DS1557 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25

C with the internal clock

oscillator running in the absence of V

INTERNAL BATTERY MONITOR

The DS1557 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.

POWER-ON RESET

A temperature compensated comparator circuit monitors the level of V

. When V

falls to the power

fail trip point, the

RST

signal (open drain) is pulled low. When V

returns to nominal levels, the

RST

signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is

independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

CLOCK OPERATIONS

Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.

DS1557

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DS1557 REGISTER MAP Table 2

DATA

ADDRESS

FUNCTION/RANGE

7FFFFh

10 Year

YEAR

00-99

7FFFEh

10 M

MONTH

01-12

7FFFDh

10 Date

DATE

01-31

7FFFCh

DAY

01-07

7FFFBh

10 HOUR

HOUR

00-23

7FFFAh

10 MINUTES

MINUTES

00-59

7FFF9h

OSC

10 SECONDS

SECONDS

00-59

7FFF8h

10 CENTURY

CENTURY

CONTROL

00-39

7FFF7h

WDS

BMB4

BMB3

BMB2

BMB1

BMB0

RB1

RB0

WATCHDOG

7FFF6h

ABE

INTERRUPTS

7FFF5h

AM4

10 DATE

DATE

ALARM DATE

01-31

7FFF4h

AM3

10 HOURS

HOURS

ALARM HOURS

00-23

7FFF3h

AM2

10 MINUTES

MINUTES

ALARM MINUTES

00-59

7FFF2h

AM1

10 SECONDS

SECONDS

ALARM SECONDS

00-59

7FFF1h

UNUSED

7FFF0h

BLF

FLAGS

X = Unused, read/writeable under Write and Read

AE = Alarm Flag Enable

bit control

Y = Unused, read/writeable without Write and Read

FT = Frequency Test bit

bit control

OSC

= Oscillator start/stop bit

ABE = Alarm in battery Back-up mode enable

W = Write bit

AM1-AM4 = Alarm Mask bits

R = Read bit

WF = Watchdog Flag

WDS = Watchdog Steering bit

AF = Alarm Flag

BMB0-BMB4 = Watchdog Multiplier bits

0 = 0 and are read only

RB0-RB1 = Watchdog Resolution bits

BLF = Battery Low Flag

CLOCK OSCILLATOR CONTROL

The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The

OSC

bit is the

MSB of the Seconds Register (B7 of 7FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1557 is shipped from Dallas Semiconductor with the clock oscillator turned off,

OSC

bit set to a 1.

READING THE CLOCK

When reading the RTC data, it is recommended to halt updates to the external set of double-buffered
RTC Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register
(7FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is
issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt
command was issued. Normal updates to the external set of registers will resume within 1 second after
the read bit is set to a 0 for a minimum of 500

s. The read bit must be a zero for a minimum of 500

to ensure the external registers will be updated.

DS1557

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SETTING THE CLOCK

The MSB bit, B7, of the Control Register is the write bit. Setting the write bit to a 1, like the read bit,
halts updates to the DS1557 (7FFF8h-7FFFFh) registers. After setting the write bit to a 1, RTC Registers
can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write
bit to a 0 then transfers the values written to the internal RTC Registers and allows normal operation to
resume.

CLOCK ACCURACY

The DS1557 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within

1.53 minutes per month (35 ppm) at 25°C and does

not require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken
to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.

FREQUENCY TEST MODE

The DS1557 frequency test mode uses the open drain

IRQ

/FT output. With the oscillator running, the

IRQ

/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and

the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 7FFF7h = 00h). The

IRQ

/FT output and the frequency test mode can be used as a measure of the actual frequency of the

32.768 kHz RTC oscillator. The

IRQ

/FT pin is an open drain output which requires a pull-up resistor for

proper operation. The FT bit is cleared to a 0 on power-up.

USING THE CLOCK ALARM

The alarm settings and control for the DS1557 reside within Registers 7FFF2h-7FFF5h. Register 7FFF6h
contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and
ABE bits must be set as described below for the

IRQ

/FT output to be activated for a matched alarm

condition.

The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1557 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once per second mode to
notify the user of an incorrect alarm setting.

DS1557

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ALARM MASK BITS Table 3

AM4

AM3

AM2

AM1

ALARM RATE

Once per second

When seconds match

When minutes and seconds match

When hours, minutes, and seconds match

When date, hours, minutes, and seconds match

When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the

IRQ

/FT pin. The

IRQ

/FT

signal is cleared by a read or write to the Flags Register (Address 7FFF0h) as shown in Figure 2 and 3.
When

is active, the

IRQ

/FT signal may be cleared by having the address stable for as short as 15 ns

and either

active, but is not guaranteed to be cleared unless t

is fulfilled. The alarm flag is

also cleared by a read or write to the Flags Register but the flag will not change states until the end of the
read/write cycle and the

IRQ

/FT signal has been cleared.

CLEARING IRQ WAVEFORMS Figure 2

CLEARING IRQ WAVEFORMS Figure 3

The

IRQ

/FT pin can also be activated in the battery backed mode. The

IRQ

/FT will go low if an alarm

occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates
alarm timing during the battery back-up mode and power-up states.

7FFF0h

DS1557

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BACK-UP MODE ALARM WAVEFORMS Figure 4

USING THE WATCHDOG TIMER

The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog
timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 7FFF7h). The
five Watchdog Register bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds.
The watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with
the 2-bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 X 1 second or
3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF)
is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read
or the Watchdog Register (7FFF7h) is read or written.

The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,
the watchdog will activate the

IRQ

/FT output when the watchdog times out.

When WDS is set to a 1, the watchdog will output a negative pulse on the

RST

output for a duration of

40 ms to 200 ms. The Watchdog Register (7FFF7h) and the FT bit will reset to a 0 at the end of a
watchdog time-out when the WDS bit is set to a 1.

The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The
time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the
Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog
Register is cleared. If the watchdog function is set to output to the

IRQ

/FT output and the frequency test

function is activated, the watchdog function prevails and the frequency test function is denied.

POWER-ON DEFAULT STATES

Upon application of power to the device, the following register bits are set to a 0:
WDS=0, BMB0-BMB4=0, RB0-RB1=0, AE=0, ABE=0.

DS1557

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

-.3V to +6.0V

Storage Temperature

-40

C to +85

Soldering Temperature

260°C for 10 seconds (DIP Package) (See Note 8)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

OPERATING RANGE

Range

Temperature

Commercial

0°C to +70°C

3.3V

10% or 5V

10%

RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1 Voltage All Inputs

= 5V

10%

2.2

+0.3V

= 3.3V

10%

2.0

+0.3V

Logic 0 Voltage All Inputs

= 5V

10%

-0.3

0.8

= 3.3V

10%

-0.3

0.6

DC ELECTRICAL CHARACTERISTICS

(Over the Operating Range; V

= 5.0V

10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Active Supply Current

2, 3

TTL Standby Current (

)

CC1

2, 3

CMOS Standby Current
(

- 0.2V)

CC2

2, 3

Input Leakage Current (any input)

-1

Output Leakage Current (any
output)

-1

Output Logic 1 Voltage
(I

OUT

= -1.0 mA)

2.4

Output Logic 0 Voltage
(I

OUT

= 2.1 mA, DQ0-7 Outputs)

OL1

0.4

OUT

= 7.0 mA,

IRQ

/FT and

RST

outputs)

OL2

0.4

1, 5

Write Protection Voltage

4.25

4.50

Battery Switch Over Voltage

BAT

1, 4

DS1557

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DC ELECTRICAL CHARACTERISTICS

(Over the Operating Range; V

= 3.3V

10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Active Supply Current

2, 3

TTL Standby Current (

= V

)

CC1

2, 3

CMOS Standby Current
(

- 0.2V)

CC2

2, 3

Input Leakage Current (any input)

-1

Output Leakage Current
(any output)

-1

Output Logic 1 Voltage
(I

OUT

= -1.0 mA)

2.4

Output Logic 0 Voltage
(I

OUT

=2.1 mA, DQ0-7 Outputs)

OL1

0.4

OUT

=7.0 mA,

IRQ

/FT and

RST

Outputs)

OL2

0.4

1, 5

Write Protection Voltage

2.80

2.97

Battery Switch Over Voltage

BAT

1, 4

READ CYCLE TIMING DIAGRAM Figure 5

DS1557

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READ CYCLE, AC CHARACTERISTICS

(Over the Operating Range)

=5.5V

±
±
±
±

=
=
=
=

10%

=3.3V

±
±
±
±

=
=
=
=

10%

PARAMETER

SYMBOL

MIN

MAX MIN

MAX

UNITS NOTES

Read Cycle Time

120

Address Access Time

120

to DQ Low-Z

CEL

Access Time

CEA

120

Data Off time

CEZ

to DQ Low-Z

OEL

Access Time

OEA

100

Data Off Time

OEZ

Output Hold from Address

WRITE CYCLE, AC CHARACTERISTICS

(Over the Operating Range

)

=5.0 V

±
±
±
±

=
=
=
=

10%

=3.3V

±
±
±
±

=
=
=
=

10%

PARAMETER

SYMBOL

MIN

MAX MIN

MAX

UNITS NOTES

Write Cycle Time

120

Address Access Time

Pulse Width

WEW

100

Pulse Width

CEW

110

Data Setup Time

Data Hold time

DH1

Data Hold time

DH2

Address Hold Time

AH1

Address Hold Time

AH2

Data Off Time

WEZ

Write Recovery Time

DS1557

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POWER-UP/DOWN CHARACTERISTICS

(Over the Operating Range; V

= 3.3V

10%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

at V

, Before

Power-Down

Fall Time: V

PF(MAX)

PF(MIN)

300

Rise Time: V

PF(MIN)

PF(MAX)

RST

High

REC

200

Expected Data Retention Time
(Oscillator On)

years

POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE Figure 9

CAPACITANCE

= 25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Capacitance on all input pins

Capacitance on

IRQ

/FT,

RST

and DQ pins

DS1557

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AC TEST CONDITIONS

Output Load:

100 pF + 1TTL Gate

Input Pulse Levels:

0.0 to 3.0V

Timing Measurement Reference Levels:

Input: 1.5V
Output: 1.5V

Input Pulse Rise and Fall Times: 5 ns

NOTES:

Voltage referenced to ground.

Typical values are at 25

C and nominal supplies.

Outputs are open.

Battery switch over occurs at the lower of either the battery voltage or V

The

IRQ

/FT and

RST

outputs are open drain.

Data retention time is at 25

Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up ("live-bug").

Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the
part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove
solder.

AH1

, t

DH1

are measured from WE going high.

10.

AH2

, t

DH2

are measured from CE going high.

DS1557

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DS1557P

NOTE:

Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up ("live-bug").

Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds.
To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply
flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.

PKG

INCHES

DIM

MIN

NOM

MAX

0.920

0.925

0.930

0.980

0.985

0.990

0.080

0.052

0.055

0.058

0.048

0.050

0.052

0.015

0.020

0.025

0.027

0.030

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