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111999
FEATURES
Converts CMOS RAMs into nonvolatile
memories
SOIC version is pin-compatible with the
Dallas Semiconductor DS1210 NV Controller
Unconditionally write protects all of memory
when V
CC
is out of tolerance
Write protects selected blocks of memory
regardless of V
CC
status when programmed
Automatically switches to battery backup
supply when power-fail occurs
Provides for multiple batteries
Consumes less than 100 nA of battery current
Test battery on power-up by inhibiting the
second memory cycle
Optional 5% or 10% power-fail detection
16-pin DIP or 16-pin SOIC surface-mount
package
Low forward voltage drop on the V
CC
switch
with currents of up to 150 mA
Optional industrial temperature range of
-40C to +85C
PIN ASSIGNMENT
PIN DESCRIPTION
V
CCI
- Input +5 Volt Supply
V
BAT1
- + Battery 1 Input
V
BAT2
- + Battery 2 Input
V
CCO
- RAM Power (V
CC
) Supply
GND
- Ground
CEI
- Chip Enable Input
CEO
- Chip Enable Output
WEI
- Write Enable Input
WEO
- Write Enable Output
TOL
- Power Supply Tolerance Select
A
W
- A
Z
- Address Inputs
DIS
- Memory Partition Disable
PFO
- Power-Fail Output
DESCRIPTION
The DS1610 is a low-power CMOS circuit which solves the application problems of converting CMOS
RAMS into nonvolatile memories. In addition the device has the ability to unconditionally write protect
blocks of memory so that inadvertent write cycles do not corrupt program and special data space. The
power supply incoming voltage at the V
CCI
input pin is constantly monitored for an out-of-tolerance
condition. When such a condition is detected, both the chip enable and write enable outputs are inhibited
to protect stored data. The battery inputs are used to supply V
CCO
with power when V
CCI
is less than the
battery input voltages. Special circuitry uses a low leakage CMOS process which affords precise voltage
detection at extremely low current consumption. By combining the DS1610 Partitioned NV Controller
chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved.
The DS1610 Partitioned NV Controller functions like the Dallas Semiconductor DS1210 NV controller
when the (
DIS
) disable pin is grounded. An internal pulldown resistor to ground on the
DIS
pin of the
DS1610S allows it to retrofit into DS1210S applications. When the
DIS
pin is grounded the address
inputs A
W
- A
Z
and the write enable input
WEI
are ignored. Also the power-fail output
PFO
and the write
enable output
WEO
are tristated.
DS1610
Partitioned NV Controller
www.dalsemi.com
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2
3
4
5
6
7
8
16
15
14
13
9
10
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12
PFO
V
CCI
A
Z
V
BAT2
WEO
CEO
WEI
CEI
A
W
V
CCO
A
X
V
BAT1
A
Y
TOL
DIS
GND
16-Pin DIP and 16-Pin SOIC
DS1610
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OPERATION - DISABLE PIN CONNECTED TO V
CCO
The DS1610 performs five circuit functions required to battery backup a RAM. First, a switch is provided
to direct power from the battery or the incoming power supply (V
CCI
) depending on which is greater. This
switch has a voltage drop of less than 0.2 volts. The second function provided by the DS1610 is power-
fail detection. The incoming supply (V
CCI
) is constantly monitored. When the supply goes out of
tolerance a precision comparator detects power failure and inhibits both the chip enable output (
CEO
) and
the write enable output (
WEO
). A third function of write protection is accomplished by holding both the
chip enable output
CEO
and write enable output
WEO
to within 0.2 volts of V
CCO
when V
CCI
is out of
tolerance. If
CEI
is low at the time that power-fail detection occurs the
CEO
signal is kept low until
CEI
is brought high again. However,
CEO
is forced high after 1.5 s regardless of the state of
CEI
. Similarly,
if
WEI
is low at the time that power fail detection occurs, the
WEO
signal will remain low until
WEI
is
brought high or 1.5 s elapses. The delay of write protection until the current memory cycle is complete
prevents corrupted data. Power-fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance
pin TOL grounded. If the tolerance pin is connected to V
CCO
then power-fail detection occurs in the range
of 4.5 volts to 4.25 volts. The
PF0
signal is driven low and remains low until V
CCI
returns to nominal
conditions. During nominal supply conditions
CEO
will follow
CEI
and
WEO
will follow
WEI
. The
fourth function which the DS1610 performs is a battery status warning so that potential data loss is
avoided. Each time V
CCI
is applied to the device battery status is checked with a precision comparator. If
during battery backup no switch occurred from one battery to the other, the voltage of the battery
supplying power when V
CCI
is applied is checked. If this voltage is less than 2.0 volts the second chip
enable cycle after power is applied is inhibited. If any switch from one battery to another did occur the
voltage of both batteries is checked. If either voltage is less than 2.0 volts the second chip enable cycle
will be inhibited. Battery status can therefore be determined by performing a read cycle after power up to
any location in memory, verifying that memory location's contents. A subsequent write cycle can then be
executed to the same memory location altering the data. If the next read cycle fails to verify the written
data then the data is in danger of being corrupted. The fifth function of the DS1610 provides for battery
redundancy. When data integrity is extremely important it is wise to use two batteries to insure reliability.
The DS1610 controller provides an internal isolation switch which allows the connection of two batteries.
When entering battery backup operation, the battery with the highest voltage is selected for use. If one
battery should fail, the other would then supply energy to the connected load. The switch to a redundant
battery is transparent to circuit operation and to the user. In applications where battery redundancy is not
a major concern a single battery should be connected to the BAT1 pin. The BAT2 battery pin must be
grounded. When batteries are first connected to one or both of the V
BAT
pins V
CCO
will not show the
battery potential until V
CCI
is applied and removed for the first time.
OPERATION - WRITE PROTECTION PROGRAMMING MODE
When the disable pin is connected to V
CCI
or V
CCO
, the DS1610 performs all of the functions described
earlier with the addition of a partition switch which selectively write protects blocks of memory. The state
of the
DIS
pin is strobed and latched as V
CCI
crosses the power-fail trip point so that the DS1610
maintains its configuration during power loss. If the strobed value of
DIS
is a high the internal pulldown
resistor on the
DIS
pin will be disconnected in the power-fail state to eliminate the possibility of battery
discharge. The register controlling the partition switch is selected by recognition of a specific binary
pattern which is sent on address lines A
W
-A
Z
. These address lines are normally the four upper order
address lines being sent to RAM. The pattern is sent by 20 consecutive read cycles with the exact pattern
as shown in Table 1. Pattern matching must be accomplished using read cycles; any write cycles will
reset the pattern matching circuitry. If this pattern is matched perfectly, then the 21
st
through 24
th
read
cycle will load the partition switch. Since there are 16 possible write protected partitions, the size of each
partition is determined by the size of the memory. For example, a 128k X 8 memory would be divided
into 16 partitions of 128k/16 or 8k X 8. Each partition is represented by one of the 16 bits contained in the
DS1610
3 of 10
21
st
through 24
th
read cycle as defined by A
W
through A
Z
and shown in Table 2. A logical 1 in a bit
location sets that partition to write protect. A logical 0 in a bit location disables write protection. For
example, if during the pattern match sequence bit 22 on address pin A
X
were a 1, this would cause the
partition register location for partition 5 to be set to a 1. This in turn would cause the DS1610 to inhibit
WEO
from going low as
WEI
goes low whenever A
Z
A
Y
A
X
A
W
=0101. Note that while setting the partition
register, data which is being accessed from the RAM should be ignored as the purpose of the 24 read
cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that on
initial battery attach the partition register can power-up in any state.
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A
W
1
0
1
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
0
1
X
X
X
X
A
X
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
1
0
0
0
0
X
X
X
X
A
Y
1
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
0
0
1
X
X
X
X
A
Z
1
1
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
0
0
X
X
X
X
PARTITION REGISTER MAPPING Table 2
Address
Pin
Bit number in pattern
Match sequence
Partition Number
Address State Affected
(A
Z
A
Y
A
X
A
W
)
A
W
BIT 21
PARTITION 0
0000
A
X
BIT 21
PARTITION 1
0001
A
Y
BIT 21
PARTITION 2
0010
A
Z
BIT 21
PARTITION 3
0011
A
W
BIT 22
PARTITION 4
0100
A
X
BIT 22
PARTITION 5
0101
A
Y
BIT 22
PARTITION 6
0110
A
Z
BIT 22
PARTITION 7
0111
A
W
BIT 23
PARTITION 8
1000
A
X
BIT 23
PARTITION 9
1001
A
Y
BIT 23
PARTITION 10
1010
A
Z
BIT 23
PARTITION 11
1011
A
W
BIT 24
PARTITION 12
1100
A
X
BIT 24
PARTITION 13
1101
A
Y
BIT 24
PARTITION 14
1110
A
Z
BIT 24
PARTITION 15
1111
DS1610
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.5V to +7.0V
Operating Temperature
0
C to 70
C
Storage Temperature
-55
C to +125
C
Soldering Temperature
260
C for 10 seconds
*
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0
C to 70
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Pin 6 = GND Supply Voltage
V
CCI
4.75
5.0
5.5
V
1
Pin 6 = V
CCO
Supply Voltage
V
CCI
4.5
5.0
5.5
V
1
Logic 1 Input
V
IH
2.0
V
CC
+0.3
V
1
Logic 0 Input
V
IL
-0.3
+0.8
V
1
Battery Input
V
BAT1
,
V
BAT2
2.0
4.0
V
1, 2
DC ELECTRICAL CHARACTERISTICS
(0C to 70C, V
CCI
WITHIN DC OPERATING CONDITIONS)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Operating Current
I
CC1
5
mA
3, 14
Standby Current
I
CC2
200
A
3, 15
Supply Voltage
V
CCO
V
CC
-0.2
V
1
Supply Current
I
CCO1
150
mA
4
Input Leakage
I
IL
-1.0
+1.0
A
Output Leakage
I
LO
-1.0
+1.0
A
V
CC
Trip Point (TOL=GND)
V
CCTP
4.50
4.62
4.75
V
1, 16
V
CC
Trip Point (TOL=V
CC
)
V
CCTP
4.25
4.37
4.50
V
1, 16
CEI
to
CEO
Impedance
Z
CE
30
5
DIS
Pulldown Resistance
R
DIS
50k
250k
PFO
,
WEO
Output @ 2.4V
I
OH
-1.0
mA
10, 16
PFO
,
WEO
Output @ 0.4V
I
OL
4.0
mA
10, 16
DC ELECTRICAL CHARACTERISTICS
(0C to 70C; V
CC
<4.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CEO
Output
V
OHL
V
BAT
-0.2
V
WEO
Output
V
OHL
V
BAT
-0.2
V
V
BAT1
or V
BAT2
Battery Current
I
BAT
100
nA
2, 3
Battery Backup Current @
V
CCO
= V
BAT
-0.2V
I
CCO2
150
A
6, 7, 8
DS1610
5 of 10
CAPACITANCE
(t
A
= 25C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
5
pF
Output Capacitance
C
OUT
7
pF
(0C to 70C; V
CCI
= 4.75V to 5.50V, TOL= GND)
AC ELECTRICAL CHARACTERISTICS
(V
CCI
= 4.50V to 5.50V, TOL-V
CCO
)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Address Setup
t
AS
0
ns
9
Address Hold
t
AH
50
ns
9
Read Recovery
t
RR
10
ns
9
CEI
,
WEI
Pulse Width
t
CW
75
ns
9
CEI
to
CEO
Falling
Propagation Delay
t
PDF
5
ns
10
Later of
CEI
,
WEI
to
WEO
Falling Propagation Delay
t
PDF
20
ns
10, 11
CEI
to
CEO
Rising
Propagation Delay
t
PDR
5
ns
10
Earlier of
CEI
,
WEI
to
WEO
Rising Propagation Delay
t
PDR
5
ns
10, 11
Write Recovery
t
WR
10
ns
9, 11
AC ELECTRICAL CHARACTERISTICS
(0C to 70C; V
CC
<4.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Recovery at Power-Up
t
REC
25
125
ms
12
V
CC
Slew Rate Power-Down
t
F
300
s
V
CC
Slew Rate Power-Down
t
FB
10
s
V
CC
Slew Rate Power-Up
t
F
0
s
13
CEO
Pulse Width
t
WP
, t
CE
1.5
s
7, 8
WEO
Pulse Width
t
WP
, t
CE
1.5
s
7, 8
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