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022101
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM. These registers are resident in the
eight top RAM locations.
Totally nonvolatile with over 10 years of
operation in the absence of power
Access times of 70 ns and 100 ns
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for 10%
V
CC
power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
DS1643 only (DIP Module)
Standard JEDEC byte-wide 8K x 8 RAM
pinout
DS1643P only (PowerCap Module Board)
Surface mountable package for direct
connection to PowerCap containing
battery and crystal
Replaceable battery (PowerCap)
Power-fail output
Pin-for-pin compatible with other
densities of DS164XP Timekeeping RAM
ORDERING INFORMATION
DS1643-XXX
28-pin DIP module
-70
70 ns access
-100
100 ns access
*DS1643P-XXX 34-pin PowerCap Module Board
-70
70 ns access
-100
100 ns access
*DS9034PCX
PowerCap
(Required; must be ordered
separately)
PIN ASSIGNMENT
DS1643/DS1643P
Nonvolatile Timekeeping RAM
www.dalsemi.com
13
27
28-PIN Encapsulated Package
(700-mil Extended)
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
VCC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
28
26
25
24
23
22
21
20
19
18
17
15
16
A12
A6
A4
NC
1
NC
2
3
NC
NC
PFO
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
NC
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
X1 GND V
BAT
X2
34-PIN PowerCap Module Board
(USES DS9034PCX PowerCap)
DS1643/DS1643P
2 of 14
PIN DESCRIPTION
A0-A12 -
Address
Input
CE
- Chip Enable
CE2
- Chip Enable 2 (DIP Module
only)
OE
- Output Enable
WE
- Write Enable
V
CC
- +5 Volts
GND -
Ground
DQ0-DQ7
- Data Input/Output
NC
- No Connect
RST
- Power-on Reset Output
(PowerCap Module board only)
X1, X2
- Crystal Connection
V
BAT
- Battery Connection
DESCRIPTION
The DS1643 is a 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) which are
both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to
any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid
access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1643 also contains its own power-fail circuitry which deselects the device when the V
CC
supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap module. The 28-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1643P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double-buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to 0.
DS1643/DS1643P
3 of 14
BLOCK DIAGRAM DS1643 Figure 1
DS1643 TRUTH TABLE Table 1
V
CC
CE
CE2
OE
WE
MODE
DQ
POWER
V
IH
X
X
X
DESELECT
HIGH Z
STANDBY
X
V
IL
X
X
DESELECT
HIGH Z
STANDBY
V
IL
V
IH
X
V
IL
WRITE
DATA IN
ACTIVE
V
IL
V
IH
V
IL
V
IH
READ
DATA OUT
ACTIVE
5 VOLTS
10%
V
IL
V
IH
V
IH
V
IH
READ
HIGH Z
ACTIVE
<4.5 VOLTS
>V
BAT
X
X
X
X
DESELECT
HIGH Z
CMOS STANDBY
<V
BAT
X
X
X
X
DESELECT
HIGH Z
DATA RETENTION
MODE
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,
CE
low,
OE
low, CE2 high, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within
1 minute per month at 25
C.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within
1.53 minutes per month (35 ppm) at 25
C.
DS1643/DS1643P
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DS1643 REGISTER MAP - BANK1 Table 2
DATA
ADDRES
S
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION
1FFF
-
-
-
-
-
-
-
-
YEAR
00-99
1FFE
X
X
X
-
-
-
-
-
MONTH
01-12
1FFD
X
X
-
-
-
-
-
-
DATE
01-31
1FFC
X
FT
X
X
X
-
-
-
DAY
01-07
1FFB
X
X
-
-
-
-
-
-
HOUR
00-23
1FFA
X
-
-
-
-
-
-
-
MINUTES
00-59
1FF9
OSC
-
-
-
-
-
-
-
SECONDS
00-59
1FF8
W
R
X
X
X
X
X
X
CONTROL
A
OSC
= STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = UNUSED
NOTE:
All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever
WE
(write enable) is high and
CE
(chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
AA
after the last address input is stable, providing that the
CE
and
OE
access times and states are satisfied. If
CE
or
OE
access times are not met, valid data will be
available at the latter of chip enable access (t
CEA
) or at output enable access time (t
OEA
). The state of the
data input/output pins (DQ) is controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data will remain valid for output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on
WE
will
then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
When V
CC
is within nominal limits (V
CC
> 4.5 volts) the DS1643 can be accessed as described above with
read or write cycles. However, when V
CC
is below the power-fail point V
PF
(point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the
CE
signal. At this time the power-on reset output signal (
RST
) will
be driven active low and will remain active until V
CC
returns to nominal levels. When V
CC
falls below the
level of the internal battery supply, power input is switched from the V
CC
pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until V
CC
is returned to nominal
DS1643/DS1643P
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level. The
RST
signal is an open drain output and requires a pull up. Except for the
RST
, all control, data,
and address signals must be powered down when V
CC
is powered down.
BATTERY LONGEVITY
The DS1643 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the V
CC
supply is not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25
C with the internal clock oscillator running in
the absence of V
CC
power. Each DS1643 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than
V
PF
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
Ds1643 will be much longer than 10 years since no lithium battery energy is consumed when V
CC
is
present.
DS1643/DS1643P
6 of 14
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +7.0V
Operating Temperature
0C to 70C
Storage Temperature
-40C to +85C
Soldering Temperature
J-STD-020A Specification (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0
C to 70
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Logic 1 Voltage All Inputs
V
IH
2.2
V
CC
+0.3
V
Logic 0 Voltage All Inputs
V
IL
-0.3
0.8
V
DC ELECTRICAL CHARACTERISTICS (0
C to
=
70
C; V
CC
= 5.0V
=
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
I
CC
15
50
mA
2, 3
TTL Standby Current
(
CE
=V
IH
, CE2=V
IL
)
I
CC1
1
3
mA
2, 3
CMOS Standby Current
(
CE
=V
CC
-0.2V
,
CE2=GND+0.2V)
I
CC2
1
3
mA
2, 3
Input Leakage Current (any input)
I
IL
-1
+1
A
Output Leakage Current (any output)
I
OL
-1
+1
A
Output Logic 1 Voltage
(I
OUT
= -1.0 mA)
V
OH
2.4
1
Output Logic 0 Voltage
(I
OUT
= +2.1 mA)
V
OL
0.4
1
Write Protection Voltage
V
PF
4.25
4.37
4.50
V
1
DS1643/DS1643P
7 of 14
READ CYCLE, AC CHARACTERISTICS (0
C to 70
C; V
CC
= 5.0V
=
10%)
70 ns access
100 ns access
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Read Cycle Time
t
RC
70
100
ns
4
Address Access Time
t
AA
70
100
ns
4
CE
and CE2 to DQ Low-Z
t
CEL
5
5
ns
4
CE
Access Time
t
CEA
70
100
ns
4
CE2 Access Time
t
CE2A
80
105
ns
4
CE
and CE2 Data Off Time
t
CEZ
25
35
ns
4
OE
to DQ Low-Z
t
OEL
5
5
ns
4
OE
Access Time
t
OEA
35
55
ns
4
OE
Data Off Time
t
OEZ
25
35
ns
4
Output Hold from Address
t
OH
5
5
ns
4
READ CYCLE TIMING DIAGRAM
WRITE CYCLE, AC CHARACTERISTICS (0
C to 70
C; V
CC
= 5.0V
=
10%)
70 ns access
100 ns access
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Write Cycle Time
t
WC
70
100
ns
4
Address Setup Time
t
AS
0
0
ns
4
WE
Pulse Width
t
WEW
50
70
ns
4
CE
Pulse Width
t
CEW
60
75
ns
4
CE2 Pulse Width
t
CE2W
65
85
ns
4
Data Setup Time
t
DS
30
40
ns
4
Data Hold Time
t
DH
0
0
ns
4
Address Hold Time
t
AH
5
5
ns
4
WE
Data Off Time
t
WEZ
25
35
ns
4
Write Recovery Time
t
WR
5
5
ns
4
DS1643/DS1643P
8 of 14
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM,
CE
, CE2 CONTROLLED
DS1643/DS1643P
9 of 14
POWER-UP/DOWN AC CHARACTERISTICS (0
C to 70
C; V
CC
= 5.0V
=
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
CE
or
WE
at V
IH
, CE2 at V
IL
, Before
Power-down
t
PD
0
s
V
CC
Fall Time: V
PF
(MAX) to V
PF
(MIN)
t
F
300
s
V
CC
Fall Time: V
PF
(MIN) to V
BAT
t
FB
10
s
V
CC
Rise Time: V
PF
(MIN) to V
PF
(MAX)
t
R
0
s
Power-up Recover Time
t
REC
35
ms
Expected Data Retention Time
(Oscillator On)
t
DR
10
years
5, 6
POWER-UP/POWER-DOWN TIMING
CAPACITANCE (t
A
= 25
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Capacitance on all pins
C
IN
7
pF
Capacitance on all output pins
C
O
10
pF
DS1643/DS1643P
10 of 14
AC TEST CONDITIONS
Output Load:
100 pF + 1TTL Gate
Input Pulse Levels:
0.0 to 3.0 Volts
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1.
Voltages are referenced to ground.
2.
Typical values are at 25
C and nominal supplies.
3.
Outputs are open.
4.
The CE2 control signal functions exactly the same as the
CE
signal except that the logic levels for
active and inactive levels are opposite.
5.
Data retention time is at 25
C.
6.
Each DS1643 has a built-in switch that disconnects the lithium source until V
CC
is first applied by the
user. The expected t
DR
is defined for DIP modules as a cumulative time in the absence of V
CC
starting
from the time power is first applied by the user.
7.
Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85
C. Post-solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap:
a.
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up ("live-bug").
b.
Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the
part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove
solder.
DS1643/DS1643P
11 of 14
DS1643 28-PIN PACKAGE
PKG
28-PIN
DIM
MIN
MAX
A IN.
MM
1.470
37.34
1.490
37.85
B IN.
MM
0.675
17.75
0.740
18.80
C IN.
MM
0.315
8.51
0.335
9.02
D IN.
MM
0.075
1.91
0.105
2.67
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.140
3.56
0.180
4.57
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.010
0.25
0.018
0.45
K IN.
MM
0.015
0.43
0.025
0.58
DS1643/DS1643P
12 of 14
DS1643P
PKG
INCHES
DIM
MIN
NOM
MAX
A
0.920
0.925
0.930
B
0.980
0.985
0.990
C
-
-
0.080
D
0.052
0.055
0.058
E
0.048
0.050
0.052
F
0.015
0.020
0.025
G
0.025
0.027
0.030
NOTE:
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up ("live-bug").
Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds.
To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux,
heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1643/DS1643P
13 of 14
DS1643P WITH DS9034PCX ATTACHED
PKG
INCHES
DIM
MIN
NOM
MAX
A
0.920
0.925
0.930
B
0.955
0.960
0.965
C
0.240
0.245
0.250
D
0.052
0.055
0.058
E
0.048
0.050
0.052
F
0.015
0.020
0.025
G
0.020
0.025
0.030
DS1643/DS1643P
14 of 14
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
INCHES
DIM
MIN
NOM
MAX
A
-
1.050
-
B
-
0.826
-
C
-
0.050
-
D
-
0.030
-
E
-
0.112
-
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