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100302
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may be simultaneously available through various sales channels. For information about device errata, click here:
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.
GENERAL DESCRIPTION
The DS1672 low-voltage serial timekeeping chip
incorporates a 32-bit counter and power-
monitoring functions. The 32-bit counter is
designed to count seconds and can be used to
derive time-of-day, week, month, month, and
year by using a software algorithm. A precision,
temperature-compensated reference and
comparator circuit monitors the status of V
CC
.
When an out-of-tolerance condition occurs, an
internal power-fail signal is generated that forces
the reset to the active state. When V
CC
returns to
an in-tolerance condition, the reset signal is kept
in the active state for 250ms to allow the power
supply and processor to stabilize.
FEATURES
32-bit counter
2-wire serial interface
Automatic power-fail detect and switch
circuitry
Power-fail reset output
Low-voltage oscillator operation (1.3V min)
Trickle charge capability
Underwriters Laboratory (UL) recognized
ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
DS1672-2
-40C to +85C
8 0.300" DIP
DS1672-2
DS1672-3
-40C to +85C
8 0.300" DIP
DS1672-3
DS1672-33
-40C to +85C
8 0.300" DIP
DS1672-33
DS1672S-2
-40C to +85C
8 0.150" SO
DS1672-2
DS1672S-3
-40C to +85C
8 0.150" SO
DS1672-3
DS1672S-33
-40C to +85C
8 0.150" SO
DS1672-33
DS1672U-2
-40C to +85C
8 SOP
1672rr-2
DS1672U-3
-40C to +85C
8 SOP
1672rr-22
DS1672U-
33
-40C to +85C
8 SOP
1672rr-33
PIN CONFIGURATION
Package Dimension Information
www.maxim-ic.com/TechSupport/DallasPackInfo.htm
DS1672
Low-Voltage Serial Timekeeping Chip
www.maxim-ic.com
www.maxim-ic.com
TYPICAL OPERATING CIRCUIT
1
2
3
4
8
7
6
5
V
CC
RST
SCL
SDA
X1
X2
V
BACKUP
GND
DIP
SO
SOP
TOP VIEW
DS1672
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
-0.5V to +6.0V
Operating Temperature Range
-40
C to +85C
Storage Temperature Range
-55
C to +125C
Soldering Temperature
See IPC/JEDEC J-STD-020A
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -40
C to +85C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
V
CC
2.97
3.3
3.63
V
1
V
CC
2.7
3.0
3.3
V
1
Supply Voltage (DS1672-33)
(DS1672-3)
(DS1672-2)
V
CC
1.8
2.0
2.2
V
1
Logic 1
V
IH
0.7V
CC
V
CC
+ 0.5
V
1
Logic 0
V
IL
-0.5
0.3V
CC
V
1
Backup Supply Voltage
V
BACKUP
1.3
3.0
3.63
V
1
Note 1: All voltages referenced to ground.
DC ELECTRICAL CHARACTERISTICS
(V
CCMIN
< V
CC
< V
CCMAX,
T
A
= -40
C to +85C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
I
CCA
600
mA
2
Standby Current
I
CCS
500
mA
3
Power-Fail Voltage
V
PF
2.80
2.88
2.97
V
Power-Fail Voltage
V
PF
2.5
2.6
2.7
V
Power-Fail Voltage
V
PF
1.6
1.7
1.8
V
V
BACKUP
Leakage Current
I
BACKUPLKG
25
50
nA
Logic 0 Output (V
OL
= 0.4V)
I
OL
3
mA
1, 4
Logic 0 Output (DS1672-2)
(V
CC
> 2 V; V
OL
= 0.4V)
(V
CC
< 2 V; V
OL
= .2V
CC
)
I
OL
3
3
mA
1, 4
Note 1: All voltages referenced to ground.
Note 2: I
CCA
specified with SCL clocking at max frequency (400kHz), trickle charger disabled.
Note 3: I
CCS
specified with V
CC
= V
CCTYP
and SDA, SCL = V
CCTYP
, trickle charger disabled.
Note 4: SDA and
RST
.
DS1672
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DC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40
C to +85C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
V
BACKUP
Current (Osc on)
I
BACKUPOSC
0.425
1
mA
5
V
BACKUP
Current (Osc off)
I
BACKUP
200
nA
Note 5: Using the recommended crystal on X1 and X2.
CRYSTAL SPECIFICATIONS
*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Nominal Frequency
F
O
32.768
kHz
Series Resistance
ESR
45
k
Load Capacitance
C
L
6
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations
for Dallas Real-Time Clocks for additional specifications
DS1672
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AC ELECTRICAL CHARACTERISTICS
(V
CC
> V
CCMIN
, T
A
= -40
C to +85C)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
Fast Mode
100
400
SCL Clock
Frequency
f
SCL
Standard Mode
100
kHz
Fast Mode
1.3
Bus Free Time
Between a STOP and
START Condition
t
BUF
Standard Mode
4.7
ms
Fast Mode
0.6
Hold Time
(Repeated) START
Condition
t
HD:STA
Standard Mode
4.0
ms
6
Fast Mode
1.3
LOW Period of SCL
Clock
t
LOW
Standard Mode
4.7
ms
Fast Mode
0.6
HIGH Period of SCL
Clock
t
HIGH
Standard Mode
4.0
ms
Fast Mode
0.6
Setup Time for a
Repeated START
Condition
t
SU:STA
Standard Mode
4.7
ms
Fast Mode
0
0.9
Data Hold Time
t
HD:DAT
Standard Mode
0
ms
7, 8
Fast Mode
100
Data Setup Time
t
SU:DAT
Standard Mode
250
ns
9
Fast Mode
20 + 0.1C
B
300
Rise Time of Both
SDA and SCL
Signals
t
R
Standard Mode
1000
ns
10
Fast Mode
20 + 0.1C
B
300
Fall Time of Both
SDA and SCL
Signals
t
F
Standard Mode
300
ns
10
Fast Mode
0.6
Setup Time for STOP
Condition
t
SU:STO
Standard Mode
4.0
ms
Capacitive Load for
Each Bus Line
C
B
400
pF
10
I/O Capacitance
C
I/O
10
pF
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
IHMIN
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 8:The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 9: A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>= to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R
max + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is
released.
Note 10: C
B
Total capacitance of one bus line in pF.
DS1672
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POWER-UP/POWER-DOWN CHARACTERISTICS
(T
A
= -40
C to +85C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
V
CC
Detect to
RST
(V
CC
Falling)
t
RPD
10
s
V
CC
Detect to
RST
(V
CC
Rising)
t
RPU
250
ms
11
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
t
F
300
ms
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
t
R
0
ms
Note 11: If the
EOSC
bit in the control register is set to logic 1, t
RPU
is equal to 250ms plus the startup time of the crystal oscillator.
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write
protection.
Figure 1. Timing Diagram
SCL
START
SDA
STOP
t
BUF
REPEATED
START
t
HD:STA
t
LOW
t
HD:STA
t
HD:DAT
t
SU:DAT
t
HIGH
t
SU:STA
t
F
t
SU:STO
Figure 2. Power-Up/Power-Down Timing
OUTPUTS
V
CC
V
PF(max)
INPUTS
HIGH-Z
RST
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
t
RPD
V
PF(min)
t
F
t
PD
t
R
t
RPU
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