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022301
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identical to the
static RAM. These registers are resident in
the eight top RAM locations
Century byte register
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
Battery voltage level indicator flag
Power-fail write protection allows for
10%
V
CC
power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Standard JEDEC bytewide 2k x 8 static RAM
pinout
Quartz accuracy
1 minute a month @ 25
C,
factory calibrated
PIN ASSIGNMENT
PIN DESCRIPTION
A0-A10 -
Address
Inputs
CE
- Chip Enable
OE
- Output Enable
WE
- Write Enable
V
CC
- Power Supply Input
GND -
Ground
DQ0-DQ7 -
Data
Input/Outputs
ORDERING INFORMATION
DS1742-XXX
(5V)
-70
70 ns access
-100 100 ns access
DS1742W-XXX
(3.3V)
-120 120 ns access
-150
150 ns access
DESCRIPTION
The DS1742 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8
non-volatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year
are made automatically.
DS1742
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
V
CC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
24
23
22
21
20
19
18
17
16
15
14
13
DS1742
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The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock
update cycles. The double buffered system also prevents time loss as the timekeeping countdown
continues unabated by access to time register data. The DS1742 also contains its own power-fail
circuitry, which deselects the device when the V
CC
supply is in an out of tolerance condition. This feature
prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and
update cycles are avoided.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count,
that is day, date, and time that was current at the moment the halt command was issued. However, the
internal clock registers of the double-buffered system continue to update so that the clock accuracy is not
affected by the access of data. All of the DS1742 registers are updated simultaneously after the internal
clock register updating process has been re-enabled. Updating is within a second after the read bit is
written to 0. The READ bit must be a zero for a minimum of 500
s to ensure the external registers will
be updated.
DS1742 BLOCK DIAGRAM Figure 1
DS1742 TRUTH TABLE Table 1
V
CC
CE
OE
WE
MODE
DQ
POWER
V
IH
X
X
DESELECT
HIGH-Z
STANDBY
V
IL
X
V
IL
WRITE
DATA IN
ACTIVE
V
IL
V
IL
V
IH
READ
DATA OUT
ACTIVE
V
CC
>V
PF
V
IL
V
IH
V
IH
READ
HIGH-Z
ACTIVE
V
SO
<V
CC
<V
PF
X
X
X
DESELECT
HIGH-Z
CMOS STANDBY
V
CC
<V
SO
<V
PF
X
X
X
DESELECT
HIGH-Z
DATA RETENTION MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1742 registers. The user can then load them with the correct day, date and
time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual
clock counters and allows normal operation to resume.
DS1742
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STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to within
1 minute per month at 25
C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements. The DS1742 does
not require additional calibration. For this reason, methods of field clock calibration are not available and
not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken
to place the RTC in the lowest level EMI section of the PCB layout. For additional information please
see application note 58.
DS1742 REGISTER MAP Table 2
DATA
ADDRESS
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION/RANGE
7FF
10 Year
YEAR
YEAR
00-99
7FE
X
X
X
10 Mo
MONTH
MONTH
01-12
7FD
X
X
10 Date
DATE
DATE
01-31
7FC
BF
FT
X
X
X
DAY
DAY
01-07
7FB
X
X
10 HOUR
HOUR
HOUR
00-23
7FA
X
10 MINUTES
MINUTES
MINUTES
00-59
7F9
OSC
10 SECONDS
SECONDS
SECONDS
00-59
7F8
W
R
10 CENTURY
CENTURY
CONTROL
00-39
OSC
= STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = SEE NOTE BELOW
BF = BATTERY FLAG
NOTE:
All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever
OE
(output enable) is low,
WE
(write enable) is high, and
CE
(chip enable) is low. The device architecture allows ripplethrough access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the
CE
, and
OE
access times and states are satisfied. If
CE
, or
OE
access times
and states are not met, valid data will be available at the latter of chip enable access (t
CEA
) or at output
enable access time (t
OEA
). The state of the data input/output pins (DQ) is controlled by
CE
, and
OE
. If
the outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the
DS1742
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address inputs are changed while
CE
, and
OE
remain valid, output data will remain valid for output data
hold time (t
OH
) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever
WE
, and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
, on
CE
. The addresses must be held valid throughout
the cycle.
CE
, or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on
WE
will
then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power fail point, V
PF
,
(point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels. The 3.3
volt device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
When V
CC
falls below the power fail point, V
PF
,
access to the device is inhibited. If V
PF
is less than Vso
,
the device
power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below V
PF
.
If V
PF
is greater than
Vso
,
the device power is switched from V
CC
to the backup supply (V
BAT
)
when V
CC
drops below Vso
.
RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
BATTERY LONGEVITY
The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the V
CC
supply is not present. The capability of this internal power supply
is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25
C with the internal clock oscillator running in
the absence of V
CC
power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than
V
PF
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1742 will be much longer than 10 years since no lithium battery energy is consumed when V
CC
is
present.
BATTERY MONITOR
The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated
and both the contents of the RTC and RAM are questionable.
DS1742
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +6.0V
Operating Temperature
0
C to 70
C
Storage Temperature
-40
C to +85
C
Soldering Temperature
See J-STD-020A Specification (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Temperature
V
CC
Commercial
0C to +70C
3.3V
10% or 5V
10%
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic 1 Voltage All Inputs
V
CC
= 5V
10%
V
IH
2.2
V
CC
+0.3V
V
1
V
CC
= 3.3V
10%
V
IH
2.0
V
CC
+0.3V
V
1
Logic 0 Voltage All Inputs
V
CC
= 5V
10%
V
IL
-0.3
0.8
V
1
V
CC
= 3.3V
10%
V
IL
-0.3
0.6
V
1
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; V
CC
= 5.0V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
I
CC
15
50
mA
2, 3
TTL Standby Current (
CE
=V
IH
)
I
CC1
1
3
mA
2, 3
CMOS Standby Current
(
CE
=V
CC
- 0.2V)
I
CC2
1
3
mA
2, 3
Input Leakage Current
(any input)
I
IL
-1
+1
A
Output Leakage Current
(any output)
I
OL
-1
+1
A
Output Logic 1 Voltage
(I
OUT
= -1.0 mA)
V
OH
2.4
1
Output Logic 0 Voltage
(I
OUT
= +2.1 mA)
V
OL
0.4
1
Write Protection Voltage
V
PF
4.25
4.50
V
1
Battery Switch-over Voltage
V
SO
V
BAT
1, 4
DS1742
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DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; V
CC
= 3.3V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current
I
CC
10
30
mA
2, 3
TTL Standby Current (
CE
= V
IH
)
I
CC1
0.7
2
mA
2, 3
CMOS Standby Current
(
CE
=V
CC
- 0.2V)
I
CC2
0.7
2
mA
2, 3
Input Leakage Current (any input)
I
IL
-1
+1
A
Output Leakage Current
(any output)
I
OL
-1
+1
A
Output Logic 1 Voltage
(I
OUT
= -1.0 mA)
V
OH
2.4
1
Output Logic 0 Voltage
(I
OUT
=2.1 mA)
V
OL
0.4
1
Write Protection Voltage
V
PF
2.80
2.97
V
1
Battery Switch-over Voltage
V
SO
V
BAT
or V
PF
V
1, 4
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; V
CC
= 5.0V
10%)
70 ns access
100 ns access
PARAMETER
SYMBOL
MIN
MAX MIN MAX UNITS
NOTES
Read Cycle Time
t
RC
70
100
ns
Address Access Time
t
AA
70
100
ns
CE
to DQ Low-Z
t
CEL
5
5
ns
CE
Access Time
t
CEA
70
100
ns
CE
Data Off time
t
CEZ
25
35
ns
OE
to DQ Low-Z
t
OEL
5
5
ns
OE
Access Time
t
OEA
35
55
ns
OE
Data Off Time
t
OEZ
25
35
ns
Output Hold from Address
t
OH
5
5
ns
DS1742
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READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; V
CC
= 3.3V
10%)
120 ns access 150 ns access
PARAMETER
SYMBOL
MIN
MAX MIN MAX UNITS
NOTES
Read Cycle Time
t
RC
120
150
ns
5
Address Access Time
t
AA
120
150
ns
5
CE
to DQ Low-Z
t
CEL
5
5
ns
5
CE
Access Time
t
CEA
120
150
ns
5
CE
Data Off time
t
CEZ
40
50
ns
5
OE
to DQ Low-Z
t
OEL
5
5
ns
5
OE
Access Time
t
OEA
100
130
ns
5
OE
Data Off Time
t
OEZ
35
35
ns
5
Output Hold from Address
t
OH
5
5
ns
5
READ CYCLE TIMING DIAGRAM
DS1742
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WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; V
CC
= 5.0V
10%)
70 ns access
100 ns access
PARAMETER
SYMBOL
MIN
MAX MIN MAX UNITS
NOTES
Write Cycle Time
t
WC
70
100
ns
Address Access Time
t
AS
0
0
ns
WE
Pulse Width
t
WEW
50
70
ns
CE
Pulse Width
t
CEW
60
75
ns
Data Setup Time
t
DS
30
40
ns
Data Hold time
t
DH
0
0
ns
Address Hold Time
t
AH
5
5
ns
WE
Data Off Time
t
WEZ
25
35
ns
Write Recovery Time
t
WR
5
5
ns
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; V
CC
= 3.3V
10%)
120 ns access 150 ns access
PARAMETER
SYMBOL
MIN
MAX MIN MAX UNITS
NOTES
Write Cycle Time
t
WC
120
150
ns
Address Setup Time
t
AS
0
0
ns
WE
Pulse Width
t
WEW
100
130
ns
CE
Pulse Width
t
CEW
110
140
ns
Data Setup Time
t
DS
80
90
ns
Data Hold Time
t
DH
0
0
ns
Address Hold Time
t
AH
0
0
ns
WE
Data Off Time
t
WEZ
40
50
ns
Write Recovery Time
t
WR
10
10
ns
DS1742
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WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM,
CE
CONTROLLED
POWER-UP/DOWN CHARACTERISTICS
(Over the Operating Range; V
CC
= 5.0V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE
or
WE
at V
IH
, Before
Power-Down
t
PD
0
s
V
CC
Fall Time: V
PF(MAX)
to
V
PF(MIN)
t
F
300
s
V
CC
Fall Time: V
PF(MIN)
to V
SO
t
FB
10
s
V
CC
Rise Time: V
PF(MIN)
to
V
PF(MAX)
t
R
0
s
Power-up Recover Time
t
REC
35
ms
Expected Data Retention Time
(Oscillator On)
t
DR
10
years
5, 6
DS1742
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POWER-UP/DOWN WAVEFORM TIMING 5-VOLT DEVICE
POWER-UP/DOWN CHARACTERISTIC
(Over the Operating Range; V
CC
= 3.3V
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE
or
WE
at V
IH
, Before
Power-Down
t
PD
0
s
V
CC
Fall Time: V
PF(MAX)
to
V
PF(MIN)
t
F
300
s
V
CC
Rise Time: V
PF(MIN)
to
V
PF(MAX)
t
R
0
s
Power-up Recovery Time
t
REC
35
ms
Expected Data Retention Time
(Oscillator On)
t
DR
10
years
5, 6
POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE
CAPACITANCE
(T
A
= 25
C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Capacitance on all input pins
C
IN
7
pF
Capacitance on all output pins
C
O
10
pF
DS1742
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AC TEST CONDITIONS
Output Load:
100 pF + 1TTL Gate
Input Pulse Levels:
0.0 to 3.0 Volts
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1.
Voltage referenced to ground.
2.
Typical values are at 25
C and nominal supplies.
3.
Outputs are open.
4.
Battery switch-over occurs at the lower of either the battery voltage or V
PF
.
5.
Data retention time is at 25
C.
6.
Each DS1742 has a built-in switch that disconnects the lithium source until V
CC
is first applied by the
user. The expected t
DR
is defined as a cumulative time in the absence of V
CC
starting from the time
power is first applied by the user.
7.
Real Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85
C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used to prevent damage to the crystal.
DS1742
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DS1742 24-PIN PACKAGE
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