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042902
FEATURES
Three linear taper potentiometers
- Two 10kW, 100-position
- One 100kW, 256-position
248 bytes of user EEPROM memory
Monitors microprocessor power supply,
voltage sense, and external override
Access to data and potentiometer control
through a 2-wire interface
External write-protect (WP) pin to protect
data and potentiometer settings
PIN CONFIGURATION
Operates from a 5V supply
Nonvolatile (NV) wiper storage
Packaging: 20-pin TSSOP
Programming temperature: 0C to +70C
Industrial operating temperature:
-40C to +85C
ORDERING INFORMATION
DS1846E-010
DS1846E-010/T&R (Tape-and-Reel Version)
PIN DESCRIPTION
V
CC
Power-Supply
Input
GND
Ground
SDA
2-Wire Serial Data
Input/Output
SCL
2-Wire Serial Clock Input
WP
Write-Protect Input
A0
Address Input
H0, H1, H2
High End of Potentiometer
L0, L1, L2 Low End of Potentiometer
W0, W1, W2 Wiper Terminal of
Potentiometer
PBRST
Pushbutton Reset Input
NMI
Nonmaskable Interrupt
Output
IN
NMI Voltage Input
RST
Active-Low Reset Output
RST
Active-High Reset Output
OVERVIEW
The DS1846 NV tri-potentiometer, memory, and MicroMonitorTM consists of two 10k
W, 100-position
linear taper potentiometers, one 100k
W, 256-position linear taper potentiometer; 256 bytes of EEPROM
memory; and a MicroMonitor. The device provides an ideal method for setting bias voltages and currents
in control applications using a minimum of circuitry.
DS1846
NV Tri-Potentiometer,
Memory, and MicroMonitor
www.maxim-ic.com
SDA
SCL
A0
WP
NMI
L0
W1
L1
L2
GND
V
CC
IN
PBRST
RST
RST
H0
W0
H1
W2
H2
20-Pin TSSOP
20
19
18
17
16
15
14
13
12
11
MicroMonitor is a trademark of Dallas Semiconductor.
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4
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7
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9
10
DS1846
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The EEPROM memory allows a user to store configuration or calibration data for a specific system or
device and provides control of the potentiometer wiper settings. Any type of user information can reside
in the first 248 bytes (00h to F7h) of this memory. The next three bytes of memory (F8h to FAh) are for
potentiometer settings and the last five addresses of EEPROM memory (FBh to FFh) are reserved. These
reserved and potentiometer registers should not be used for data storage. Access to this EEPROM is
through an industry-standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The wiper
positions of the DS1846, as well as EEPROM data, can be hardware write-protected using the WP input
pin.
The MicroMonitor is a precision temperature-compensated reference and comparator that monitors
certain vital status conditions for a microprocessor. When a sense input detects an out-of-tolerance (V
CC
)
condition, a nonmaskable interrupt is generated. As the voltage at the device degrades, an internal power-
fail signal is generated that can be used to reset the processor. When V
CC
returns to an in-tolerance level,
the reset signal is kept in the active state for a minimum time of t
RST
to allow for the stabilization of the
power supply and the microprocessor. The MicroMonitor also functions as a pushbutton reset control.
The pushbutton input is debounced internally and generates an active pulse width of t
RST
minimum.
DS1846 BLOCK DIAGRAM Figure 1
DS1846
2-Wire
Interface
SCL
SDA
WP
A0
5 Reserved
Bytes
FBh-FFh
Potentiometer 2
FAh
Potentiometer 0
F9h
Potentiometer 1
F8h
User EPROM
248 Bytes
00h-F7h
EEPROM
Potentiometer 2
H2
W2
L2
10k
W
Addr FAh
100-Positions
Potentiometer 0
H0
W0
L0
10k
W
Addr F9h
100-Positions
Potentiometer 1
H1
W1
L1
100k
W
Addr F8h
256-Positions
Data
Nonvolatile
Digital Potentiometer
PBRST
V
CCTP
V
TP
V
CC
IN
RST
RST
V
CC
NMI
MicroMonitor
Timer
Delay
Timer
Delay
V
CC
2.4k
W
typical
R
PBR
DS1846
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PIN DESCRIPTIONS
V
CC
--Power-Supply Terminal. The DS1846 will support supply voltages ranging from +4.5V to +5.5V.
GND--Ground Terminal
SDA--2-Wire Serial Data Interface. The serial data pin is for serial data transfer to and from the
DS1846. The pin is open drain and can be wire-ORed with other open-drain or open-collector interfaces.
SCL--2-Wire Serial Clock Interface. The serial clock input is used to clock data into the DS1846 on
rising edges and clock data out on falling edges.
WP--Write Protect. WP must be connected to GND before either the data in memory or potentiometer
wiper settings may be changed. WP is pulled high internally and must be either left open or connected to
V
CC
if write protection is desired.
A0--Address Input. This input pin specifies the address of the device when used in a multidropped
configuration. As many as two DS1846s may be addressed on a single 2-wire bus.
H0, H1, H2--High-End Terminals of the Potentiometers. For the three potentiometers, it is not
required that these terminals be connected to a potential greater than the low-end terminal of the
potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power-supply
voltage, V
CC
, or go below ground.
L0, L1, L2--Low-End Terminals of the Potentiometers. It is not required that these terminals be
connected to a potential less than the high-end terminals of the pot. Voltage applied to the low end of the
potentiometers cannot exceed the power-supply voltage, V
CC
, or go below ground.
W0, W1, W2--Wipers of the Potentiometers. These pins are the wiper terminals of the potentiometers.
Three bytes in EEPROM memory locations F8h, F9h, and FAh determine each wiper's setting. Voltage
applied to either wiper terminal cannot exceed the power-supply voltage, V
CC
, or go below ground.
PBRST
--Pushbutton Reset. This input pin is active low. It acts as the pushbutton reset pin for the
MicroMonitor. Pushbutton reset is pulled high internally.
NMI
--Nonmaskable Interrupt. Active-low signal that is generated to provide for an early power-fail
warning.
IN--NMI Voltage Input. An input voltage below VTP on this input forces the NMI output low. This can
be used with a voltage-divider to set a secondary voltage monitoring level. (See Figure 4.)
RST
--Active-Low Reset Output. This signal provides an output that can be used to reset a
microprocessor.
RST--Active-High Reset Output. This signal provides an output that can be used to reset a
microprocessor.
DS1846
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MEMORY ORGANIZATION
The EEPROM of the DS1846 contains 256 bytes. Bytes 00h to F7h are general-purpose user memory.
The next three bytes, F8h, F9h, and FAh, contain the wiper settings for each of the potentiometers (see
Table 1). The last five bytes, FBh to FFh, are reserved and should not be used.
The memory, internal to the device, is organized as 32 pages of eight bytes each. Once an address byte is
clocked into the device through the 2-wire interface, the five MSBs decode which page is to be accessed,
and the three LSBs decode a particular byte on that page. The selected page is shadowed in SRAM as a
staging area while data is clocked in or out through the 2-wire interface. When reading any number of
bytes, all eight bytes of the current page are shadowed in SRAM where the requested byte(s) eventually
get clocked out. When reading, the page is incremented automatically, and hence transparent to the user.
When performing a write, the page of the starting address is shadowed in SRAM. The new data is then
written to the SRAM. When the end of the page is reached, the address returns to the beginning of the
same page. When the 2-wire master issues a stop, the entire page (even if only a single byte changed) is
copied from the SRAM into EEPROM. All reads and writes to the EEPROM are actually executed as
page operations even though they are invisible to the user when performing single byte reads and writes.
Understanding the internal memory organization is important when performing sequential address writes
due to page boundaries. See the Write Operations in the 2-WIRE OPERATION section for more
information.
MEMORY LOCATIONS Table 1
MEMORY
LOCATION
NAME OF MEMORY
LOCATION
FUNCTION OF MEMORY LOCATION
00h to F7h
User Memory
General-purpose user memory.
F8h
Potentiometer 1 Setting
Writing to this byte controls the setting of potentiometer 1, a
256-position pot. Valid settings are 00h to FFh.
F9h
Potentiometer 0 Setting
Writing to this byte controls the setting of potentiometer 0, a
100-position pot.
Valid settings are 00h to 63h. MSB is ignored.
FAh
Potentiometer 2 Setting
Writing to this byte controls the setting of potentiometer 0, a
100-position pot.
Valid settings are 00h to 63h. MSB is ignored.
FBh to FFh
Reserved
Reserved
DS1846
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2-WIRE OPERATION
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high
periods indicates a start or stop condition depending on the conditions discussed below. See the timing
diagrams for further details (Figures 2 and 3).
Start Condition: A high-to-low transition of SDA with SCL high is a start condition, which must
precede any other command. See the timing diagrams for further details (Figures 2 and 3).
Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command places the DS1846 into a low-power mode. See the timing diagrams for
further details (Figures 2 and 3).
Acknowledge:
All address and data bytes are transmitted through a serial protocol. The DS1846 pulls the
SDA line low during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode: The DS1846 features a low-power mode that is automatically enabled after power-on,
after a stop command, and after the completion of all internal operations.
Memory Reset: After any interruption in protocol, power loss, or system reset, the following steps reset
the DS1846:
1) Clock up to nine cycles.
2) Look for SDA high in each cycle while SCL is high.
3) Create a start condition while SDA is high.
Device Addressing: The DS1846 must receive an 8-bit device address word following a start condition
to enable a specific device for a read or write operation. The address word is clocked into the DS1846
MSB to LSB. The address word consists of 101000 binary followed by A0 then the R/W bit. If the R/W
bit is high, a read operation is initiated. If the R/W bit is low, a write operation is initiated. For a device
to become active, the value of A0 must be the same as the hard-wired address pins on the DS1846. Upon
a match of written and hard-wired addresses, the DS1846 outputs a zero for one clock cycle as an
acknowledge. If the address does not match the DS1846 returns to a low-power mode.
Write Operations: After receiving a matching device address byte with the R/W bit set low, the device
goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to
the device to define the address where the data is to be written. After the byte has been received, the
DS1846 transmits a zero for one clock cycle to acknowledge the memory address has been received. The
master must then transmit an 8-bit data word to be written into this memory address. The DS1846 again
transmits a zero for one clock cycle to acknowledge the receipt of the data byte. At this point, the master
must terminate the write operation with a stop condition. The DS1846 then enters an internally timed
write process t
w
to the EEPROM memory. All inputs other than those controlling the MicroMonitor are
disabled during this write cycle.
The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but
the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges
the data byte has been received, the master can send up to seven more data bytes using the same nine-
clock sequence. After a write to the last byte in the page, the address returns to the beginning of the same
page. The master must then terminate the write cycle with a stop condition or the data clocked into the
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