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REV: 083006
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata
.
iButton DESCRIPTION
The DS1972 is a 1024-bit, 1-Wire
EEPROM
organized as four memory pages of 256 bits each in
a rugged iButton package. Data is written to an 8-
byte scratchpad, verified, and then copied to the
EEPROM memory. As a special feature, the four
memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only
be changed from a 1 to a 0 state. The DS1972
communicates over the single-conductor 1-Wire bus.
The communication follows the standard Dallas
Semiconductor 1-Wire protocol. Each device has its
own unalterable and unique 64-bit ROM registration
number that is factory lasered into the device. The
registration number is used to address the device in
a multidrop 1-Wire net environment.
APPLICATIONS
Access Control/Parking Meter
Work-In-Progress Tracking
Tool Management
Inventory Control
Maintenance/Inspection Data Storage
F5 AND F3 MicroCAN
0.51
5.89
IO
16.25
17.35
51
2D
0000006234FB
1-Wire
3.10
IO
GND
0.51
GND
F3 size
F5 size
Branding
SPECIAL FEATURES
1024 Bits of EEPROM Memory Partitioned into
Four Pages of 256 Bits
Individual Memory Pages can be Permanently
Write Protected or Put in EPROM-Emulation
Mode ("Write to 0")
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air, typical)
Reads and Writes Over a Wide Voltage Range of
2.8V to 5.25V from -40C to +85C
Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
COMMON iButton FEATURES
Unique Factory-Lasered 64-Bit Registration
Number Assures Error-Free Device Selection
and Absolute Traceability Because No Two Parts
are Alike
Built-In Multidrop Controller for 1-Wire Net
Chip-Based Data Carrier Stores Digital Identifi-
cation and Information, Armored in a Durable
Stainless-Steel Case
Data can be Accessed While Affixed to Object
Button Shape is Self-Aligning with Cup-Shaped
Probes
Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed onto its Rim
Presence Detector Acknowledges when Reader
First Applies Voltage
Designed to meet UL#913 (4th Edit.); Intrinsically
Safe Apparatus: Under Entity Concept for use in
Class I, Division 1, Group A, B, C, and D
Locations, contact Dallas Semiconductor for
certification schedule
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS1972-F5#
-40C to 85C
F5 iButton
DS1972-F3#
-40C to 85C
F3 iButton
# indicates RoHS complience
Contact factory lead-free compliance
Commands, Registers, and Modes are capitalized for
clarity.
IButton, 1-Wire, and MicroCAN are registered trademarks of Dallas
Semiconductor Corp.
DS1972
1024-Bit EEPROM iButton
www.maxim-ic.com
DS1972: 1024-Bit EEPROM iButton
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ABSOLUTE MAXIMUM RATINGS
I/O Voltage to GND
-0.5V, +6V
I/O Sink Current
20mA
Operating Temperature Range
-40C to +85C
Junction Temperature
+150C
Storage Temperature Range
-40C to +85C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40C to +85C; see Note 1.)
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O PIN GENERAL DATA
1-Wire Pullup Voltage
V
PUP
(Notes 2)
2.8
5.25
V
1-Wire Pullup Resistance
R
PUP
(Notes 2, 3)
0.3 2.2
k
W
Input Capacitance
C
IO
(Notes
4,
5)
1000 pF
Input Load Current
I
L
I/O pin at V
PUP
0.05
6.7
A
High-to-Low Switching
Threshold
V
TL
(Notes 5, 6, 7)
0.46
4.4
V
Input Low Voltage
V
IL
(Notes 2, 8)
0.3
V
Low-to-High Switching
Threshold
V
TH
(Notes 5, 6, 9)
1.0
4.9
V
Switching Hysteresis
V
HY
(Notes 5, 6, 10)
0.21
1.70
V
Output Low Voltage
V
OL
At 4mA (Note 11)
0.4 V
Standard speed, R
PUP
= 2.2k
W
5
Overdrive speed, R
PUP
= 2.2k
W
2
Recovery Time
(Notes 2,12)
t
REC
Overdrive speed, directly prior to Reset
Pulse; R
PUP
= 2.2k
W
5
s
Standard speed
0.5
5.0
Rising-Edge Hold-off Time
(Notes 5, 13)
t
REH
Overdrive speed
Not applicable (0)
s
Standard speed
65
Timeslot Duration
(Note 2, 14)
t
SLOT
Overdrive speed
8
s
I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE
Standard
speed
480 640
Reset Low Time (Note 2)
t
RSTL
Overdrive
speed
48 80
s
Standard
speed
15 60
Presence Detect High
Time
t
PDH
Overdrive
speed
2 6
s
Standard speed
60
240
Presence Detect Low
Time
t
PDL
Overdrive speed
8
24
s
Standard
speed
60 75
Presence Detect Sample
Time (Notes 2, 15)
t
MSP
Overdrive speed
6
10
s
I/O PIN, 1-Wire WRITE
Standard speed
60
120
Overdrive speed, V
PUP
> 4.5V
5
15.5
Write-0 Low Time (Notes
2, 16)
t
W0L
Overdrive speed
6
15.5
s
Standard speed
1
15 -
e
Write-1 Low Time
(Notes 2, 17)
t
W1L
Overdrive speed
1
2 -
e
s
I/O PIN, 1-Wire READ
Standard speed
5
15 -
d
Read Low Time
(Notes 2, 18)
t
RL
Overdrive speed
1
2 -
d
s
Standard speed
t
RL
+
d
15
Read Sample Time
(Notes 2, 18)
t
MSR
Overdrive speed
t
RL
+
d
2
s
DS1972: 1024-Bit EEPROM iButton
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PARAMETER SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM
Programming Current
I
PROG
(Note 5, 19)
0.8
mA
Programming Time
t
PROG
(Note 20)
10
ms
At 25C
200k
Write/Erase Cycles (En-
durance) (Notes 21, 22)
N
CY
At 85C (worst case)
50k
---
Data Retention
(Notes 23, 24)
t
DR
At 85C (worst case)
10
years
Note 1:
Specifications at T
A
= -40C are guaranteed by design only and not production-tested.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4:
Maximum value represents the internal parasite capacitance when V
PUP
is first applied. If a 2.2k
W resistor is used to pull up the
data line, 2.5s after V
PUP
has been applied the parasite capacitance will not affect normal communications.
Note 5:
Guaranteed by design, characterization and/or simulation only. Not production tested.
Note 6:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage which is itself a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of V
TL
, V
TH
,
and V
HY
.
Note 7:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8:
The voltage on IO needs to be less or equal to V
IL(MAX)
at all times the master is driving IO to a logic-0 level.
Note 9:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10:
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
HY
to be detected as logic '0'.
Note 11:
The I-V characteristic is linear for voltages less than 1V.
Note 12:
Applies to a single device attached to a 1-Wire line.
Note 13:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached on the preceding rising edge.
Note 14:
Defines maximum possible bit rate. Equal to t
W0L(min)
+ t
REC(min)
.
Note 15:
Interval after t
RSTL
during which a bus master is guaranteed to sample a logic-0 on IO if there is a DS1972 present. Minimum limit
is t
PDH(max)
; maximum limit is t
PDH(min)
+ t
PDL(min)
.
Note 16:
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Note 17:
e represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
.
Note 18:
d represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high threshold of the bus
master.
Note 19:
Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a low
impedance bypass of Rpup which can be activated during programming may need to be added.
Note 20:
Interval begins t
WiLMIN
after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
.
Note 21:
Write-cycle endurance is degraded as T
A
increases.
Note 22:
Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 23:
Data retention is degraded as T
A
increases.
Note 24:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
LEGACY VALUES
DS1972 VALUES
PARAMETER
STANDARD SPEED
OVERDRIVE SPEED
STANDARD SPEED
OVERDRIVE SPEED
MIN MAX MIN MAX MIN MAX MIN MAX
t
SLOT
(incl. t
REC
)
61s (undef.) 7s (undef.) 65s
1)
(undef.) 8s
1)
(undef.)
t
RSTL
480s
(undef.) 48s 80s 480s 640s 48s 80s
t
PDH
15s 60s 2s 6s 15s 60s 2s 6s
t
PDL
60s 240s 8s 24s 60s 240s 8s 24s
t
W0L
60s 120s 6s 16s 60s 120s 6s 15.5s
1)
Intentional change, longer recovery time requirement due to modified 1-Wire front end.
EXAMPLES OF ACCESSORIES
PART DESCRIPTION
DS9096P
Self-Stick Adhesive Pad
DS9101 Multipurpose
Clip
DS9093RA
Mounting Lock Ring
DS9093A Snap-In
Fob
DS9092 iButton Probe
DS1972: 1024-Bit EEPROM iButton
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DESCRIPTION
The DS1972 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes,
and a fully-featured 1-Wire interface in a rugged iButton package. Each DS1972 has its own 64-bit ROM
registration number that is factory lasered to provide a guaranteed unique identity for absolute traceability. Data is
transferred serially via the 1-Wire protocol, which requires only a single data contact and a ground return. The
DS1972 has an additional memory area called the scratchpad that acts as a buffer when writing to the main
memory or the register page. Data is first written to the scratchpad from which it can be read back. After the data
has been verified, a Copy Scratchpad command transfers the data to its final memory location. Applications of the
DS1972 include access control/parking meter, Work-In-Progress tracking, tool management, inventory control, and
maintenance/inspection data storage. Software for communication with the DS1972 is available for free download
from the http://www.maxim-ic.com/products/ibutton/ website.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS1972. The DS1972 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte
pages of EEPROM, and 4) 64-bit register page. The hierarchical structure of the 1-Wire protocol is shown in Figure
2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of
an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all
subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is
described in Figure 9. After a ROM function command is successfully executed, the memory functions become
accessible and the master may provide any one of the four memory function commands. The protocol for these
memory function commands is described in Figure 7. All data is read and written least significant bit first.
Figure 1. Block Diagram
PARASITE POWER
I/O
64-bit
Lasered ROM
1-Wire
Function Control
64-bit
Scratchpad
Data Memory
4 Pages of
256 bits each
CRC16
Generator
Memory
Function
Control Unit
Register Page
64 bits
DS1972
DS1972: 1024-Bit EEPROM iButton
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Figure 2. Hierarchical Structure for 1-Wire Protocol
Available
Commands:
DS1972 Command Level:
Data Field
Affected:
1-Wire ROM Function
Commands (see Figure 9)
DS1972-specific
Memory Function
Commands (see Figure 7)
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive-Skip
Overdrive-Match
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
64-bit Scratchpad, Flags
64-bit Scratchpad
Data Memory, Register Page
Data Memory, Register Page
64-BIT LASERED ROM
Each DS1972 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the
last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
MSB
LSB
8-Bit
CRC Code
48-Bit Serial Number
8-Bit Family
Code (2Dh)
MSB LSB
MSB
LSB
MSB
LSB
Figure 4. 1-Wire CRC Generator
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
Polynomial = X
8
+ X
5
+ X
4
+ 1
1
st
STAGE
2
nd
STAGE
3
rd
STAGE
4
th
STAGE
6
th
STAGE
5
th
STAGE
7
th
STAGE
8
th
STAGE
INPUT DATA
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