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101000

FEATURES

Generates/detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems

Operates at speeds from DC to 20 MHz

Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 2

-1, 2

-1,

and 2

-1

Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length

Large 32-bit error count and bit count
registers

Software programmable bit error insertion

Fully independent transmit and receive
sections

8-bit parallel control port

Detects test patterns with bit error rates up to
10

-2

PIN ASSIGNMENT

ORDERING INFORMATION

DS21372

C to 70

DS21372N

(-40

C to +85

DESCRIPTION

The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates
ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.

The DS21372 user-programmable pattern registers provide the unique ability to generate loopback
patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can
initiate the loopback, run the test, check for errors, and finally deactivate the loopback.

The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up
to 2

-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic

inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-
T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS21372 can insert single or 10

-1

to 10

-7

bit errors to verify equipment operation and connectivity.

DS21372

3.3V Bit Error Rate Tester (BERT)

www.dalsemi.com

AD0
AD1

TEST

VSS

AD2
AD3
AD4

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE (AS)

BTS

RD(DS

)

ATA

RCLK

RDI

RDA

DS21372

32-PIN TQFP

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

DS21372

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1. GENERAL OPERATION

1.1 PATTERN GENERATION

The DS21372 is programmed to generate a particular test pattern by programming the following registers:

Pattern Set Registers (PSR)

Pattern Length Register (PLR)

Polynomial Tap Register (PTR)

Pattern Control Register (PCR)

Error Insertion Register (EIR)

Please see Tables 4 and 5 for examples of how to program these registers in order to generate some
standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit
Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin
appearing at the TDATA pin.

1.2 PATTERN SYNCHRONIZATION

The DS21372 expects to receive the same pattern that it transmitted. The synchronizer examines the data
at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard
synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.

In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined
in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all
0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by
using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are
received without error, where n is the exponent in the polynomial from Table 4. Once in synchronization
(SR.0 = 1) any deviation from this pattern will be counted by the Bit Error Count Register.

In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.
Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in
the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an
explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this
pattern will be counted by the Bit Error Count Register.

1.3 BER CALCULATION

Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the
bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count
Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over
the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration
period.

1.4 GENERATING ERRORS

Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the
transmitted data stream. Injecting errors allows users to stress communication links and to check the
functionality of error monitoring equipment along the path.

DS21372

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DETAILED PIN DESCRIPTION Table 1

PIN

SYMBOL

TYPE DESCRIPTION

Transmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR'ed with PCR.7 and should
be tied to V

if not used. See Figure 8 for timing information.

AD0

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD1

I/O

Data Bus. An 8-bit multiplexed address/data bus.

TEST

Test. Set high to 3-state all output pins (

INT

, ADx, TDATA, RLOS).

Should be tied to V

to enable all outputs.

Signal Ground. 0.0V. Should be tied to local ground plane.

AD2

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD3

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD4

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD5

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD6

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD7

I/O

Data Bus. An 8-bit multiplexed address/data bus.

Signal Ground. 0.0V. Should be tied to local ground plane.

Positive Supply. 3.3V.

BTS

Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the

(DS),

ALE(AS), and

(R/

) pins. If BTS = 1, then these pins assume the

function listed in parenthesis ().

(DS)

Read Input (Data Strobe).

Chip Select. Must be low to read or write the port.

ALE(AS)

Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.

(R/

)

Write Input (Read/Write).

INT

Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.

Positive Supply. 3.3V.

Signal Ground. 0.0V. Should be tied to local ground plane.

Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR'ed with control bit PCR.4.
Should be tied to V

if not used.

RLOS

Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.

DS21372

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PIN

SYMBOL

TYPE DESCRIPTION

Receive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR'ed with control bit PCR.3. Should be tied to V

if not used.

RDATA

Receive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.

RDIS

Receive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to V

if not used. See Figure 6 for timing information. All receive side

operations are disabled when RDIS is high.

RCLK

Receive Clock. Input clock from transmission link. 0 to 20 MHz. Can
be a gapped clock. Fully independent from TCLK.

Positive Supply. 3.3V.

Signal Ground. 0.0V. Should be tied to local ground plane.

TCLK

Transmit Clock. Transmit demand clock. 0 to 20 MHz. Can be a
gapped clock. Fully independent of RCLK.

TDIS

Transmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to V

if not used. See Figure 7 for timing information. All transmit

side operations are disabled when TDIS is high.

TDATA

Transmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.

DS21372 REGISTER MAP Table 2

ADDRESS R/W

REGISTER NAME

ADDRESS R/W

REGISTER NAME

R/W Pattern Set Register 3.

Bit Error Counter Register 3.

R/W Pattern Set Register 2.

Bit Error Counter Register 2.

R/W Pattern Set Register 1.

Bit Error Counter Register 1.

R/W Pattern Set Register 0.

Bit Error Counter Register 0.

R/W Pattern Length Register.

Pattern Receive Register 3.

R/W Polynomial Tap Register.

Pattern Receive Register 2.

R/W Pattern Control Register.

Pattern Receive Register 1.

R/W Error Insert Register.

Pattern Receive Register 0.

Bit Counter Register 3.

Status Register.

Bit Counter Register 2.

R/W Interrupt Mask Register.

Bit Counter Register 1.

R/W Test Register (see note 1)

Bit Counter Register 0.

NOTE:

The Test Register must be set to 00 hex to insure proper operation of the DS21372.

Электронный компонент: DS21372N