1 of 229
120602
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
GENERAL DESCRIPTION
The DS2155 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The DS2155 is composed of
a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled by
an 8-bit parallel port configured for Intel or Motorola
bus operations. The DS2155 is pin and software
compatible with the DS2156.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75
coax and 120 twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
FEATURES
Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder for Optical I/F
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
Programmable BERT Generator and Detector
Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75/100/120 T1 and E1 Interfaces
Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued on
page 8
.
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS2155L
0C to +70C
100 LQFP
DS2155LN
-40C to +85C
100 LQFP
DS2155
T1/E1/J1 Single-Chip Transceiver
www.maxim-ic.com
DS2155
T1/E1/J1
SCT
T1/E1/J1
NETWORK
BACKPLANE
TDM
DS2155
2 of 229
TABLE OF CONTENTS
1.
MAIN FEATURES........................................................................................................................................8
1.1
F
UNCTIONAL
D
ESCRIPTION
...........................................................................................................................11
1.2
B
LOCK
D
IAGRAM
...........................................................................................................................................13
F
IGURE
1-1. B
LOCK
D
IAGRAM
................................................................................................................................13
F
IGURE
1-2. R
ECEIVE AND
T
RANSMIT
LIU.............................................................................................................14
F
IGURE
1-3. R
ECEIVE AND
T
RANSMIT
F
RAMER
/HDLC..........................................................................................15
F
IGURE
1-4. B
ACKPLANE
I
NTERFACE
.....................................................................................................................16
2.
PIN FUNCTION DESCRIPTION .............................................................................................................17
2.1.1
Transmit Side ........................................................................................................................................17
2.1.2
Receive Side ..........................................................................................................................................20
2.2
P
ARALLEL
C
ONTROL
P
ORT
P
INS
...................................................................................................................23
2.3
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
........................................................................................................24
2.4
U
SER
O
UTPUT
P
ORT
P
INS
..............................................................................................................................25
2.5
JTAG T
EST
A
CCESS
P
ORT
P
INS
.....................................................................................................................26
2.6
L
INE
I
NTERFACE
P
INS
....................................................................................................................................27
2.7
S
UPPLY
P
INS
..................................................................................................................................................28
2.8
L
AND
G P
ACKAGE
P
INOUT
...........................................................................................................................29
T
ABLE
2-A. P
IN
D
ESCRIPTION
S
ORTED BY
P
IN
N
UMBER
.......................................................................................29
2.9
10
MM
CSBGA P
IN
C
ONFIGURATION
............................................................................................................31
F
IGURE
2-1. 10
MM
CSBGA P
IN
C
ONFIGURATION
..................................................................................................31
3.
PARALLEL PORT .....................................................................................................................................32
3.1
R
EGISTER
M
AP
..............................................................................................................................................32
T
ABLE
3-A. R
EGISTER
M
AP
S
ORTED BY
A
DDRESS
................................................................................................32
4.
SPECIAL PER-CHANNEL REGISTER OPERATION.........................................................................38
5.
PROGRAMMING MODEL.......................................................................................................................40
F
IGURE
5-1. P
ROGRAMMING
S
EQUENCE
.................................................................................................................40
5.1
P
OWER
-U
P
S
EQUENCE
...................................................................................................................................41
5.1.1
Master Mode Register...........................................................................................................................41
5.2
I
NTERRUPT
H
ANDLING
..................................................................................................................................42
5.3
S
TATUS
R
EGISTERS
........................................................................................................................................42
5.4
I
NFORMATION
R
EGISTERS
.............................................................................................................................43
5.5
I
NTERRUPT
I
NFORMATION
R
EGISTERS
..........................................................................................................43
6.
CLOCK MAP ..............................................................................................................................................44
F
IGURE
6-1. C
LOCK
M
AP
........................................................................................................................................44
7.
T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................45
7.1
T1 C
ONTROL
R
EGISTERS
...............................................................................................................................45
7.2
T1 T
RANSMIT
T
RANSPARENCY
.....................................................................................................................50
7.3
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
....................................................................................50
7.4
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
.......................................................................51
T
ABLE
7-A. T1 A
LARM
C
RITERIA
..........................................................................................................................53
DS2155
3 of 229
8.
E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................54
8.1
E1 C
ONTROL
R
EGISTERS
...............................................................................................................................54
T
ABLE
8-A. E1 S
YNC
/R
ESYNC
C
RITERIA
...............................................................................................................55
8.2
A
UTOMATIC
A
LARM
G
ENERATION
................................................................................................................58
8.3
E1 I
NFORMATION
R
EGISTERS
........................................................................................................................59
T
ABLE
8-B. E1 A
LARM
C
RITERIA
...........................................................................................................................60
9.
COMMON CONTROL AND STATUS REGISTERS ............................................................................61
9.1
T1/E1 S
TATUS
R
EGISTERS
.............................................................................................................................62
10.
I/O PIN CONFIGURATION OPTIONS...................................................................................................68
11.
LOOPBACK CONFIGURATION ............................................................................................................70
11.1
P
ER
-C
HANNEL
L
OOPBACK
........................................................................................................................72
12.
ERROR COUNT REGISTERS .................................................................................................................74
12.1
L
INE
-C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR)...............................................................................75
12.1.1
T1 Operation.........................................................................................................................................75
T
ABLE
12-A. T1 L
INE
C
ODE
V
IOLATION
C
OUNTING
O
PTIONS
..............................................................................75
12.1.2
E1 Operation.........................................................................................................................................75
T
ABLE
12-B. E1 L
INE
-C
ODE
V
IOLATION
C
OUNTING
O
PTIONS
..............................................................................75
12.2
P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) ..............................................................................77
12.2.1
T1 Operation.........................................................................................................................................77
T
ABLE
12-C. T1 P
ATH
C
ODE
V
IOLATION
C
OUNTING
A
RRANGEMENTS
................................................................77
12.2.2
E1 Operation.........................................................................................................................................77
12.3
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR)................................................................................78
12.3.1
T1 Operation.........................................................................................................................................78
T
ABLE
12-D. T1 F
RAMES
O
UT
-
OF
-S
YNC
C
OUNTING
A
RRANGEMENTS
.................................................................78
12.3.2
E1 Operation.........................................................................................................................................78
12.4
E-B
IT
C
OUNTER
(EBCR)...........................................................................................................................79
13.
DS0 MONITORING FUNCTION .............................................................................................................80
14.
SIGNALING OPERATION .......................................................................................................................82
14.1
R
ECEIVE
S
IGNALING
.................................................................................................................................82
F
IGURE
14-1. S
IMPLIFIED
D
IAGRAM OF
R
ECEIVE
S
IGNALING
P
ATH
......................................................................82
14.1.1
Processor-Based Signaling...................................................................................................................82
14.1.2
Hardware-Based Receive Signaling .....................................................................................................83
14.2
T
RANSMIT
S
IGNALING
...............................................................................................................................88
F
IGURE
14-2. S
IMPLIFIED
D
IAGRAM OF
T
RANSMIT
S
IGNALING
P
ATH
...................................................................88
14.2.1
Processor-Based Mode .........................................................................................................................88
T
ABLE
14-A. T
IME
S
LOT
N
UMBERING
S
CHEMES
...................................................................................................89
14.2.2
Software Signaling Insertion-Enable Registers, E1 CAS Mode............................................................92
14.2.3
Software Signaling Insertion-Enable Registers, T1 Mode....................................................................94
14.2.4
Hardware-Based Mode.........................................................................................................................94
15.
PER-CHANNEL IDLE CODE GENERATION ......................................................................................95
T
ABLE
15-A. I
DLE
-C
ODE
A
RRAY
A
DDRESS
M
APPING
...........................................................................................95
15.1
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
....................................................................................................96
DS2155
4 of 229
T
ABLE
15-B. GRIC
AND
GTIC F
UNCTIONS
...........................................................................................................97
16.
CHANNEL BLOCKING REGISTERS ..................................................................................................100
17.
ELASTIC STORES OPERATION..........................................................................................................103
17.1
R
ECEIVE
S
IDE
..........................................................................................................................................106
17.1.1
T1 Mode ..............................................................................................................................................106
17.1.2
E1 Mode..............................................................................................................................................106
17.2
T
RANSMIT
S
IDE
.......................................................................................................................................106
17.2.1
T1 Mode ..............................................................................................................................................107
17.2.2
E1 Mode..............................................................................................................................................107
17.3
E
LASTIC
S
TORES
I
NITIALIZATION
...........................................................................................................107
T
ABLE
17-A. E
LASTIC
S
TORE
D
ELAY
A
FTER
I
NITIALIZATION
.............................................................................107
17.4
M
INIMUM
D
ELAY
M
ODE
.........................................................................................................................107
18.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).....................................................108
F
IGURE
18-1. CRC-4 R
ECALCULATE
M
ETHOD
....................................................................................................108
19.
T1 BIT-ORIENTED CODE (BOC) CONTROLLER............................................................................109
19.1
T
RANSMIT
BOC.......................................................................................................................................109
Transmit a BOC ................................................................................................................................................109
19.2
R
ECEIVE
BOC .........................................................................................................................................109
Receive a BOC ..................................................................................................................................................109
20.
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) ........................112
20.1
M
ETHOD
1: H
ARDWARE
S
CHEME
...........................................................................................................112
20.2
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
................................................112
20.3
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
..........................................115
21.
HDLC CONTROLLERS..........................................................................................................................125
21.1
B
ASIC
O
PERATION
D
ETAILS
....................................................................................................................125
21.2
HDLC C
ONFIGURATION
..........................................................................................................................125
T
ABLE
21-A. HDLC C
ONTROLLER
R
EGISTERS
....................................................................................................126
21.2.1
FIFO Control......................................................................................................................................129
21.3
HDLC M
APPING
......................................................................................................................................130
21.3.1
Receive................................................................................................................................................130
21.3.2
Transmit..............................................................................................................................................132
21.3.3
FIFO Information ...............................................................................................................................137
21.3.4
Receive Packet-Bytes Available..........................................................................................................137
21.3.5
HDLC FIFOs ......................................................................................................................................138
21.4
R
ECEIVE
HDLC C
ODE
E
XAMPLE
............................................................................................................139
21.5
L
EGACY
FDL S
UPPORT
(T1 M
ODE
)........................................................................................................139
21.5.1
Overview .............................................................................................................................................139
21.5.2
Receive Section ...................................................................................................................................139
21.5.3
Transmit Section .................................................................................................................................141
21.6
D4/SLC-96 O
PERATION
..........................................................................................................................141
22.
LINE INTERFACE UNIT (LIU) .............................................................................................................142
22.1
LIU O
PERATION
......................................................................................................................................142
DS2155
5 of 229
22.2
R
ECEIVER
................................................................................................................................................142
22.2.1
Receive Level Indicator and Threshold Interrupt...............................................................................143
22.2.2
Receive G.703 Synchronization Signal (E1 Mode).............................................................................143
22.2.3
Monitor Mode .....................................................................................................................................143
F
IGURE
22-1. T
YPICAL
M
ONITOR
A
PPLICATION
...................................................................................................143
22.3
T
RANSMITTER
.........................................................................................................................................144
22.3.1
Transmit Short-Circuit Detector/Limiter............................................................................................144
22.3.2
Transmit Open-Circuit Detector.........................................................................................................144
22.3.3
Transmit BPV Error Insertion ............................................................................................................144
22.3.4
Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................144
22.4
MCLK P
RESCALER
.................................................................................................................................145
22.5
J
ITTER
A
TTENUATOR
...............................................................................................................................145
22.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
.................................................................................................145
F
IGURE
22-2. CMI C
ODING
..................................................................................................................................145
22.7
LIU C
ONTROL
R
EGISTERS
......................................................................................................................146
22.8
R
ECOMMENDED
C
IRCUITS
.......................................................................................................................153
F
IGURE
22-3. B
ASIC
I
NTERFACE
...........................................................................................................................153
F
IGURE
22-4. P
ROTECTED
I
NTERFACE
U
SING
I
NTERNAL
R
ECEIVE
T
ERMINATION
..............................................154
22.9
C
OMPONENT
S
PECIFICATIONS
.................................................................................................................155
T
ABLE
22-A. T
RANSFORMER
S
PECIFICATIONS
.....................................................................................................155
F
IGURE
22-5. E1 T
RANSMIT
P
ULSE
T
EMPLATE
....................................................................................................156
F
IGURE
22-6. T1 T
RANSMIT
P
ULSE
T
EMPLATE
....................................................................................................156
F
IGURE
22-7. J
ITTER
T
OLERANCE
.........................................................................................................................157
F
IGURE
22-8. J
ITTER
T
OLERANCE
(E1 M
ODE
)......................................................................................................157
F
IGURE
22-9. J
ITTER
A
TTENUATION
(T1 M
ODE
)..................................................................................................158
F
IGURE
22-10. J
ITTER
A
TTENUATION
(E1 M
ODE
)................................................................................................158
F
IGURE
22-11. O
PTIONAL
C
RYSTAL
C
ONNECTIONS
.............................................................................................159
23.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION........................160
24.
BERT FUNCTION....................................................................................................................................167
24.1
S
TATUS
....................................................................................................................................................167
24.2
M
APPING
.................................................................................................................................................167
F
IGURE
24-1. S
IMPLIFIED
D
IAGRAM OF
BERT
IN
N
ETWORK
D
IRECTION
............................................................168
F
IGURE
24-2. S
IMPLIFIED
D
IAGRAM OF
BERT
IN
B
ACKPLANE
D
IRECTION
.........................................................168
24.3
BERT R
EGISTER
D
ESCRIPTIONS
.............................................................................................................169
24.4
BERT R
EPETITIVE
P
ATTERN
S
ET
............................................................................................................173
24.5
BERT B
IT
C
OUNTER
...............................................................................................................................174
24.6
BERT E
RROR
C
OUNTER
.........................................................................................................................175
25.
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)..................................................177
T
ABLE
25-A. T
RANSMIT
E
RROR
-I
NSERTION
S
ETUP
S
EQUENCE
...........................................................................177
25.1
N
UMBER
-
OF
-E
RRORS
R
EGISTERS
............................................................................................................179
T
ABLE
25-B. E
RROR
I
NSERTION
E
XAMPLES
.........................................................................................................179
25.1.1
Number-of-Errors Left Register..........................................................................................................180
26.
INTERLEAVED PCM BUS OPERATION (IBO).................................................................................181
26.1
C
HANNEL
I
NTERLEAVE
...........................................................................................................................181
26.2
F
RAME
I
NTERLEAVE
................................................................................................................................181
PDF 
ZIP