MAIN FEATURES
1 of 262
110502
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
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GENERAL DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The backplane is user-
configurable for a TDM or UTOPIA II bus interface.
The DS2156 is composed of a line interface unit
(LIU), framer, HDLC controllers, and a
UTOPIA/TDM backplane interface, and is controlled
by an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS2156 is pin and
software compatible with the DS2155.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75
coax and 120 twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
APPLICATIONS
Inverse Mux ATM (IMA)
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
FEATURES
Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
User-Selectable TDM or UTOPIA II Bus
Interface
Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder for Optical I/F
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
Programmable BERT Generator and Detector
Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75/100/120 T1 and E1 Interfaces
Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued on page 8.
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS2156L
0C to +70C
100 LQFP
DS2156LN
-40C to +85C
100 LQFP
DS2156
T1/E1/J1 Single-Chip Transceiver
TDM/UTOPIA II Interface
www.maxim-ic.com
DS2156
T1/E1/J1
TDM/UTOPIA
T1/E1/J1
NETWORK
BACKPLANE
UTOPIA
TDM
DS2156
2 of 262
TABLE OF CONTENTS
1.
MAIN FEATURES........................................................................................................................................8
2.
DETAILED DESCRIPTION......................................................................................................................11
2.1
B
LOCK
D
IAGRAM
...........................................................................................................................................13
F
IGURE
2-1. B
LOCK
D
IAGRAM
................................................................................................................................13
F
IGURE
2-2. R
ECEIVE AND
T
RANSMIT
LIU (TDM B
ACKPLANE
E
NABLED
)...........................................................14
F
IGURE
2-3. R
ECEIVE AND
T
RANSMIT
LIU (UTOPIA B
ACKPLANE
E
NABLED
).....................................................15
F
IGURE
2-4. R
ECEIVE AND
T
RANSMIT
F
RAMER
/HDLC..........................................................................................16
F
IGURE
2-5. B
ACKPLANE
I
NTERFACE
(TDM B
ACKPLANE
E
NABLED
) ...................................................................17
F
IGURE
2-6. B
ACKPLANE
I
NTERFACE
(UTOPIA B
US
E
NABLED
)...........................................................................18
3.
PIN FUNCTION DESCRIPTION .............................................................................................................19
3.1
TDM B
ACKPLANE
.........................................................................................................................................19
3.1.1
Transmit Side ........................................................................................................................................19
3.1.2
Receive Side ..........................................................................................................................................22
3.2
UTOPIA B
US
.................................................................................................................................................25
3.2.1
Receive Side ..........................................................................................................................................25
3.2.2
Transmit Side ........................................................................................................................................26
3.3
P
ARALLEL
C
ONTROL
P
ORT
P
INS
...................................................................................................................27
3.4
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
........................................................................................................28
3.5
U
SER
O
UTPUT
P
ORT
P
INS
..............................................................................................................................29
3.6
JTAG T
EST
A
CCESS
P
ORT
P
INS
.....................................................................................................................30
3.7
L
INE
I
NTERFACE
P
INS
....................................................................................................................................31
3.8
S
UPPLY
P
INS
..................................................................................................................................................32
3.9
L
AND
G P
ACKAGE
P
INOUT
...........................................................................................................................33
T
ABLE
3-A. P
IN
D
ESCRIPTION
S
ORTED BY
P
IN
N
UMBER
(TDM B
ACKPLANE
E
NABLED
) .....................................33
T
ABLE
3-B. P
IN
D
ESCRIPTION
S
ORTED BY
P
IN
N
UMBER
(UTOPIA B
ACKPLANE
E
NABLED
) ................................35
3.10
10
MM
CSBGA P
IN
C
ONFIGURATION
........................................................................................................37
F
IGURE
3-1. 10
MM
CSBGA P
IN
C
ONFIGURATION
(TDM S
IGNALS
S
HOWN
).........................................................37
4.
PARALLEL PORT .....................................................................................................................................38
4.1
R
EGISTER
M
AP
..............................................................................................................................................38
T
ABLE
4-A. R
EGISTER
M
AP
S
ORTED BY
A
DDRESS
................................................................................................38
4.2
UTOPIA B
US
R
EGISTERS
..............................................................................................................................44
T
ABLE
4-B. UTOPIA R
EGISTER
M
AP
.....................................................................................................................44
5.
SPECIAL PER-CHANNEL REGISTER OPERATION.........................................................................45
6.
PROGRAMMING MODEL.......................................................................................................................47
F
IGURE
6-1. P
ROGRAMMING
S
EQUENCE
.................................................................................................................47
6.1
P
OWER
-U
P
S
EQUENCE
...................................................................................................................................48
6.1.1
Master Mode Register...........................................................................................................................48
6.2
I
NTERRUPT
H
ANDLING
..................................................................................................................................49
6.3
S
TATUS
R
EGISTERS
........................................................................................................................................49
6.4
I
NFORMATION
R
EGISTERS
.............................................................................................................................50
6.5
I
NTERRUPT
I
NFORMATION
R
EGISTERS
..........................................................................................................50
7.
CLOCK MAP ..............................................................................................................................................51
F
IGURE
7-1. C
LOCK
M
AP
(TDM M
ODE
).................................................................................................................51
8.
T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................52
8.1
T1 C
ONTROL
R
EGISTERS
...............................................................................................................................52
DS2156
3 of 262
8.2
T1 T
RANSMIT
T
RANSPARENCY
.....................................................................................................................57
8.3
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
....................................................................................57
8.4
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
.......................................................................58
T
ABLE
8-A. T1 A
LARM
C
RITERIA
..........................................................................................................................60
9.
E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................61
9.1
E1 C
ONTROL
R
EGISTERS
...............................................................................................................................61
T
ABLE
9-A. E1 S
YNC
/R
ESYNC
C
RITERIA
...............................................................................................................62
9.2
A
UTOMATIC
A
LARM
G
ENERATION
................................................................................................................65
9.3
E1 I
NFORMATION
R
EGISTERS
........................................................................................................................66
T
ABLE
9-B. E1 A
LARM
C
RITERIA
...........................................................................................................................67
10.
COMMON CONTROL AND STATUS REGISTERS ............................................................................68
10.1
T1/E1 S
TATUS
R
EGISTERS
........................................................................................................................69
11.
I/O PIN CONFIGURATION OPTIONS...................................................................................................75
12.
LOOPBACK CONFIGURATION ............................................................................................................77
12.1
P
ER
-C
HANNEL
L
OOPBACK
........................................................................................................................79
13.
ERROR COUNT REGISTERS .................................................................................................................81
13.1
L
INE
-C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR)...............................................................................82
13.1.1
T1 Operation.........................................................................................................................................82
T
ABLE
13-A. T1 L
INE
-C
ODE
V
IOLATION
C
OUNTING
O
PTIONS
..............................................................................82
13.1.2
E1 Operation.........................................................................................................................................82
T
ABLE
13-B. E1 L
INE
-C
ODE
V
IOLATION
C
OUNTING
O
PTIONS
..............................................................................82
13.2
P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) ..............................................................................84
13.2.1
T1 Operation.........................................................................................................................................84
T
ABLE
13-C. T1 P
ATH
C
ODE
V
IOLATION
C
OUNTING
A
RRANGEMENTS
................................................................84
13.2.2
E1 Operation.........................................................................................................................................84
13.3
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR)................................................................................85
13.3.1
T1 Operation.........................................................................................................................................85
T
ABLE
13-D. T1
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNTING
A
RRANGEMENTS
.................................................................85
13.3.2
E1 Operation.........................................................................................................................................85
13.4
E-B
IT
C
OUNTER
(EBCR)...........................................................................................................................86
14.
DS0 MONITORING FUNCTION .............................................................................................................87
15.
SIGNALING OPERATION .......................................................................................................................89
15.1
R
ECEIVE
S
IGNALING
.................................................................................................................................89
F
IGURE
15-1. S
IMPLIFIED
D
IAGRAM OF
R
ECEIVE
S
IGNALING
P
ATH
......................................................................89
15.1.1
Processor-Based Signaling...................................................................................................................89
15.1.2
Hardware-Based Receive Signaling .....................................................................................................90
15.2
T
RANSMIT
S
IGNALING
...............................................................................................................................95
F
IGURE
15-2. S
IMPLIFIED
D
IAGRAM OF
T
RANSMIT
S
IGNALING
P
ATH
...................................................................95
15.2.1
Processor-Based Mode .........................................................................................................................95
T
ABLE
15-A. T
IME
S
LOT
N
UMBERING
S
CHEMES
...................................................................................................96
15.2.2
Software Signaling Insertion-Enable Registers, E1 CAS Mode............................................................99
15.2.3
Software Signaling Insertion-Enable Registers, T1 Mode..................................................................101
15.2.4
Hardware-Based Mode.......................................................................................................................101
16.
PER-CHANNEL IDLE CODE GENERATION ....................................................................................102
T
ABLE
16-A. I
DLE
-C
ODE
A
RRAY
A
DDRESS
M
APPING
.........................................................................................102
16.1
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
..................................................................................................103
T
ABLE
16-B. GRIC
AND
GTIC F
UNCTIONS
.........................................................................................................104
DS2156
4 of 262
17.
CHANNEL BLOCKING REGISTERS ..................................................................................................107
18.
ELASTIC STORES OPERATION..........................................................................................................110
18.1
R
ECEIVE
S
IDE
..........................................................................................................................................113
18.1.1
T1 Mode ..............................................................................................................................................113
18.1.2
E1 Mode..............................................................................................................................................113
18.2
T
RANSMIT
S
IDE
.......................................................................................................................................113
18.2.1
T1 Mode ..............................................................................................................................................114
18.2.2
E1 Mode..............................................................................................................................................114
18.3
E
LASTIC
S
TORES
I
NITIALIZATION
...........................................................................................................114
T
ABLE
18-A. E
LASTIC
S
TORE
D
ELAY
A
FTER
I
NITIALIZATION
.............................................................................114
18.4
M
INIMUM
D
ELAY
M
ODE
.........................................................................................................................114
19.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).....................................................115
F
IGURE
19-1. CRC-4 R
ECALCULATE
M
ETHOD
....................................................................................................115
20.
T1 BIT-ORIENTED CODE (BOC) CONTROLLER............................................................................116
20.1
T
RANSMIT
BOC.......................................................................................................................................116
Transmit a BOC ................................................................................................................................................116
20.2
R
ECEIVE
BOC .........................................................................................................................................116
Receive a BOC ..................................................................................................................................................116
21.
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) ........................119
21.1
M
ETHOD
1: H
ARDWARE
S
CHEME
...........................................................................................................119
21.2
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
................................................119
21.3
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
..........................................122
22.
HDLC CONTROLLERS..........................................................................................................................132
22.1
B
ASIC
O
PERATION
D
ETAILS
....................................................................................................................132
22.2
HDLC C
ONFIGURATION
..........................................................................................................................132
T
ABLE
22-A. HDLC C
ONTROLLER
R
EGISTERS
....................................................................................................133
22.2.1
FIFO Control......................................................................................................................................136
22.3
HDLC M
APPING
......................................................................................................................................137
22.3.1
Receive................................................................................................................................................137
22.3.2
Transmit..............................................................................................................................................139
22.3.3
FIFO Information ...............................................................................................................................144
22.3.4
Receive Packet-Bytes Available..........................................................................................................144
22.3.5
HDLC FIFOs ......................................................................................................................................145
22.4
R
ECEIVE
HDLC C
ODE
E
XAMPLE
............................................................................................................146
22.5
L
EGACY
FDL S
UPPORT
(T1 M
ODE
)........................................................................................................146
22.5.1
Overview .............................................................................................................................................146
22.5.2
Receive Section ...................................................................................................................................146
22.5.3
Transmit Section .................................................................................................................................148
22.6
D4/SLC-96 O
PERATION
..........................................................................................................................148
23.
LINE INTERFACE UNIT (LIU) .............................................................................................................149
23.1
LIU O
PERATION
......................................................................................................................................149
23.2
R
ECEIVER
................................................................................................................................................149
23.2.1
Receive Level Indicator and Threshold Interrupt...............................................................................150
23.2.2
Receive G.703 Synchronization Signal (E1 Mode).............................................................................150
23.2.3
Monitor Mode .....................................................................................................................................150
F
IGURE
23-1. T
YPICAL
M
ONITOR
A
PPLICATION
...................................................................................................150
23.3
T
RANSMITTER
.........................................................................................................................................151
23.3.1
Transmit Short-Circuit Detector/Limiter............................................................................................151
DS2156
5 of 262
23.3.2
Transmit Open-Circuit Detector.........................................................................................................151
23.3.3
Transmit BPV Error Insertion ............................................................................................................151
23.3.4
Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................151
23.4
MCLK P
RESCALER
.................................................................................................................................152
23.5
J
ITTER
A
TTENUATOR
...............................................................................................................................152
23.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
.................................................................................................152
F
IGURE
23-2. CMI C
ODING
..................................................................................................................................152
23.7
LIU C
ONTROL
R
EGISTERS
......................................................................................................................153
23.8
R
ECOMMENDED
C
IRCUITS
.......................................................................................................................160
F
IGURE
23-3. B
ASIC
I
NTERFACE
...........................................................................................................................160
F
IGURE
23-4. P
ROTECTED
I
NTERFACE
U
SING
I
NTERNAL
R
ECEIVE
T
ERMINATION
..............................................161
23.9
C
OMPONENT
S
PECIFICATIONS
.................................................................................................................162
T
ABLE
23-A. T
RANSFORMER
S
PECIFICATIONS
.....................................................................................................162
F
IGURE
23-5. E1 T
RANSMIT
P
ULSE
T
EMPLATE
....................................................................................................163
F
IGURE
23-6. T1 T
RANSMIT
P
ULSE
T
EMPLATE
....................................................................................................163
F
IGURE
23-7. J
ITTER
T
OLERANCE
.........................................................................................................................164
F
IGURE
23-8. J
ITTER
T
OLERANCE
(E1 M
ODE
)......................................................................................................164
F
IGURE
23-9. J
ITTER
A
TTENUATION
(T1 M
ODE
)..................................................................................................165
F
IGURE
23-10. J
ITTER
A
TTENUATION
(E1 M
ODE
)................................................................................................165
F
IGURE
23-11. O
PTIONAL
C
RYSTAL
C
ONNECTIONS
.............................................................................................166
24.
UTOPIA BACKPLANE INTERFACE ...................................................................................................167
24.1
D
ESCRIPTION
...........................................................................................................................................167
24.1.1
List of Applicable Standards...............................................................................................................167
24.1.2
Acronyms and Definitions...................................................................................................................167
24.2
UTOPIA C
LOCK
M
ODES
.........................................................................................................................168
F
IGURE
24-1. UTOPIA C
LOCKING
C
ONFIGURATIONS
.........................................................................................168
24.3
F
ULL
T1/E1 M
ODE AND
C
LEAR
-C
HANNEL
E1 M
ODE
............................................................................168
24.4
F
RACTIONAL
T1/E1
MODE
......................................................................................................................169
T
ABLE
24-A. UTOPIA C
LOCK
M
ODE
C
ONFIGURATION
......................................................................................169
24.5
T
RANSMIT
O
PERATION
............................................................................................................................170
24.5.1
UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV ......................................................170
F
IGURE
24-2. P
OLLING
P
HASE AND
S
ELECTION
P
HASE AT
T
RANSMIT
I
NTERFACE
..............................................171
F
IGURE
24-3. E
ND AND
R
ESTART OF
C
ELL AT
T
RANSMIT
I
NTERFACE
................................................................172
F
IGURE
24-4. T
RANSMISSION TO
PHY P
AUSED FOR
T
HREE
C
YCLES
...................................................................173
24.5.2
UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) .................................................173
F
IGURE
24-5. E
XAMPLE OF
D
IRECT
S
TATUS
I
NDICATION
, T
RANSMIT
D
IRECTION
..............................................174
24.5.3
Transmit Processing ...........................................................................................................................175
F
IGURE
24-6. T
RANSMIT
C
ELL
F
LOW
...................................................................................................................175
24.6
R
ECEIVE
O
PERATION
...............................................................................................................................176
24.6.1
Receive Processing .............................................................................................................................176
F
IGURE
24-7. C
ELL
-D
ELINEATION
S
TATE
D
IAGRAM
...........................................................................................176
F
IGURE
24-8. H
EADER
C
ORRECTION
S
TATE
M
ACHINE
........................................................................................177
24.6.2
UTOPIA Side Receive: Muxed Mode with One Receive CLAV ..........................................................178
F
IGURE
24-9. P
OLLING
P
HASE AND
S
ELECTION AT
R
ECEIVE
I
NTERFACE
............................................................178
F
IGURE
24-10. E
ND AND
R
ESTART OF
C
ELL
T
RANSMISSION AT
R
ECEIVE
I
NTERFACE
........................................179
24.6.3
UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) .....................................................179
F
IGURE
24-11. E
XAMPLE OF
D
IRECT
S
TATUS
I
NDICATION
, R
ECEIVE
D
IRECTION
...............................................180
24.7
R
EGISTER
D
EFINITIONS
...........................................................................................................................181
24.8
R
ECEIVE
FIFO O
VERRUN
........................................................................................................................192
24.9
UTOPIA D
IAGNOSTIC
L
OOPBACK
..........................................................................................................192
25.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION........................193
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