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050202
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here:
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.
FEATURES
Generates and detects digital patterns for
analyzing and trouble-shooting digital
communications systems
Programmable polynomial length and
feedback taps for generation of any
pseudorandom patterns up to 2
32
- 1; up to 32
taps can be used in the feedback path
Programmable, user-defined pattern registers
for long repetitive patterns up to 512 bytes in
length
Large 48-bit count and bit error count registers
Software-programmable bit error insertion
Fully independent transmit and receive paths
8-bit parallel-control port
Detects polynomial test patterns in the
presence of bit error rates up to 10
-2
Programmable for serial, 4-bit parallel, or 8-bit
parallel data interfaces
Serial mode clock rate is 155MHz; byte mode
is 80MHz for a net 622Mbps; OC-3
Available in 44-pin PLCC
ORDERING INFORMATION
DS2174Q
44-Pin PLCC 0C to +70C
DS2174QN 44-Pin PLCC -40C to +85C
PIN ASSIGNMENT
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Digital-to-Analog Converters (DACs)
CPE Equipment
Bridges
Smart Jack
DESCRIPTION
The DS2174 enhanced bit error rate tester (EBERT) is a software-programmable test-pattern generator,
receiver, and analyzer capable of meeting the most stringent error-performance requir ements of digital
transmission facilities. It features bit-serial, nibble-parallel, and byte-parallel data interfaces, and
generates and uniquely synchronizes to pseudorandom patterns of the form 2
n
- 1, where n can take on
values from 1 to 32, and user-defined repetitive patterns of any length up to 512 octets.
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19 20 21
22 23 24 25
26 27 28
6 5
4 3 2
1 44 43 42 41 40
D2
D1
D0
TDAT7
TDAT6
GND
TDAT5
TDAT4
TDAT3
TDAT2
GND
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
GND
A0
A1
A2
A3
CS
RDAT2 RDAT1
RDAT0 RCLK_EN RCLK
VDD D7 D6
D5 D4 D3
RD WR
TEST TEST GND
VDD TCLK
TCLK_EN
TCLKO TDAT0 TDAT1
www.maxim-ic.com
DS2174
EBERT
DS2174
DS2174
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TABLE OF CONTENTS
1. GENERAL OPERATION ................................................................................................................4
1.1 PATTERN GENERATION ...........................................................................................................4
1.2 PATTERN SYNCHRONIZATION...............................................................................................5
1.3 BIT ERROR RATE (BER) CALCULATION ...............................................................................5
1.4 GENERATING ERRORS ..............................................................................................................5
1.5 CLOCK DISCUSSION..................................................................................................................6
1.6 POWER-UP SEQUENCE..............................................................................................................6
1.7 DETAILED PIN DESCRIPTION..................................................................................................8
2. PARALLEL CONTROL INTERFACE ........................................................................................10
3. CONTROL REGISTERS ...............................................................................................................11
3.1 STATUS REGISTER...................................................................................................................15
3.2 PSEUDORANDOM PATTERN REGISTERS ...........................................................................15
3.3 TEST REGISTER ........................................................................................................................17
3.4 COUNT REGISTERS ..................................................................................................................17
4. RAM ACCESS .................................................................................................................................18
4.1 INDIRECT ADDRESSING .........................................................................................................18
5. DC OPERATION ............................................................................................................................19
6. AC TIMING CHARACTERISTICS .............................................................................................20
6.1 PARALLEL PORT ......................................................................................................................20
6.2 DATA INTERFACE....................................................................................................................22
7. MECHANICAL DIMENSIONS ....................................................................................................24
DS2174
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LIST OF FIGURES
Figure 1-1: BLOCK DIAGRAM .............................................................................................................6
Figure 6-1: READ TIMING ..................................................................................................................20
Figure 6-2: WRITE TIMING ................................................................................................................21
Figure 6-3: TRANSMIT INTERFACE TIMING..................................................................................22
Figure 6-4: RECEIVE INTERFACE TIMING .....................................................................................23
LIST OF TABLES
Table 1-1: PIN ASSIGNMENT...............................................................................................................7
Table 2-1: REGISTER MAP .................................................................................................................10
Table 3-1: MODE SELECT ..................................................................................................................13
Table 3-2: ERROR BIT INSERTION...................................................................................................13
Table 3-3: PSEUDORANDOM PATTERN GENERATION...............................................................16
Table 5-1: RECOMMENDED DC OPERATING CONDITIONS.......................................................19
Table 5-2: DC CHARACTERISTICS...................................................................................................19
Table 6-1: PARALLEL PORT READ TIMING...................................................................................20
Table 6-2: PARALLEL PORT WRITE TIMING .................................................................................21
Table 6-3: TRANSMIT DATA TIMING..............................................................................................22
Table 6-4: RECEIVE DATA TIMING .................................................................................................23
DS2174
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1. GENERAL OPERATION
1.1 Pattern Generation
Polynomial Generation
The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path
of the polynomial generator. It also features a seed register that can be used to preload the polynomial
generator with a seed value. This is done on the rising edge of TL in Control Register 1.
The DS2174 generates polynomial patterns of any length up to and including 2
32
- 1. All of the industry-
standard polynomials can be programmed using the control registers. The polynomial is generated using a
shift register of programmable length and programmable feedback tap positions. The user has access to
all combinations of pattern length and pattern tap location to gene rate industry-standard polynomials or
other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the
polynomial 2
20
- 1. This pattern has the additional requirement that "an output bit is forced to a ONE
whenever the next 14 bits are ZERO." Setting the QRSS bit in Control Register 1 causes the pattern
generator to enforce this rule.
Repetitive Pattern Generation
In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The
programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through
PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is
addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in
the memory.
Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to
store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8
bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that
the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is
used in serial mode: a 5-bit pattern is written to memory 5 times. For example,
To generate a 00001 pattern at the serial output, write these bytes to memory:
RAM ADDRESS BINARY CODE HEX CODE
00h
00010000
10h
01h
01000010
42h
02h
00001000
08h
03h
00100001
21h
04h
10000100
84h
DS2174
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1.2 Pattern Synchronization
Synchronization
The receiver synchronizes to the same pattern that is being transmitted. The pattern must be error free
when the synchronizer is online. Once synchronized, an error density of 6 bits in 64 causes the receiver to
declare loss of pattern sync, set the RLOS bit, and the synchronizer comes back online.
Polynomial Synchronization
Synchronization to polynomial patterns take 50 + n clock cycles (14 + n in nibble mode, 8 + n in byte
mode), where n is the exponent in the polynomial that describes the pattern. Once synchronized, any bit
that does not match the polynomial is counted as a bit error.
Repetitive Pattern Synchronization
Synchronization to repetitive patterns can take several complete repetitions of the entire pattern. The
actual sync time depends on the nature of the pattern and the location of the synchronization pointer.
Errors that occur during synchronization could affect the sync time; at least one complete error-free
repetition must be received before synchronization is declared. Once synchronized, any bit that does not
match the pattern that is programmed in the on-board RAM is counted as a bit error.
1.3 Bit Error Rate (BER) Calculation
Counters
The bit counter is active at all times. Once synchronized, the error counters come online. The receiver has
large 48-bit count registers. These counters accumulate for 50,640 hours at the T1 line rate, 1.544MHz,
and 38,170 hours at the E1 line rate, 2.048MHz. At higher clock rates, the counters saturate quicker, but
at the T3 line rate, the counter still runs for almost 1500 hours, and at 155MHz it runs for 504 hours.
To accumulate BER data, the user toggles the LC bit at T = 0. This clears the accumulators and loads the
contents into the count registers. At T = 0, these results should be ignored. At this point, the device is
counting bits and bit errors. At the end of the specified time interval, the user toggles the LC bit again and
reads the count registers. These are the valid results used to calculate a bit error rate. Remember, the bit
counter is really counting clocks, so in nibble and byte modes the bit counter value needs to be multiplied
by 4 or 8 to get the correct bit count. For longer integration periods, the results of multiple read cyc les
have to be accumulated in software.
1.4 Generating Errors
Through Control Register 2, the user can intentionally inject a particular error rate into the transmitted
data stream. Injecting errors allows users to stress communication links and to check the functionality of
error monitoring equipment along the path.
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