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112099
FEATURES
Single chip DS1 rate transceiver
Supports common framing standards
12 frames/superframe "193S"
24 frames/superframe "193E"
Three zero suppression modes
B7 stuffing
B8ZS
Transparent
Simple serial interface used for config-
uration, control and status monitoring in
"processor" mode
="Hardware" mode requires no host
processor; intended for stand-alone app-
lications
Selectable 0, 2, 4, 16 state robbed bit
signaling modes
Allows mix of "clear" and "non-clear" DS0
channels on same DS1 link
Alarm generation and detection
Receive error detection and counting for
transmission performance monitoring
5V supply, low-power CMOS technology
Surface-mount package available, designated
DS2180AQ
Industrial temperature range of -40
C to
+85
C available, designated DS2180AN or
DS2180AQN
Compatible to DS2186 Transmit Line
Interface, DS2187 Receive Line Interface,
DS2188 Jitter Attenuator, DS2175 T1/CEPT
Elastic Store, DS2290 T1 Isolation Stik, and
DS2291 T1 Long Loop Stik
PIN ASSIGNMENT
DS2180A
T1 Transceiver
www.dalsemi.com
TMSYNC
1
40
VDD
TFSYNC
2
39
RLOS
TCLK
3
38
RFER
TCHCLK
4
37
RBV
TSER
5
36
RCL
TMO
6
35
RNEG
TSIGSEL
7
34
RPOS
TSIGFR
8
33
RST
TABCD
9
32
TEST
TLINK
10
31
RSIGSEL
TLCLK
11
30
RSIGFR
TPOS
12
29
RABCD
TNEG
13
28
RMSYNC
INT
14
27
RFSYNC
SDI
15
26
RSER
SDO
16
25
RCHCLK
CS
17
24
RCLK
SCLK
18
23
RLCLK
SPS
19
22
RLINK
VSS
20
21
RYEL
40-Pin DIP (600-mil)
TCH
C
L
K
N
C
TCL
K
N
C
TM
SY
N
C
TFSYNC
VDD
RLO
S
RF
E
R
RBV
RCL
TSER
TMO
TSIGSEL
TSIGFR
TABCD
TLINK
TLCLK
TPOS
TNEG
INT
SDI
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
RSER
RCHCLK
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
CS
SDO
SC
L
K
SPS
RY
EL
VSS
RLI
N
K
NC
RLC
L
K
RCL
K
NC
19
20
21
23
22
24
25
26
27
5
4
3
1
2
44
43
42
41
DS1386/DS1386P
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DESCRIPTION
The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier
transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12
frames/superframe). The 193E framing mode supports the extended superframe format (24
frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression
and signaling modes.
Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate
framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides
output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and
multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and
transmission errors, and provides output clocks useful for data conditioning and decoding.
The control block is shared between transmit and receive sides. This block determines the frame, zero
suppression, alarm and signaling formats. User access to the control block is by one of two modes.
In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port
which can be used for device configuration, control and status monitoring.
In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into "hard-
wired" select pins. Features such as selection "clear" DS0 channels, insertion of idle code and alteration
of sync algorithm are unavailable in the hardware mode.
DS2180A BLOCK DIAGRAM Figure 1
DS2180A
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TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2
TFSYNC
I
Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3
TCLK
I
Transmit Clock. 1.544 MHz primary clock.
4
TCHCLK
O
Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5
TSER
I
Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6
TMO
O
Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7
TSIGSEL
O
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8
TSIGFR
O
Transmit Signaling Frame. High during signaling frames, low otherwise.
9
TABCD
I
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10
TLINK
I
Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193S-
External S-Bit insertion).
11
TLCLK
O
Transmit Link Clock. 4 kHz demand clock for TLINK input.
12
13
TPOS
TNEG
O
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN
SYMBOL
TYPE
DESCRIPTION
14
INT
1
O
Receive Alarm Interrupt.
Flags host controller during alarm conditions. Active
low, open drain output.
15
SDI
1
I
Serial Data In.
Data for onboard registers. Sampled on rising edge of SCLK.
16
SDO
1
O
Serial Data Out.
Control and status information from onboard registers. Updated
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
17
CS
1
I
Chip Select.
Must be low to write or read the serial port registers.
18
SCLK
1
I
Serial Data Clock.
Used to write or read the serial port registers.
19
SPS
I
Serial Port Select.
Tie to V
DD
to select serial port. Tie to V
SS
to select hardware
mode.
NOTE:
1.
Multifunction pins. See "Hardware Mode Description."
DS2180A
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POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3
PIN
SYMBOL
TYPE
DESCRIPTION
20
V
SS
-
Signal Ground.
0.0 volts.
32
TEST
I
Test Mode.
Tie to V
SS
for normal operation.
40
V
DD
-
Positive Supply.
5.0 volts.
RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4
PIN
SYMBOL
TYPE
DESCRIPTION
21
RYEL
0
Receive Yellow Alarm.
Transitions high when yellow alarm detected, goes low
when alarm clears.
22
RLINK
0
Receive Link Data.
Updated with extracted FDL data one RCLK before start of
odd frames (193E) and held until next update. Updated with extracted S-bit data one
RCLK before start of even frames (193S) and held until next update.
23
RLCLK
0
Receive Link Clock.
4 kHz demand clock for RLINK.
24
RCLK
I
Receive Clock.
1.544 MHz primary clock.
25
RCHCLK
O
Receive Channel Clock.
192 kHz clock identifies time slot (channel) boundaries.
26
RSER
O
Receive Serial Data.
Received NRZ serial data, updated on rising edges of RCLK.
27
RFSYNC
O
Receive Frame Sync.
Extracted 8 kHz clock, one RCLK wide, indicates F-Bit
position in each frame.
28
RMSYNC
O
Receive Multiframe Sync.
Extracted multiframe sync; edge indicates start of
multiframe, 50% duty cycle.
29
RABCD
O
Receive ABCD Signaling.
Extracted signaling data output, valid for each channel
time in signaling frames. In non-signaling frames, RABCD outputs the LSB of each
channel word.
30
RSIGFR
O
Receive Signaling Frame.
High during signaling frames, low during resync and
non-signaling frames.
31
RSIGSEL
O
Receive Signaling Select.
In 193E framing a .667 kHz clock which identifies
signaling frames A and C. A 1.33 kHz clock in 193S.
33
RST
I
Reset.
A high-low transition clears all internal registers and resets receive side
counters. A high-low-high transition will initiate a receive resync.
34
35
RPOS
RNEG
I
Receive Bipolar Data Inputs.
Samples on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
36
RCL
O
Receive Carrier Loss.
High if 32 consecutive 0's appear at RPOS and RNEG; goes
low after next 1.
37
RBV
O
Receive Bipolar Violation.
High during accused bit time at RSER if bipolar
violation detected, low otherwise.
38
RFER
O
Receive Frame Error.
High during F-Bit time when F
T
or F
S
errors occur (193S)
or when FPS or CRC errors occur (193E). Low during resync.
39
RLOS
O
Receive Loss of Sync.
Indicates sync status; high when internal resync is in
progress, low otherwise.
DS2180A
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REGISTER SUMMARY Table 5
REGISTER
ADDRESS
T/R
1
DESCRIPTION/FUNCTION
RSR
0000
R
2
Receive Status Register.
Reports all receive alarm conditions.
RIMR
0001
R
Receive Interrupt Mask Register.
Allows masking of individual alarm-
generated interrupts.
BVCR
0010
R
Bipolar Violation Count Register.
8-bit presettable counter which records
individual bipolar violations.
ECR
0011
R
Error Count Register.
Two independent 4-bit counters which record OOF
occurrences and individual frame bit or CRC errors.
CCR
3
0100
T/R
Common Control Register.
Selects device operating characteristics common
to receive and transmit sides.
RCR
3
0101
R
Receive Control Register.
Programs device operating characteristics
unique to the receive side.
TCR
3
0110
T
Transmit Control Register.
Selects additional transmit side modes.
TIR1
TIR2
TIR3
0111
1000
1001
T
T
T
Transmit Idle Registers.
Designate which outgoing channels are to be
substituted with idle code.
TTR1
TTR2
TTR3
1010
1011
1100
T
T
T
Transmit Transparent Registers.
Designate which outgoing channels are to be
treated transparently. (No robbed bit signaling or bit 7 zero insertion.)
RMR1
RMR2
RMR3
1101
1110
1111
R
R
R
Receive Mark Registers.
Designate which incoming channels are to be replaced
with idle or digital milliwatt codes (under control of RCR).
NOTES:
1.
Transmit or receive side register.
2.
RSR is a read only register; all other registers are read/write.
3.
Reserved bit locations in the control registers should be programmed to 0 to maintain compatibility
with future transceiver products.
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2180A serve as a microprocessor/microcontroller-compatible serial port.
Sixteen onboard registers allow the user to update operational characteristics and monitor device status
via host controller, minimizing hardware interfaces. Port read/write timing is unrelated to the system
transmit and receive timing, allowing asynchronous reads and/or writes by the host.
ADDRESS/COMMAND
Reading or writing the control, configuration or status registers requires writing one address command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4-bit nibble identifies register address. The next two bits are
reserved and must be set to 0 for proper operation. The last bit of the address/ command word enables
burst mode when set; the burst mode causes all registers to be consecutively written or read. Data is
written to and read from the transceiver LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the
CS
input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held on the next falling edge.
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