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080802
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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.
FEATURES
Performs framing and monitoring functions
Supports Superframe and extended
Superframe formats
Four on-board error counters
-
16-bit bipolar violation
-
8-bit CRC
-
8-bit OOF
-
8-bit frame bit error
Indication of the following
-
Yellow and blue alarms
-
Incoming B8ZS code words
-
8 and 16 zero strings
-
Change-of-frame alignment
-
Loss-of-sync
-
Carrier loss
Simple serial interface used for
configuration, control, and status monitoring
Burst mode allows quick access to counters
for status updates
Automatic counter reset feature
Single 5V supply; low-power CMOS
technology
Available in 28-pin DIP and 28-pin PLCC
The DS2182A is upward-compatible from
the original DS2182
The DS2182A includes the following changes
from the original DS2182:
Ability to count excessive zeros
Severely errored-framing-event indication
Updated AIS detection
Updated RCL detection
AIS and RCL alarm clear indications
PIN ASSIGNMENT (Top View)
ORDERING INFORMATION
PART
PIN-
PACKAGE
TEMP
RANGE
DS2182A
28 DIP
0C to +70C
DS2182AN
28 DIP
-40C to +85C
DS2182AQ
28 PLCC
0C to +70C
DS2182AQN
28 PLCC
-40C to +85C
INT
1
28
VDD
SDI
2
27
RLOS
SDO
3
26
RFER
CS
4
25
RBV
SCLK
5
24
RCL
NC
6
23
RNEG
RYEL
7
22
RPOS
RLINK
8
21
RST
RLCLK
9
20
TEST
RCLK
10
19
RSIGSEL
RCHCLK
11
18
RSIGFR
RSER
12
17
RABCD
N.C.
13
16
RMSYNC
VSS
14
15
RFSYNC
28-Pin DIP (600mil)
DS2182A
T1 Line Monitor Chip
www.maxim-ic.com
DS2182A
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DESCRIPTION
The DS2182A T1 line monitor chip is a monolithic CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
T1.231.
Figure 1. BLOCK DIAGRAM
DS2182A
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Table 1. PIN DESCRIPTION
PIN
SYMBOL
TYPE
FUNCTION
1
INT
O
Receive Alarm Interrupt. Flags host controller during alarm conditions.
Active low; open-drain output.
2
SDI
I
Serial Data In. Data for on-board registers. Sampled on rising edge of SCLK.
3
SDO
O
Serial Data Out. Control and status information from on-board registers.
Updated on falling edge of SCLK; tri-stated during serial port write or when
CS is high.
4
CS
I
Chip Select. Must be low to read or write the serial port.
5
SCLK
I
Serial Data Clock. Used to read or write the serial port registers.
6, 13
N.C.
--
No Connect. No internal connection. This pin can be connected to either V
SS
or V
DD
, or it can be floated.
7
RYEL
O
Receive Yellow Alarm. Transitions high when a yellow alarm detected; goes
low when the alarm clears.
8
RLINK
O
Receive Link Data. Updated with extracted FDL data one RCLK before start
of odd frames (193E) and held until next update. Updated with extracted S-bit
data one RCLK before start of even frames (193S) and held until next update.
9
RLCLK
O
Receive Link Clock. 4kHz demand clock for RLINK
10
RCLK
I
Receive Clock. 1.544MHz primary clock
11
RCHCLK
O
Receive Channel Clock. 192kHz clock; identifies timeslot (channel)
boundaries
12
RSER
O
Receive Serial Data. Received NRZ serial data; updated on rising edges of
RCLK
15
RFSYNC
O
Receive Frame Sync. Extracted 8kHz clock, one RCLK wide; F-bit position
in each frame
16
RMSYNC
O
Receive Multiframe Sync. Extracted multiframe sync; positive-going edge
indicates start of multiframe; 50% duty cycle
17
RABCD
O
Receive ABCD Signaling. Extracted signaling data output; valid for each
channel in signaling frames. In non-signaling frames, RABCD outputs the
LSB of each channel word.
18
RSIGFR
O
Receive Signaling Frame. High during signaling frames; low during non-
signaling frames (and during resync)
19
RSIGSEL
O
Receive Signaling Select. In 193E framing, a .667kHz clock that identifies
signaling frames A and C; a 1.33kHz clock in 193S
21
RST
I
Reset. A high-low transition clears all internal registers and resets counters. A
high-low-high transition initiates a resync.
22
23
RPOS
RNEG
I
Receive Bipolar Data Inputs. Sampled on falling of RCLK. Connect together
to receive NRZ data and disable bipolar violation monitoring circuitry.
24
RCL
O
Receive Carrier Loss. High if 192 consecutive 0's appear at RPOS and
RNEG; goes low upon seeing 12.5% 1's density.
25
RBV
O
Receive Bipolar Violation. High during accused bit time at RSER. If bipolar
violation detected, low otherwise.
26
RFER
O
Receive Frame Error. High during F-bit time when FT or FS errors occur
(193S), or when FPS or CRC errors occur (193E). Low during resync.
27
RLOS
O
Receive Loss-of-Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
DS2182A
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Table 2. POWER AND TEST PIN DESCRIPTION
PIN
SYMBOL
TYPE
FUNCTION
14
V
SS
--
Signal Ground. 0V
20
TEST
I
Test Mode. Connect to V
SS
for normal operation.
28
V
DD
--
Positive Supply. 5.0V
Table 3. REGISTER SUMMARY
REGISTER
ADDRESS
FUNCTION
BVCR2
0000
Bipolar Violation Count Register 2. LSW of a 16-bit presettable
counter that records individual bipolar violations.
BVCR1
0001
Bipolar Violation Count Register 1. MSW of a 16-bit presettable
counter that records individual bipolar violations.
CRCCR
0010
CRC Error Count Register. 8-bit presettable counter that records
CRC6 errored words in the 193E frame mode.
OOFCR
0011
OOF Count Register. 8-bit presettable counter that records OOF
events. OOF events are defined by RCR1.5 and RCR1.6.
FECR
0100
Frame Error Count Register. 8-bit presettable counter that records
individual bit errors in the framing pattern.
RSR1
0101
Receive Status Register 1. Reports alarm conditions.
RIMR1
0110
Receive Interrupt Mask Register 1. Allows masking of individual
alarm-generated interrupts from RSR1.
RSR2
0111
Receive Status Register 2. Reports alarm conditions.
RIMR2
1000
Receive Interrupt Mask Register 2. Allows masking of individual
alarm-generated interrupts from RSR2.
RCR1
1001
Receive Control Register 1. Programs device operating
characteristics.
RCR2
1010
Receive Control Register 2. Programs device operating
characteristics.
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven
on-board registers allow the user to update operational characteristics and monitor device status through a
host controller, minimizing hardware interfaces. The port on the DS2182A can be read from or written to
at any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and
RNEG. However, RCLK is needed in order to clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
Reading or writing the control, configuration, or status registers requires writing one address/command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4 bits identify the register address. The next 2 bits are reserved and
must be set to 0 for proper operation. The last bit of the address/ command word enables burst mode
when set; the burst mode causes all registers to be consecutively read or written to. Data is read and
written to the DS2182A LSB first.
DS2182A
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CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the
CS
input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.
All data transfers are terminated if the
CS
input transitions high. Port control logic is disabled and SDO is
tri-stated when
CS
is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into
the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and can be connected to SDI in applications where
the host processor has a bidirectional I/O pin.
BURST MODE
The burst mode allows all on-board registers to be consecutively written to or read by the host processor.
A burst read is used to poll all registers; RSR1 and RSR2 contents are unaffected. This feature minimizes
device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the
address is 0000. A burst is terminated by a low-high transition on
CS
.
ACB: ADDRESS COMMAND BYTE
MSB
LSB
BM
--
--
ADD3
ADD2
ADD1
ADD0
R/
W
SYMBOL
POSITION
FUNCTION
BM
ACB.7
Burst Mode. If set (and register address is 0000), burst read or
write is enabled.
--
ACB.6
Reserved; must be 0 for operation
---
ACB.5
Reserved; must be 0 for operation
ADD3
ACB.4
MSB of register address
ADD0
ACB.1
LSB of register address
R/W
ACB.0
Read/Write Select
0 = write addressed register
1 = read addressed register
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