1 of 17
REV: 060303
GENERAL DESCRIPTION
The DS21Q348 design kit is an evaluation board for
the DS21Q348 3.3V E1/T1/J1 line interface. The
DS21Q348DK is intended to be used as a daughter
card with either the DK2000 or the DK101
motherboards. The board comes complete with a line
interface unit (LIU), transformers, termination
resistors, configuration switches, network connectors,
and an interface to the motherboard.
ORDERING INFORMATION
PART DESCRIPTION
DS21Q348DK
DS21Q348 (Quad BGA) Design Kit
FEATURES
Expedites New Designs by Eliminating First-Pass
Prototyping
Interfaces Directly to the DK101 or DK2000
Motherboards
Demonstrates Key Functions of the DS21Q348
High-Level Software Provides Visual Access to
Registers
Software-Controlled (Register Mapped)
Configuration Switches to Facilitate Clock and
Signal Routing
BNC Connections for 75
W E1
Bantam and RJ48 Connectors for 120
W E1 and
100
W T1
Multitap Transformer Facilitates True Impedance
Matching for 75
W and 120W/100W Paths
DS21Q348DK
3.3V E1/T1/J1 Line Interface
Design Kit Daughter Card
www.maxim-ic.com
DS21Q348DK 3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
2 of 17
COMPONENT LIST
DESIGNATION QTY
DESCRIPTION SUPPLIER
PART
1 1
3.3V E1/T1/J1 line interface, 0C to +70C, 144-pin
BGA
Dallas
Semiconductor
DS21Q348
C1, C2, C6,
C10, C12, C22,
C24
7
0.47
mF 10%, 25V ceramic capacitors (1206)
Digi-Key PCC1891CT-ND
C13C16 4
0.1
mF 10%, 25V ceramic capacitors (1206)
Digi-Key PCC1883CT-ND
C17C20 4
1
mF 10%, 16V ceramic capacitors (1206)
Digi-Key PCC1882CT-ND
C3C5, C7, C8,
C11, C21, C23,
C25, C26
10
0.1
mF 10%, 16V ceramic capacitors (0603)
Digi-Key 311-1088-1-ND
C9 1
10
mF 20%, 16V tantalum capacitors (B case)
Digi-Key PCS3106CT-ND
DS1DS5
5
LED, red, SMD
Digi-Key
P500CT-ND
J1, J6J13
9
Right-angle, 5-pin BNC connectors
Kruvand
UCBJR220
J14
1
Right-angle RJ45, 8-pin, 4-port jack
Molex
43223-8140
J15, J16
2
50-pin, dual row, vertical SMD sockets
Samtec
TFM-125-02-S-D-LC
J2
1
10-pin, dual row, vertical connector
Digi-Key
S2012-05-ND
J3J5
--
8-row by 2-column pin strip, 0.1" centers, 0.025" post NA
Lab Stock
R17, R20, R21,
R25, R28R36,
R53
14
10k
W 1%, 1/10W resistors (0805)
Digi-Key P10.0KCCT-ND
R18, R19,
R22R24, R26,
R27
7
51.1
W 1%, 1/10W resistors (0805)
Digi-Key P51.1CCT-ND
R1R16,
R37R41,
R54R57
25
0
W 5%, 1/8W resistors (1206)
Digi-Key P0.0ETR-ND
R42, R43
2
1.0k
W 1%, 1/10W resistors (0805)
Digi-Key P1.00KCCT-ND
R44R51 8
61.9
W 1%, 1/8W resistors (1206)
Digi-Key P61.9FCT-ND
T1T4
4
XFMR, dual, 16-pin SMT
Pulse
Engineering
TX1099
U1
1
Xilinx CPLD 72 macrocell, 100-pin TQFP, 3.3V
Avnet
XC95142XL-
10TQ100C
DS21Q348DK 3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
3 of 17
BASIC OPERATION
Hardware Configuration
Using the DK101 Processor Board:
Connect the daughter card to the DK101 processor board.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the TIM 5V supply headers are unused.)
All processor-board DIP switch settings should be in the ON position with the exception of the flash-
programming switch, which should be OFF.
From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation in options were used, click the Start button on the Windows toolbar and select
Programs
ChipViewChipView.
Using the DK2000 Processor Board:
Connect the daughter card to the DK2000 processor board.
Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected
to connector J2.
From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation in options were used, click the Start button on the Windows toolbar and select
Programs
ChipViewChipView.
General:
Upon power-up, the RCL LEDs are lit, and the INT LED is off.
After power-up, the RCL LEDs extinguish upon external loopback.
Due to the dual winding transformer, only the 120W line build-out configuration setting is needed to cover 75W
E1 and 120
W E1.
Quick Setup (Register View)
The PC loads the program, offering a choice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View.
The program requests a definition file. Select DS21Q348DK02A0_CPLD.DEF.
The Register View Screen appears, showing the register names, acronyms, and values. Note the CPLD def file
contains a link such that the def file for the DS21Q348 is also loaded. Selection among the def files is
accomplished using the drop-down box on the right-hand side of the program window.
From the drop-down box select the DS21Q348 def file and configure register CCR3 of ports 1 through 4 with a
90h.
The device begins transmitting a pseudorandom bit sequence. Upon external loopback, the RCL LED
extinguishes, denoting that the device has found a carrier and has successfully decoded the
pseudorandom bit sequence. For more advanced configurations, please refer to the DS21Q348 data
sheet.
Miscellaneous:
Clock frequencies are provided by a register-mapped CPLD, which is on the DS21Q348 daughter card.
The definition file for this CPLD is named DS21Q348DK02A0_CPLD.def. See CPLD Register Map definitions.
DS21Q348DK 3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
4 of 17
ADDRESS MAP
The DK101 daughter card address space begins at 0x81000000.
The DK2000 daughter card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets in the Daughter Card Address Map table are relative to the beginning of the daughter card address
space.
Daughter Card Address Map
OFFSET DEVICE
FUNCTION
0X0000 to 0X0015
CPLD
Board ID, clock and signal routing
0X2000 to 0X2015
LIU Port 1
0X3000 to 0X3015
LIU Port 2
0X4000 to 0X4015
LIU Port 3
0X5000 to 0X5015
LIU Port 4
Board is populated with either the DS21Q348 or the DS21448.
Please see the factory data sheet for details.
Registers in the CPLD can be easily modified using ChipView, a host-based user-interface software, with the
definition file named ds21q348dk02A0_cpld.def. This file is included as part of the design kit documentation
download (accessed through the DS21Q348's quick view data sheet). The definition file for the LIU is named
DS21Q348.def.
CPLD Register Map
OFFSET REGISTER
TYPE
FUNCTION
0X0000 BID Read-Only
Board
ID
0X0001 --
--
Unused
0X0002
XBIDH
Read-Only
High Nibble Extended Board ID
0X0003
XBIDM
Read-Only
Middle Nibble Extended Board ID
0X0004
XBIDL
Read-Only
Low Nibble Extended Board ID
0X0005
BREV
Read-Only
Board FAB Revision
0X0006
AREV
Read-Only
Board Assembly Revision
0X0007 PREV Read-Only
PLD
Revision
0X0011 MCLK_SRC Read-Write
MCLK Source Register
0X0012
TCLK1_SRC
Read-Write
TCLK1 Source Register
0X0013
TCLK2_SRC
Read-Write
TCLK2 Source Register
0X0014
TCLK3_SRC
Read-Write
TCLK3 Source Register
0X0015
TCLK4_SRC
Read-Write
TCLK4 Source Register
ID Registers
OFFSET NAME
FUNCTION
0X0000
BID
Board ID. BID is read-only with a value of 0xD.
0X0002
XBIDH High Nibble Extended Board ID. XBIDH is read-only with a value of 0x00.
0X0003
XBIDM Middle Nibble Extended Board ID. XBIDM is read-only with a value of 0x02.
0X0004
XBIDL Low Nibble Extended Board ID. XBIDL is read-only with a value of 0x00.
0X0005
BREV Board FAB Revision. BREV is read-only and displays the current fab revision.
0X0006
AREV Board Assembly Revision. AREV is read-only and displays the assembly revision.
0X0007
PREV PLD Revision. PREV is read-only and displays the current PLD firmware revision.
DS21Q348DK 3.3V E1/T1/J1 Line Interface Design Kit Daughter Card
5 of 17
Control Registers
The control registers are used set the clock frequency on the MCLK and TCLK pins. Options are 1.544MHz,
2.048MHz, external source (through AUX CLK BNC), and tri-state.
MCLK_SRC: MCLK SOURCE (OFFSET = 0x0011) INITIAL VALUE = 0x1
(MSB)
(LSB)
-- -- -- -- HI_Z
EXTOSC
2048MHZ
1544MHZ
NAME POSITION
FUNCTION
HI_Z
MCLK_SRC.3
1 = Tri-state MCLK.
EXTOSC
MCLK_SRC.2
1 = Connect MCLK to the external oscillator.
2048MHZ
MCLK_SRC.1
1 = Connect MCLK to the 2.048MHz clock.
1544MHZ
MCLK_SRC.0
1 = Connect MCLK to the 1.544MHz clock.
TCLK1_SRC: TCLK SOURCE (OFFSET = 0x0012) INITIAL VALUE = 0x1
(MSB)
(LSB)
-- -- -- -- HI_Z
EXTOSC
2048MHZ
1544MHZ
NAME POSITION
FUNCTION
HI_Z
TCLK1_SRC.3
1 = Tri-state TCLK1.
EXTOSC
TCLK1_SRC.2
1 = Connect TCLK1 to the external oscillator.
2048MHZ
TCLK1_SRC.1
1 = Connect TCLK1 to the 2.048MHz clock.
1544MHZ
TCLK1_SRC.0
1 = Connect TCLK1 to the 1.544MHz clock.
TCLK2_SRC: TCLK SOURCE (OFFSET = 0x0013) INITIAL VALUE = 0x1
(MSB)
(LSB)
-- -- -- -- HI_Z
EXTOSC
2048MHZ
1544MHZ
NAME POSITION
FUNCTION
HI_Z
TCLK2_SRC.3
1 = Tri-state TCLK2.
EXTOSC
TCLK2_SRC.2
1 = Connect TCLK2 to the external oscillator.
2048MHZ
TCLK2_SRC.1
1 = Connect TCLK2 to the 2.048MHz clock.
1544MHZ
TCLK2_SRC.0
1 = Connect TCLK2 to the 1.544MHz clock.
TCLK3_SRC: TCLK SOURCE (OFFSET = 0x0014) INITIAL VALUE = 0x1
(MSB)
(LSB)
-- -- -- -- HI_Z
EXTOSC
2048MHZ
1544MHZ
NAME POSITION
FUNCTION
HI_Z
TCLK3_SRC.3
1 = Tri-state TCLK3.
EXTOSC
TCLK3_SRC.2
1 = Connect TCLK3 to the external oscillator.
2048MHZ
TCLK3_SRC.1
1 = Connect TCLK3 to the 2.048MHz clock.
1544MHZ
TCLK3_SRC.0
1 = Connect TCLK3 to the 1.544MHz clock.
PDF 
ZIP