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080902
FEATURES
4096 bits Electrically Erasable Programmable
Read-Only Memory (EEPROM)
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute identity because no two parts are
alike
Built-in multidrop controller ensures
compatibility with other MicroLANTM
products
Memory partitioned into sixteen 256-bit pages
for packetizing data
256-bit scratchpad with strict read/write
protocols ensures integrity of data transfer
Reduces control, address, data, and power to a
single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3kbps
Overdrive mode boosts communication speed
to 142kps
8-bit family code specifies DS2433
communication requirements to reader
Presence detector acknowledges when reader
first applies voltage
Low cost PR-35 or 8-pin SO surface mount
package
Reads and writes over a wide voltage range of
2.8V to 6.0V from -40C to +85C
PIN ASSIGNMENT
PIN DESCRIPTION
PR-35
SO
Pin 1
Ground
NC
Pin 2
Data
NC
Pin 3
NC
Data
Pin 4
--
Ground
Pin 5-8
--
NC
ORDERING INFORMATION
DS2433 PR-35
package
DS2433S
8-pin SOIC package
DS2433S/T&R
Tape & Reel version of
DS2433S
DS2433X
Chip Scale Pkg., Tape &
Reel
DS2433X-S
Chip-Scale Pkg, 2.5k pc.,
Tape & Reel
SILICON LABEL DESCRIPTION
The DS2433 4kb 1-Wire
EEPROM identifies and stores relevant information about the product to which
it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2433 consists of a factory-lasered registration
DS2433
4kb 1-Wire EEPROM
PRELIMINARY
NC
NC
DATA
GND
NC
2
3
4
8
7
6
5
1
8-Pin SO (208mil)
NC
NC
NC
1 2 3
3
2
1
PR-35
BOTTOM VIEW
PR-35
1-Wire is a registered trademark of Dallas Semiconductor.
MicroLAN is a trademark of Dallas Semiconductor.
www.maxim-ic.com
DS2433
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number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (23h) plus
4096 bits of user-programmable EEPROM. The power to read and write the DS2433 is derived entirely
from the 1-Wire communication line. The memory is organized as sixteen pages of 256 bits each. The
scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the
scratchpad where it may be read back for verification. A copy scratchpad command will then transfer the
data to memory. This process insures data integrity when modifying the memory. The 64-bit registration
number provides a guaranteed unique identity which allows for absolute traceability and acts as node
address if multiple DS2433 are connected in parallel to form a local network. Data is transferred serially
via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SOIC
packages provide a compact enclosure that allows standard assembly equipment to handle the device
easily for attachment to printed circuit boards or wiring. Typical applications include storage of
calibration constants, board identification and product revision status.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2433. The DS2433 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,
and 3) 4096-bit EEPROM. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The
bus master must first provide one of the six ROM Function Commands, 1) Read ROM, 2) Match ROM,
3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion
of an overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode
where all subsequent communication occurs at a higher speed. The protocol required for these ROM
function commands is described in Figure 9. After a ROM function command is successfully executed,
the memory functions become accessible and the master may provide any one of the four memory
function commands. The protocol for these memory function commands is described in Figure 7. All data
is read and written least significant bit first.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry "steals" power
whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and
voltage requirements are met.
DS2433
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Figure 1. DS2433 BLOCK DIAGRAM
64-BIT LASERED ROM
Each DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton
Standards.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8
th
bit of the family code has been entered, then the serial number
is entered. After the 48
th
bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.
MEMORY
The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages
called memory. The DS2433 contains pages 0 through 15 that make up the 4096-bit EEPROM. The
scratch-pad is an additional page that acts as a buffer when writing to memory.
ADDRESS REGISTERS AND TRANSFER STATUS
Because of the serial data transfer, the DS2433 employs three address registers, called TA1, TA2 and E/S
(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be
written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte
counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,
the master only has read access to this register. The lower five bits of the E/S register indicate the address
of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the
E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or
if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear
the PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address also
determine the address within the scratchpad, where intermediate storage of data will begin. This address
is called byte offset. If the target address (TA1) for a Write command is 03CH for example, then the
scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only four
iButton is a registered trademark of Dallas Semiconductor.
DS2433
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bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency,
the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0.
Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH.
However, it is possible to write one or several contiguous bytes somewhere within a page. The ending
offset together with the Partial Flag support the master checking the data integrity after a Write command.
The highest valued bit of the E/S register, called AA is valid only if the PF flag reads 0. If PF is 0 and AA
is 1, a copy has taken place. The AA bit is cleared when the device receives a write scratchpad command.
WRITING WITH VERIFICATION
To write data to the DS2433, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address and data at the end of the write scratchpad command sequence.
Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the
communication was successful and proceed to the Copy Scratchpad command. If the master could not
receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to verify
data integrity. As preamble to the scratchpad data, the DS2433 repeats the target address TA1 and TA2
and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not
need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag
together with a cleared PF flag indicates that the Write command was not recognized by the device. If
everything went correctly, both flags are cleared and the ending offset indicates the address of the last
byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the
contents of these registers by reading the scratchpad or derive it from the target address and the amount of
data to be written. As soon as the DS2433 has received these bytes correctly, it will copy the data to the
requested location beginning at the target address.
DS2433
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Figure 2. HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL
Figure 3. 64-BIT LASERED ROM
MSB
LSB
8-Bit CRC Code
48-Bit Serial Number
8-Bit Family Code (23h)
MSB
LSB MSB
LSB MSB
LSB
Figure 4. 1-WIRE CRC GENERATOR
MEMORY FUNCTION COMMANDS
The "Memory Function Flow Chart" (Figure 7) describes the protocols necessary for accessing the
memory. An example follows the flowchart. The communication between master and DS2433 takes place
either at regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the
Overdrive Mode the DS2433 assumes regular speed.
WRITE SCRATCHPAD COMMAND [0FH]
After issuing the write scratchpad command, the master must first provide the 2-byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at
the byte offset (T4:T0). The ending offset (E4:E0) will be the byte offset at which the master stops
INPUT
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