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REV 072205
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.
GENERAL DESCRIPTION
The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
TNEG
RCLK
TPOS
TCLK
RPOS
RNEG
Software Control,
Hardware Control
and JTAG
Transmitter
Receiver
RLOS
1
8
RTIP
RRING
MODESEL
Jtag
TTTIP
TRING
FEATURES
8 Complete E1, T1, or J1 Short Haul Line
Interface Units
Independent E1, T1, or J1 Selections
Internal Software-Selectable Transmit and
Receive-Side Termination
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode and
AMI or HDB3/ B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss-of-Signal Detection as per
T1.231, G.775, and ETSI 300233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally Adapted
for T1 or E1 Use
Built-In BERT Tester for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Hardware Mode Interface Support
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Specification Compliance to the Latest T1 and
E1 Standards--ANSI T1.102, AT&T Pub 62411,
T1.231, T1.403, ITU G.703, G.742, G.775,
G.823, ETSI 300 166, and ETSI 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as per IEEE 1149.1
160-Pin PBGA/144-Pin
eLQFP
Package
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS26303G-XXX*
0C to +70C
160 PBGA
DS26303GN-XXX*
-40C to +85C
160 PBGA
DS26303L-XXX
0C to +70C
144 eLQFP
DS26303L-XXX+
0C to +70C
144 eLQFP
DS26303LN-XXX
-40C to +85C
144 eLQFP
DS26303LN-XXX+
-40C to +85C
144 eLQFP
Note: When XXX is 075, the part defaults to 75
W impedance in E1
mode; when XXX is 120, the part defaults to 120
W impedance.
+ Denotes a lead-free/ROHS-compliant device.
* Future product--contact factory for availability.
DS26303
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
www.maxim-ic.com
DS26303
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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TABLE OF CONTENTS
1
DETAILED DESCRIPTION ............................................................................................................ 6
2
TELECOM SPECIFICATIONS COMPLIANCE............................................................................... 7
3
BLOCK DIAGRAMS ...................................................................................................................... 9
4
PIN DESCRIPTION ...................................................................................................................... 11
4.1
H
ARDWARE AND
H
OST
P
ORT
O
PERATION
.................................................................................... 21
4.1.1
Hardware Mode................................................................................................................................... 21
4.1.2
Serial Port Operation .......................................................................................................................... 22
4.1.3
Parallel Port Operation........................................................................................................................ 23
4.1.4
Interrupt Handling................................................................................................................................ 23
5
REGISTERS................................................................................................................................. 25
5.1
R
EGISTER
D
ESCRIPTION
............................................................................................................. 30
5.1.1
Primary Registers................................................................................................................................ 30
5.1.2
Secondary Registers........................................................................................................................... 38
5.1.3
Individual LIU Registers ...................................................................................................................... 39
5.1.4
BERT Registers .................................................................................................................................. 46
6
FUNCTIONAL DESCRIPTION ..................................................................................................... 53
6.1
P
OWER
-U
P AND
R
ESET
.............................................................................................................. 53
6.2
M
ASTER
C
LOCK
......................................................................................................................... 53
6.3
T
RANSMITTER
............................................................................................................................ 54
6.3.1
Transmit Line Templates .................................................................................................................... 55
6.3.2
LIU Transmit Front End....................................................................................................................... 57
6.3.3
Dual-Rail Mode ................................................................................................................................... 58
6.3.4
Single-Rail Mode................................................................................................................................. 58
6.3.5
Zero Suppression--B8ZS or HDB3 .................................................................................................... 58
6.3.6
Transmit Power-Down ........................................................................................................................ 58
6.3.7
Transmit All Ones................................................................................................................................ 58
6.3.8
Drive Failure Monitor........................................................................................................................... 58
6.4
R
ECEIVER
.................................................................................................................................. 58
6.4.1
Peak Detector and Slicer .................................................................................................................... 58
6.4.2
Clock and Data Recovery ................................................................................................................... 59
6.4.3
Loss of Signal...................................................................................................................................... 59
6.4.4
AIS ...................................................................................................................................................... 60
6.4.5
Bipolar Violation and Excessive Zero Detector................................................................................... 61
6.4.6
LIU Receiver Front End ...................................................................................................................... 61
6.5
H
ITLESS
-P
ROTECTION
S
WITCHING
(HPS).................................................................................... 61
6.6
J
ITTER
A
TTENUATOR
.................................................................................................................. 63
6.7
G.772 M
ONITOR
........................................................................................................................ 64
6.8
L
OOPBACKS
............................................................................................................................... 64
6.8.1
Analog Loopback ................................................................................................................................ 64
6.8.2
Digital Loopback.................................................................................................................................. 64
6.8.3
Remote Loopback ............................................................................................................................... 65
6.9
BERT........................................................................................................................................ 66
6.9.1
Configuration and Monitoring.............................................................................................................. 66
6.9.2
Receive Pattern Detection .................................................................................................................. 67
6.9.3
Transmit Pattern Generation............................................................................................................... 68
6.10
S
PECIAL
T
EST
F
UNCTIONS
.......................................................................................................... 69
6.10.1
Metal Options ...................................................................................................................................... 69
7
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................. 70
7.1
TAP C
ONTROLLER
S
TATE
M
ACHINE
............................................................................................ 71
7.2
I
NSTRUCTION
R
EGISTER
............................................................................................................. 74
7.3
T
EST
R
EGISTERS
....................................................................................................................... 75
7.3.1
Boundary Scan Register ..................................................................................................................... 75
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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7.3.2
Bypass Register .................................................................................................................................. 75
7.3.3
Identification Register ......................................................................................................................... 75
8
OPERATING PARAMETERS....................................................................................................... 76
9
THERMAL CHARACTERISTICS ................................................................................................. 77
10
AC CHARACTERISTICS ............................................................................................................. 78
10.1
L
INE
I
NTERFACE
C
HARACTERISTICS
............................................................................................ 78
10.2
P
ARALLEL
H
OST
I
NTERFACE
T
IMING
C
HARACTERISTICS
............................................................... 79
10.3
S
ERIAL
P
ORT
............................................................................................................................. 91
10.4
S
YSTEM
T
IMING
......................................................................................................................... 92
10.5
JTAG T
IMING
............................................................................................................................ 94
11
PACKAGE INFORMATION.......................................................................................................... 95
11.1
E
LQFP P
ACKAGE
O
UTLINE
(1
OF
2)............................................................................................ 95
11.2
E
LQFP P
ACKAGE
O
UTLINE
(2
OF
2)............................................................................................ 96
12
DOCUMENT REVISION HISTORY .............................................................................................. 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................... 9
Figure 3-2. Receive Logic Detail................................................................................................................................ 10
Figure 3-3. Transmit Logic Detail............................................................................................................................... 10
Figure 4-1. 160-Pin PBGA Pin Assignment............................................................................................................... 19
Figure 4-2. 144-Pin eLQFP Pin Assignment ............................................................................................................. 20
Figure 4-3. Serial Port Operation for Write Access ................................................................................................... 22
Figure 4-4. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 22
Figure 4-5. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 23
Figure 4-6. Interrupt Handling Flow Diagram ............................................................................................................ 24
Figure 6-1. Pre-Scaler PLL and Clock Generator...................................................................................................... 53
Figure 6-2. T1 Transmit Pulse Templates ................................................................................................................. 55
Figure 6-3 E1 Transmit Pulse Templates .................................................................................................................. 56
Figure 6-4. LIU Front End .......................................................................................................................................... 57
Figure 6-5. HPS Logic ............................................................................................................................................... 62
Figure 6-6. HPS Block Diagram................................................................................................................................. 62
Figure 6-7. Jitter Attenuation ..................................................................................................................................... 63
Figure 6-8. Analog Loopback..................................................................................................................................... 64
Figure 6-9. Digital Loopback...................................................................................................................................... 65
Figure 6-10. Remote Loopback ................................................................................................................................. 65
Figure 6-11. PRBS Synchronization State Diagram.................................................................................................. 67
Figure 6-12. Repetitive Pattern Synchronization State Diagram............................................................................... 68
Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 70
Figure 7-2. TAP Controller State Diagram................................................................................................................. 73
Figure 10-1. Intel Nonmuxed Read Cycle ................................................................................................................. 80
Figure 10-2. Intel Mux Read Cycle ............................................................................................................................ 81
Figure 10-3. Intel Nonmux Write Cycle...................................................................................................................... 83
Figure 10-4. Intel Mux Write Cycle ............................................................................................................................ 84
Figure 10-5. Motorola Nonmux Read Cycle .............................................................................................................. 86
Figure 10-6. Motorola Mux Read Cycle ..................................................................................................................... 87
Figure 10-7. Motorola Nonmux Write Cycle .............................................................................................................. 89
Figure 10-8. Motorola Mux Write Cycle ..................................................................................................................... 90
Figure 10-9. Serial Bus Timing Write Operation........................................................................................................ 91
Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 91
Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 91
Figure 10-12. Transmitter Systems Timing ............................................................................................................... 92
Figure 10-13. Receiver Systems Timing ................................................................................................................... 93
Figure 10-14. JTAG Timing ....................................................................................................................................... 94
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LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7
Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8
Table 4-1. Pin Descriptions........................................................................................................................................ 11
Table 4-2. Hardware Mode Configuration Examples................................................................................................. 21
Table 4-3. Parallel Port Mode Selection and Pin Functions ...................................................................................... 23
Table 5-1. Primary Register Set ................................................................................................................................ 25
Table 5-2. Secondary Register Set............................................................................................................................ 26
Table 5-3. Individual LIU Register Set ....................................................................................................................... 26
Table 5-4. BERT Register Set ................................................................................................................................... 27
Table 5-5. Primary Register Set Bit Map ................................................................................................................... 28
Table 5-6. Secondary Register Set Bit Map .............................................................................................................. 28
Table 5-7. Individual LIU Register Set Bit Map.......................................................................................................... 28
Table 5-8. BERT Register Bit Map ............................................................................................................................ 29
Table 5-9. G.772 Monitoring Control ......................................................................................................................... 33
Table 5-10. TST Template Select Transmitter Register ............................................................................................ 35
Table 5-11. Template Selection................................................................................................................................. 36
Table 5-12. Address Pointer Bank Selection............................................................................................................. 37
Table 5-13. MCLK Selections .................................................................................................................................... 41
Table 5-14. PLL Clock Select .................................................................................................................................... 44
Table 5-15. Clock A Select ........................................................................................................................................ 44
Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters ............................................ 54
Table 6-2. Registers Related to Control of DS26303 Transmitters ........................................................................... 54
Table 6-3. DS26303 Template Selections................................................................................................................. 55
Table 6-4. LIU Front-End Values ............................................................................................................................... 57
Table 6-5. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications............................................................... 59
Table 6-6. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications................................................................. 60
Table 6-7. AIS Detection and Reset Criteria ............................................................................................................. 60
Table 6-8. Registers Related to AIS Detection.......................................................................................................... 60
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting ..................................................................... 61
Table 6-10. Pseudorandom Pattern Generation........................................................................................................ 66
Table 6-11. Repetitive Pattern Generation ................................................................................................................ 66
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 74
Table 7-2. ID Code Structure..................................................................................................................................... 75
Table 7-3 Device ID Codes........................................................................................................................................ 75
Table 8-1. Recommended DC Operating Conditions ................................................................................................ 76
Table 8-2. Capacitance.............................................................................................................................................. 76
Table 8-3. DC Characteristics.................................................................................................................................... 76
Table 9-1. Thermal Characteristics............................................................................................................................ 77
Table 10-1. Transmitter Characteristics .................................................................................................................... 78
Table 10-2. Receiver Characteristics......................................................................................................................... 78
Table 10-3. Intel Read Mode Characteristics ............................................................................................................ 79
Table 10-4. Intel Write Cycle Characteristics ............................................................................................................ 82
Table 10-5. Motorola Read Cycle Characteristics ..................................................................................................... 85
Table 10-6. Motorola Write Cycle Characteristics ..................................................................................................... 88
Table 10-7. Serial Port Timing Characteristics .......................................................................................................... 91
Table 10-8. Transmitter System Timing .................................................................................................................... 92
Table 10-9. Receiver System Timing......................................................................................................................... 93
Table 10-10. JTAG Timing Characteristics................................................................................................................ 94
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