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REV: 070105

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS26324 is a 16-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
impedance matching. A single bill of material can
support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered. The device is offered a 256-pin TEBGA,
the smallest package available for a 16-channel LIU.

APPLICATIONS

T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers

FUNCTIONAL DIAGRAM

TNEG

RCLK

TPOS

TCLK

RPOS
RNEG

SOFTWARE CONTROL

AND JTAG

TRANSMITTER

RECEIVER

LOSS

RTIP

RRING

JTAG

TTIP

TRING

FEATURES

16 E1, T1, or J1 Short-Haul Line Interface Units

Independent E1, T1, or J1 selections

Software-Selectable Transmit and Receive-Side
Impedance Matching

Crystal Less Jitter Attenuator

Selectable Single-Rail and Dual-Rail Mode and
AMI or HDB3/ B8ZS Line Encoding and
Decoding

Detection and Generation of AIS

Digital/Analog Loss of Signal Detection as per
T1.231, G.775, and ETSI 300233

External Master Clock can be Multiple of 2.048 or
1.544MHz for T1/J1 or E1 Operation (This clock
will be internally adapted for T1 or E1 Use.)

Receiver Signal Level Indicator from -2.5dB to
-20dB in 2.5dB Increments

Two Built-In BERT Testers for Diagnostics

8-Bit Parallel Interface Support for Intel or
Motorola Mode, or 4-Wire Serial Interface

Transmit Short-Circuit Protection

G.772 Nonintrusive Monitoring

Receive Monitor Mode Handles Combinations of
14dB or 20dB of Resistive Attenuation Along with
12dB to 30dB of Cable Attenuation.

Specification Compliance to the Latest T1/E1
Standards--ANSI T1.102, AT&T Pub 62411,
T1.231, T1.403, ITU G.703, G.742, G.775,
G.823, ETSI 300 166, and ETSI 300 233

Single 3.3V Supply with 5V Tolerant I/O

JTAG Boundary Scan as per IEEE 1149.1

ORDERING INFORMATION

PART TEMP

RANGE

PIN-PACKAGE

DS26324G

0°C to +70°C

256 TEBGA

DS26324GN

-40°C to +85°C 256 TEBGA

DS26324

3.3V, 16-Channel, E1/T1/J1

Short-Haul Line Interface Unit

www.maxim-ic.com

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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TABLE OF CONTENTS

STANDARDS COMPLIANCE ........................................................................................................ 6

1.1

ELECOM

PECIFICATIONS

OMPLIANCE

.......................................................................................................... 6

DETAILED DESCRIPTION............................................................................................................. 7

BLOCK DIAGRAMS....................................................................................................................... 8

PIN DESCRIPTION ...................................................................................................................... 10

FUNCTIONAL DESCRIPTION ..................................................................................................... 18

5.1

ORT

PERATION

......................................................................................................................................... 18

5.1.1

Serial Port Operation .......................................................................................................................... 18

5.1.2

Parallel Port Operation........................................................................................................................ 19

5.1.3

Interrupt Handling................................................................................................................................ 19

5.2

OWER

-U

P AND

ESET

................................................................................................................................. 20

5.3

ASTER CLOCK

............................................................................................................................................. 20

5.4

RANSMITTER

............................................................................................................................................... 21

5.4.1

Transmit Line Templates .................................................................................................................... 23

5.4.2

LIU Transmit Front End....................................................................................................................... 26

5.4.3

Dual Rail.............................................................................................................................................. 27

5.4.4

Single-Rail Mode................................................................................................................................. 27

5.4.5

Zero Suppression--B8ZS or HDB3 .................................................................................................... 27

5.4.6

Transmit Power-Down ........................................................................................................................ 27

5.4.7

Transmit All Ones................................................................................................................................ 28

5.4.8

Drive Failure Monitor........................................................................................................................... 28

5.5

ECEIVER

..................................................................................................................................................... 28

5.5.1

Receiver Monitor Mode....................................................................................................................... 28

5.5.2

Peak Detector and Slicer .................................................................................................................... 28

5.5.3

Receive Level Indicator....................................................................................................................... 28

5.5.4

Clock and Data Recovery ................................................................................................................... 29

5.5.5

Loss of Signal...................................................................................................................................... 29

5.5.6

AIS ...................................................................................................................................................... 30

5.5.7

Bipolar Violation and Excessive Zero detector ................................................................................... 31

5.6

ITTER

TTENUATOR

..................................................................................................................................... 31

5.7

G.772 M

ONITOR

........................................................................................................................................... 32

5.8

OOPBACKS

.................................................................................................................................................. 32

5.8.1

Analog Loopback ................................................................................................................................ 32

5.8.2

Digital Loopback.................................................................................................................................. 33

5.8.3

Remote Loopback ............................................................................................................................... 34

5.9

BERT........................................................................................................................................................... 34

5.9.1

General Description ............................................................................................................................ 34

5.9.2

Configuration and Monitoring.............................................................................................................. 35

5.9.3

Receive Pattern Detection .................................................................................................................. 36

5.9.4

Transmit Pattern Generation............................................................................................................... 38

REGISTER MAPS AND DEFINITION .......................................................................................... 39

6.1

EGISTER

ESCRIPTION

................................................................................................................................ 48

6.1.1

Primary Register Bank ........................................................................................................................ 48

6.1.2

Secondary Register Bank ................................................................................................................... 60

6.1.3

Individual LIU Register Bank............................................................................................................... 62

6.1.4

BERT Registers .................................................................................................................................. 78

JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ................................. 85

7.1

TAP C

ONTROLLER

TATE

ACHINE

............................................................................................................... 86

7.2

NSTRUCTION

EGISTER

................................................................................................................................ 89

7.3

EST

EGISTERS

........................................................................................................................................... 90

7.4

OUNDARY

CAN

EGISTER

.......................................................................................................................... 90

7.5

YPASS

EGISTER

........................................................................................................................................ 90

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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7.6

DENTIFICATION

EGISTER

............................................................................................................................. 90

DC ELECTRICAL CHARACTERIZATION ................................................................................... 91

AC TIMING CHARACTERISTICS ................................................................................................ 92

9.1

INE

NTERFACE

HARACTERISTICS

............................................................................................................... 92

9.2

ARALLEL

OST

NTERFACE

IMING

HARACTERISTICS

.................................................................................. 93

9.3

ERIAL

ORT

.............................................................................................................................................. 105

9.4

YSTEM

IMING

........................................................................................................................................... 106

9.5

JTAG T

IMING

.............................................................................................................................................. 108

PIN CONFIGURATION............................................................................................................... 109

PACKAGE INFORMATION........................................................................................................ 110

THERMAL INFORMATION ........................................................................................................ 111

REVISION HISTORY.................................................................................................................. 112

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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LIST OF FIGURES

Figure 3-1. Block Diagram ........................................................................................................................................... 8

Figure 3-2. Receive Logic Detail.................................................................................................................................. 9

Figure 3-3. Transmit Logic Detail................................................................................................................................. 9

Figure 5-1. Serial Port Operation for Write Access ................................................................................................... 18

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 18

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 19

Figure 5-4. Interrupt Handling Flow Diagram ............................................................................................................ 20

Figure 5-5. Pre-Scaler PLL and Clock Generator...................................................................................................... 21

Figure 5-6. T1 Transmit Pulse Templates ................................................................................................................. 24

Figure 5-7. E1 Transmit Pulse Templates ................................................................................................................. 25

Figure 5-8. LIU Front End .......................................................................................................................................... 26

Figure 5-9. Jitter Attenuation ..................................................................................................................................... 32

Figure 5-10. Analog Loopback................................................................................................................................... 33

Figure 5-11. Digital Loopback.................................................................................................................................... 33

Figure 5-12. Remote Loopback ................................................................................................................................. 34

Figure 5-13. PRBS Synchronization State Diagram.................................................................................................. 36

Figure 5-14. Repetitive Pattern Synchronization State Diagram............................................................................... 37

Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 85

Figure 7-2. TAP Controller State Diagram................................................................................................................. 88

Figure 9-1. Intel Nonmuxed Read Cycle ................................................................................................................... 94

Figure 9-2. Intel Mux Read Cycle .............................................................................................................................. 95

Figure 9-3. Intel Nonmux Write Cycle........................................................................................................................ 97

Figure 9-4. Intel Mux Write Cycle .............................................................................................................................. 98

Figure 9-5. Motorola Nonmux Read Cycle .............................................................................................................. 100

Figure 9-6. Motorola Mux Read Cycle ..................................................................................................................... 101

Figure 9-7. Motorola Nonmux Write Cycle .............................................................................................................. 103

Figure 9-8. Motorola Mux Write Cycle ..................................................................................................................... 104

Figure 9-9. Serial Bus Timing Write Operation........................................................................................................ 105

Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 105

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 105

Figure 9-12. Transmitter Systems Timing................................................................................................................ 106

Figure 9-13. Receiver Systems Timing ................................................................................................................... 107

Figure 9-14. JTAG Timing ....................................................................................................................................... 108

Figure 10-1.256-Ball TEBGA ................................................................................................................................... 109

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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LIST OF TABLES

Table 4-1. Pin Descriptions........................................................................................................................................ 10

Table 5-1. Parallel Port Mode Selection and Pin Functions ...................................................................................... 19

Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters ............................................ 22

Table 5-3. Registers Related to Control of DS26324 Transmitters ........................................................................... 22

Table 5-4. Template Selections for the DS26324 for Short-Haul Mode .................................................................... 23

Table 5-5. LIU Front-End Values ............................................................................................................................... 27

Table 5-6. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications............................................................... 29

Table 5-7. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications................................................................. 30

Table 5-8. AIS Detection and Reset Criteria ............................................................................................................. 30

Table 5-9. Registers Related to AIS Detection.......................................................................................................... 30

Table 5-10. BPV, Code Violation, and Excessive Zero Error Reporting ................................................................... 31

Table 5-11. Pseudorandom Pattern Generation........................................................................................................ 35

Table 5-12. Repetitive Pattern Generation ................................................................................................................ 35

Table 6-1. Primary Register Set ................................................................................................................................ 40

Table 6-2. Secondary Register Set............................................................................................................................ 41

Table 6-3. Individual LIU Register Set ....................................................................................................................... 42

Table 6-4. BERT Register Set ................................................................................................................................... 43

Table 6-5. Primary Register Set Bit Map ................................................................................................................... 44

Table 6-6. Secondary Register Set Bit Map .............................................................................................................. 45

Table 6-7. Individual LIU Register Set Bit Map.......................................................................................................... 46

Table 6-8. BERT Register Bit Map ............................................................................................................................ 47

Table 6-9. G.772 Monitoring Control (LIU 1) ............................................................................................................. 52

Table 6-10. G.772 Monitoring Control (LIU 9) ........................................................................................................... 53

Table 6-11. TST Template Select Transmitter Register ............................................................................................ 56

Table 6-12. TST Template Select Transmitter Register ............................................................................................ 56

Table 6-13. Template Selection................................................................................................................................. 57

Table 6-14. Address Pointer Bank Selection............................................................................................................. 59

Table 6-15. MCLK Selections for the DS26324......................................................................................................... 65

Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection ................................................................................ 69

Table 6-17. Receiver Signal Level............................................................................................................................. 70

Table 6-18. Bit Error Rate Transceiver Select for Channels 18 .............................................................................. 73

Table 6-19. Bit Error Rate Transceiver Select for Channels 916 ............................................................................ 74

Table 6-20. PLL Clock Select .................................................................................................................................... 76

Table 6-21. Clock A Select ........................................................................................................................................ 76

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 89

Table 7-2. ID Code Structure..................................................................................................................................... 90

Table 7-3. Device ID Codes....................................................................................................................................... 90

Table 8-1. DC Pin Logic Levels ................................................................................................................................. 91

Table 8-2. Pin Capacitance ....................................................................................................................................... 91

Table 8-3. Supply Current and Output Voltage ......................................................................................................... 91

Table 9-1. Transmitter Characteristics....................................................................................................................... 92

Table 9-2. Receiver Characteristics........................................................................................................................... 92

Table 9-3. Intel Read Mode Characteristics .............................................................................................................. 93

Table 9-4. Intel Write Cycle Characteristics .............................................................................................................. 96

Table 9-5. Motorola Read Cycle Characteristics ....................................................................................................... 99

Table 9-6. Motorola Write Cycle Characteristics ..................................................................................................... 102

Table 9-7. Serial Port Timing Characteristics .......................................................................................................... 105

Table 9-8. Transmitter System Timing..................................................................................................................... 106

Table 9-9. Receiver System Timing......................................................................................................................... 107

Table 9-10. JTAG Timing Characteristics................................................................................................................ 108

Table 12-1. Thermal Characteristics........................................................................................................................ 111

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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1 STANDARDS COMPLIANCE

1.1 Telecom

Specifications

Compliance

The DS26324 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1
and E1 Specifications and relevant sections that are applicable to the DS26324.

· T1-Related Telecommunications Specifications

· ANSI T1.102- Digital Hierarchy Electrical Interface

· ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring

· ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface

· G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s

· G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy

· Pub 62411 High Capacity Terrestrial Digital Service

· ITUT G.772 Protected monitoring points provided on digital transmission systems

· E1-Related Telecommunications Specifications

· ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces

· ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048 Kbit/s

· ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448 Kbit/s

· ITUT G.772 Protected monitoring points provided on digital transmission systems

· ITUT G.775 Loss of signal (LOS) and alarm indication signal (AIS) defect detection and clearance criteria

· ETSI 300 166 Physical and electrical characteristics of hierarchical digital interfaces for equipment using

the 2,048 kbit/s-based plesiosynchronous or synchronous digital hierarchies

· ETSI 300 233 Integrated Services Digital Network (ISDN)

· G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s

· G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy

· Pub 62411 High Capacity Terrestrial Digital Service

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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2 DETAILED DESCRIPTION

The DS26324 is a single-chip, 16-channel, short-haul line interface unit for T1 (1.544Mbps) and E1 (2.048Mbps)
applications. Sixteen independent receivers and transmitters are provided in a single TEBGA package. The LIUs
can be individually selected for T1, J1, or E1 operation. The LIU requires a single master reference clock. This
clock can be either 1.544MHz or 2.048MHz or multiples thereof, and either frequency can be internally adapted for
T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive paths reduces external
component count. The transmit waveforms are compliant to G.703 and T1.102 specification. The DS26324
provides software-selectable internal transmit termination for 100

W T1 twisted pair, 110W J1 twisted pair, 120W E1

twisted pair, and 75

W E1 coaxial applications. The transmitters have fast high-impedance capability and can be

individually powered down.

The receivers can function with up to an 18dB receive signal attenuation. A monitor gain setting also can be
enabled to provide 14dB and 20dB of resistive gain. The DS26324 can be configured as a 14-channel LIU with
channel 1 and 9 used for nonintrusive monitoring in accordance with G.772. The receivers and transmitters can be
programmed into single or dual-rail mode. AMI or HDB3/B8ZS encoding and decoding is selectable in single-rail
mode. A 128-bit, crystal-less, on-board jitter attenuator for each LIU can be placed in the receive or transmit
directions. The jitter attenuator meets the ETSI CTR12/13 ITU G.736, G.742, G.823, and AT&T PUB62411
specifications.

The DS26324 detects and generates AIS in accordance with T1.231, G.775, and ETSI 300233. Loss of signal is
detected in accordance with T1.231, G.775, and ETSI 300233. The DS26324 can perform digital, analog, remote,
and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.

The DS26324 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial
port selection is also available for configuration and monitoring of the device.

The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled
into the RTIP and RRING pins of the DS26324. The user has the option to select internal impedance matching to
75

W, 100W, 110W, or 120W with the use of a single external resistor. The device recovers clock and data from the

analog signal and passes it through a selectable jitter attenuator outputting the received line clock at RCLK and
data at RPOS and RNEG.

The DS26324 receivers can recover data and clock for up to 18 dB of attenuation of the transmitted signals.
Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8. Receiver 9 can monitor the
performance of receivers 10 to 16 or transmitters 10 to 16.

The DS26324 contains 16 identical transmitters. Digital-transmit data is input at TPOS/TNEG with reference to
TCLK. The data at these pins can be single rail or dual rail. This data is processed by waveshaping circuitry and
the line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.

The DS26324 drives the E1 or T1 line from the TTIP and TRING pins by a 1:2 coupling transformer. The DS26324
supports the use of either a 1:1 or a 1:2 transformer on the receive side through the receiver turns ratio (RTR) bit.
Receive internal impedance matching allows one external resistance value to work for all T1/J1/E1 modes.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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4 PIN DESCRIPTION

Table 4-1. Pin Descriptions

NAME PIN

TYPE

FUNCTION

ANALOG TRANSMIT AND RECEIVE

TTIP1 E1
TTIP2 F1
TTIP3 K1
TTIP4 L1
TTIP5 T5
TTIP6 T6
TTIP7 T10
TTIP8 T11
TTIP9 M16

TTIP10 L16
TTIP11 G16
TTIP12 F16
TTIP13 A12
TTIP14 A11
TTIP15 A7
TTIP16 A6

Analog

output

Transmit Bipolar Tip for Channels 116. These pins are
differential line driver Tip outputs. These pins can be high
impedance if pin OE is low. When "1" is set in the Output Enable
Register

bit, the associated TTIPn pin will be enabled when

the OE pin is high. The differential outputs of TTIPn and TRINGn
can provide internal matched impedance for E1 75

W, E1 120W, T1

100

W, or J1 110W.

If the TCLK input for a given LIU is held low for 64 MCLKs that
LIUs transmitter is powered down and the TTIP/TRING outputs
are high impedance.

TRING1 E2
TRING2 F2
TRING3 K2
TRING4 L2
TRING5 R5
TRING6 R6
TRING7 R10
TRING8 R11
TRING9 M15

TRING10 L15
TRING11 G15
TRING12 F15
TRING13 B12
TRING14 B11
TRING15 B7
TRING16 B6

Analog

output

Transmit Bipolar Ring for Channels 116. These pins are
differential line driver Ring outputs. These pins can be High-Z if pin
OE is low. When "1" is set in the Output Enable Register

bit,

the associated TRINGn pin will be enabled when the OE pin is
high. The differential outputs of TTIPn and TRINGn can provide
internal matched impedance for E1 75

W, E1 120W, T1 100W, or J1

110

If the TCLK input for a given LIU is held low for 64 MCLKs that
LIUs transmitter is powered down and the TTIP/TRING outputs
are high impedance.

RTIP1 A1
RTIP2 C1
RTIP3 H1
RTIP4 N1
RTIP5 T1
RTIP6 T3
RTIP7 T8
RTIP8 T13
RTIP9 T16

RTIP10 P16
RTIP11 J16
RTIP12 D16
RTIP13 A16
RTIP14 A14
RTIP15 A9
RTIP16 A4

Analog

input

Receive Bipolar Tip for Channels 116. Receive analog input for
differential receiver. Data and clock are recovered and output at
RPOS/RNEG and RCLK pins respectively. The differential inputs
of RTIPn and RRINGn can provide impedance matching with
external resistance for E1 75

W, E1 120W, T1 100W, or J1 110W.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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NAME PIN

TYPE

FUNCTION

RRING1 A2
RRING2 C2
RRING3 H2
RRING4 N2
RRING5 R1
RRING6 R3
RRING7 R8
RRING8 R13
RRING9 T15

RRING10 P15
RRING11 J15
RRING12 D15
RRING13 B16
RRING14 B14
RRING15 B9
RRING16 B4

Analog

Input

Receive Bipolar Ring for Channels 116. Receive analog input
for differential receiver. Data and clock are recovered and output
at RPOS/RNEG and RCLK pins respectively. The differential
inputs of RTIPn and RRINGn can provide impedance matching
with external resistance for E1 75

W, E1 120W, T1 100W, or J1

110

DIGITAL Tx/Rx

TPOS1/TDATA1 F6
TPOS2/TDATA2 G7
TPOS3/TDATA3 J6
TPOS4/TDATA4 K6
TPOS5/TDATA5 L9
TPOS6/TDATA6 N5
TPOS7/TDATA7 P12
TPOS8/TDATA8 M11
TPOS9/TDATA9 L11

TPOS10/TDATA10 J11
TPOS11/TDATA11 G11
TPOS12/TDATA12 C14
TPOS13/TDATA13 F9
TPOS14/TDATA14 E7
TPOS15/TDATA15 N12
TPOS16/TDATA16 D5

Transmit Positive Data Input for Channels 116. When
DS26324 is configured in dual-rail mode, the data input to TPOSn
is output as a positive pulse on the line (TIP and Ring).

Transmit Data Input for Channels 116. When the device is
configured in single-rail mode NRZ data is input to TDATAn. The
data is sampled on the falling edge of TCLKn and encoded
HDB3/B8ZS or AMI before being output to the line.

TNEG1 C3
TNEG2 J14
TNEG3 J5
TNEG4 G10
TNEG5 M6

Transmit Negative Data for Channels 116. When DS26324 is
configured in dual-rail mode. The data input to TNEGn is output as
a negative mark on the line. TPOS and TNEG in dual-rail mode
result in positive and negative pulses sent on the line:

TNEG6 P6

TPOSn TNEGn

OUTPUT

PULSE

TNEG7 P7

0 Space

TNEG8 K9

1 Negative

Mark

TNEG9 L12

0 Positive

Mark

TNEG10 J12

1 Space

TNEG11 H11
TNEG12 E13
TNEG13 G8
TNEG14 F7
TNEG15 C6
TNEG16 C5

TCLK1 F5
TCLK2 G4
TCLK3 G9
TCLK4 H6

Transmit Clock for Channels 116. The transmit clock must be
1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock
used to sample the data TPOS/TNEG or TDAT on the falling edge.
The expected TCLK can be inverted.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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NAME PIN

TYPE

FUNCTION

TCLK5 M7
TCLK6 L8
TCLK7 L10
TCLK8 P9
TCLK9 K11

TCLK10 K12
TCLK11 F14
TCLK12 E12
TCLK13 C11
TCLK14 D12
TCLK15 N7
TCLK16 D11

If TCLKn is `high' for 16 or more MCLKs, then transmit all ones
(TAOs) is sent to the line side of the corresponding transmit
channel. When TCLKn starts clocking again, normal operation will
begin again for the corresponding transmit channel.

If TCLKn is `low' for 64 or more MCLKs, the corresponding
transmit channel on the line side powers down and is put into high
impedance. When TCLKn starts clocking again the corresponding
transmit channel powers up and comes out of high impedance.

RPOS1/RDATA1 F4
RPOS2/RDATA2 F3
RPOS3/RDATA3 L3
RPOS4/RDATA4 L4
RPOS5/RDATA5 K8
RPOS6/RDATA6 M9
RPOS7/RDATA7 P8
RPOS8/RDATA8 M12
RPOS9/RDATA9 M14

RPOS10/RDATA10 K13
RPOS11/RDATA11 G12
RPOS12/RDATA12 E14
RPOS13/RDATA13 C12
RPOS14/RDATA14 C10
RPOS15/RDATA15 C8
RPOS16/RDATA16 E5

tri-state

Receive Positive Data Output for Channels 116. In dual-rail
mode, the NRZ data output indicates a positive pulse on
RTIP/RRING. Upon detecting a LOS, AIS can be inserted if AISEL
bit in the

is set otherwise the pins will be active. AIS insertion

can also be controlled on an individual LIU basis by

IAISEL

register. If a given receiver is in power-down mode the associated
RPOS pin is high impedance.

Receive Data Output for Channels 116. In single-rail mode,
NRZ data is sent out on this pin. If a given receiver is in power-
down mode, the associated RPOS pin is high impedance.

Note: During an LOS condition, the RPOS/RDATA outputs remain
active.

RNEG1/CV1 E3
RNEG2/CV2 G5
RNEG3/CV3 K4
RNEG4/CV4 M3
RNEG5/CV5 L7
RNEG6/CV6 M10
RNEG7/CV7 P11
RNEG8/CV8 K10
RNEG9/CV9 M13

RNEG10/CV10 L14
RNEG11/CV11 F13
RNEG12/CV12 F11
RNEG13/CV13 E10
RNEG14/CV14 C9
RNEG15/CV15 C7
RNEG16/CV16 J3

tri-state

Receive Negative Data Output for Channels 116. In dual-rail
mode, the NRZ data output indicates a negative pulse on
RTIP/RRING. Upon detecting an LOS, AIS can be inserted if
AISEL bit in the

is set; otherwise, the pins are active. AIS

insertion can also be controlled on an individual LIU basis by

IAISEL

associated RNEG pin is high impedance.

Code Violation for Channels 116. In single-rail mode, bipolar
violation, code violation, and excessive zeros are reported on
CVn. If HDB3 or B8ZS is not selected, this pin indicates only
BPVs. If a given receiver is in power-down mode the associated
CV pin is high impedance.

RCLK1 D3
RCLK2 G6
RCLK3 K3
RCLK4 K5
RCLK5 P5
RCLK6 M8
RCLK7 P10
RCLK8 P13
RCLK9 L13

tri-state

Receive Clock for Channels 1 to 16. The receive data
(RPOS/RNEG) is clocked out on the rising edge of RCLK. If a
given receiver is in power-down mode the RCLK is high
impedance. Upon a LOS being detected, the RCLK is switched
from the recovered clock to MCLK. RCLK can be inverted by the
RCLKI register.

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NAME PIN

TYPE

FUNCTION

HOST SELECTION

MODESEL A3 I

Mode Selection. This pin is used to select the control mode of the
DS26324:
Low

® serial host mode

High

® parallel host mode

MOTEL B3

Motorola Intel Select. When this pin is low Motorola mode is
selected. When this pin is high Intel mode is selected.

CSB P14

Chip-Select Bar. This signal must be low during all accesses to
the registers.

SCLK/ALE/ASB N14 I

Shift Clock. In the serial host mode, this pin is the serial clock.
Data on SDI is clocked on the rising edge of SCLK. The data is
clocked on SDO on the rising edge of SCLK if CLKE is high. If
CLKE is low the data on SDO is clocked on the falling edge of
SCLK.

Address Latch Enable. In parallel Intel multiplexed mode, the
address lines are latched on the falling edge of ALE.

Address Strobe Bar. In parallel Motorola multiplexed mode the
address is sampled on the falling edge of ASB.

Note: Tie ALE/ASB pin high if using nonmuxed mode.

RDB/RWB H14 I

Read Bar. Intel host mode, this pin has to be low for read
operation.

Read Write Bar. In Motorola mode this pin is low for write
operation and high for read operation.

SDI/WRB/DSB G14 I

Serial Data Input. In the serial host mode, this pin is the serial
input SDI. It is sampled on the rising edge of SCLK.

Write Bar. In Intel host mode, this pin is active low during write
operation. The data or address (multiplexed mode) is sampled on
the rising edge of WRB.

Data Strobe Bar. In the parallel Motorola mode, this pin is active
low. During a write operation the data or address is sampled on
the rising edge of DSB. During a read operation the data or
address is driven on the rising edge of DSB. In the nonmultiplexed
Motorola mode, the address bus (A [5:0]) is latched on the falling
edge of DSB.

SD0/RDYB/ACKB C13 O

Serial Data Out. In serial host mode, the SDO data is output on
this pin. If a serial write is in progress this pin is high impedance.
During a read, SDO is high impedance when the SDI is in
command/address mode. If CLKE is low, SDO is output on the
rising edge of SCLK, if CLKE is high on the falling edge.

Ready Bar Output. A high on this pin reports to the host that the
cycle is not complete and wait states must be inserted. A low
means the cycle is complete.

Acknowledge Bar. In Motorola parallel mode, a low on this pin
indicates that the read data is available for the host or that the
written data cycle is complete.

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NAME PIN

TYPE

FUNCTION

INTB D7

open
drain

Interrupt Bar (Active Low). This signal is tri-stated when RST pin
is low. This interrupt signal is driven low when an event is detected
on any of the enabled interrupt sources in any of the register
banks. When there are no active and enabled interrupt sources,
the pin can be programmed to either drive high or as open drain.
The reset default is open drain when there are no active enabled
interrupt sources. All interrupt sources are disabled when RST = 0
and they must be programmed to be enabled.

D7/AD7 N3
D6/AD6 P3
D5/AD5 M4
D4/AD4 L5
D3/AD3 K7
D2/AD2 P4
D1/AD1 M5
D0/AD0 L6

I/O,

tri-state

Data Bus 70. In nonmultiplexed host mode, these pins are the
bidirectional data bus.

Address/Data Bus 70. In multiplexed host mode, these pins are
the bidirectional address/data bus. Note: AD7 and AD6 do not
carry address information.

In serial host mode, these pins should be grounded.

A5/BSWP E4

Address 5. In the host nonmultiplexed mode, this is the most
significant bit of the address bus.

Bit Swap. In serial host mode, this bit defines the serial data
position to be MSB first when low and LSB first when high.

In multiplexed host mode, this pin should be grounded.

A4 C4
A3 H5
A2 G3
A1 H3
A0 N10

Address Bus 40. These five pins are address pins in the parallel
host mode. In serial host mode and multiplexed host mode, these
pins should be grounded.

OE R12

Output Enable. If this pin is pulled low, all the transmitter outputs
(TTIP and TRING) are high impedance. If pulled high, all the
transmitters are enabled when the associated Output Enable

bit is set.

If GC.RTCTL is set, the OE pin is granted control of the receiver
internal termination. When OE is low, receiver internal termination
is high impedance. When OE is high, receiver termination is
enabled. The receiver can still monitor incoming signals even
when termination is high impedance.

CLKE/MUX T14 I

Clock Edge. If CLKE is high, SDO is clocked out on falling edge
of SCLK and if low SDO is on rising edge of SCLK.

Multiplexed/Nonmultiplexed Select Pin. When in parallel port
mode, this pin is used to select multiplexed address and data
operation or separate address and data. When mux is a high,
multiplexed address and data is used and when mux is low,
nonmultiplexed is used.

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5 FUNCTIONAL DESCRIPTION

5.1 Port

Operation

5.1.1 Serial

Port

Operation

Setting MODESEL = `low' enables the serial bus interface on the DS26324. Port read/write timing is unrelated to
the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section

9.3

for the

AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when
BSWP is low.

Figure 5-1

Figure 5-3

show operation with LSB first.

This port is compatible with the SPI interface defined for Motorola Processors. An example of this is the MMC2107
from Motorola.

Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next 6 bits identify the register address (A1 to A6)(A7 is ignored).

All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising
edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO
is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.

Figure 5-1. Serial Port Operation for Write Access

SCLK

CSB

A
6

(adrs

msb)

SDI

SDO

(lsb)

(msb)

(lsb)

WRITE ACCESS ENABLED

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0

SCLK

SDI

SDO

CSB

(lsb)

(msb)

(lsb)

(msb)

Read
Access
Enabled

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Figure 5-3. Serial Port Operation for Read Access with CLKE = 1

SCLK

SDI

SDO

CSB

(lsb)

(msb)

(lsb)

(msb)

5.1.2 Parallel Port Operation

When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or
nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can
operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following table lists all the
pins and their functions in the parallel port mode. See the timing diagrams in Section

for more details.

Table 5-1. Parallel Port Mode Selection and Pin Functions

MODESEL, MOTEL,

MUX

PARALLEL HOST

INTERFACE

ADDRESS, DATA,

AND CONTROL

100

Nonmultiplexed Motorola CSB, ACKB, DSB, RWB, ASB, A [5:0], D [7:0], INTB

110

Nonmultiplexed Intel

CSB, RDYB, WRB, RDB, ALE, A [5:0], D [7:0], INTB

101

Multiplexed Motorola

CSB, ACKB, DSB, RWB, ASB, AD [7:0], INTB

111

Multiplexed Intel

CSB, RDYB, WRB, RDB, ALE, AD [7:0], INTB

5.1.3 Interrupt

Handling

There are 4 sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:
· When status changes on an interruptible event, INTB pin will go low if the event is enabled through the

corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10 K

W resister for

wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be High when
not active by setting register

GISC.INTM

· When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source

of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The
Interrupt Status register can also be configured as clear on write as per register

GISC.CWE

. When set to clear

on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a `1' to
it's bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a
register without clearing them on all bits.

· Subsequently the host processor can read the corresponding Status Register to check the real-time status of

the event.

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Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters

TRANSMITTER FUNCTION

TELECOMMUNICATIONS COMPLIANCE

AMI Coding, B8ZS Substitution, DS1 Electrical

Interface

ANSI T1.102

T1 Telecom Pulse Mask compliance

ANSI T1.403

T1 Telecom Pulse Mask compliance

ANSI T1.102

Transmit Electrical Characteristics for E1 Transmission

and Return Loss Compliance

ITUT G.703.

Table 5-3. Registers Related to Control of DS26324 Transmitters

REGISTER NAME

ACRONYM

FUNCTION

Transmit All Ones Enable

TAOE

Transmit All Ones Enable

Driver Fault Monitor Status

DFMS

Driver Fault Status

Driver Fault Monitor Interrupt Enable

DFMIE

Driver Fault Status Interrupt Mask

Driver Fault Monitor Interrupt Status

DFMIS

Driver Fault Status Interrupt Mask

Automatic Transmit All Ones Select

ATAOS

Transmit all ones enabled automatically on LOS

Global Configuration Register

Global control of Jitter Attenuator, line coding and
short circuit protection.

Template Select Transmitter

TST

The Transmitter that the Template Select Register
Applies to.

Template Select

The TS2 to TS0 bits for Selection of the Templates for
Transmitter and TIMPOFF and TIMPRIM bits to
control transmit impedance match

Output Enable Configuration
Register

These register bits can be used to enable the
Transmitter outputs

Master Clock Selection

Selects the MCLK frequency used for Transmit and
Receive.

Transmit Single-Rail Mode Select
Register

SRMS

This register can be used to select between single-rail
and dual-rail mode.

Line Code Selection

LCS

The individual Transceiver Line Codes can be
selected to overwrite the global setting.

Transmit Power-down

TPDE

Individual Transmitters can be powered down.

Individual Jitter Attenuator Enable

IJAE

Enables the jitter attenuator

Individual Jitter Attenuator Position
Select

IJAPS

Selects whether jitter attenuator is in transmit or
receive path

Individual Jitter Attenuator FIFO
Depth Select

IJAFDS

Selects depth of jitter attenuator FIFO.

Individual Jitter Attenuator FIFO
Limit Trip

IJAFLT

Indicates jitter attenuator FIFO within 4 bits of its
useful limit

Individual Short Circuit Protection
Disable

ISCPD

This register allows the individual Transmitters to have
Short Circuit Protection Disable.

BERT Control Register

BTCR

This register allows mapping of the internal BERTs
into an individual transmit path.

Transmit clock invert

TCLKI

Inverts TCLK input.

BPV Error insertion

BEIR

Inserts a bipolar error in the transmit path when in
single-rail mode.

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Figure 5-6. T1 Transmit Pulse Templates

1 . 2

- 0 . 1

- 0 . 2

- 0 . 3

- 0 . 4

- 0 . 5

0 . 1

0 . 2

0 . 3

0 . 4

0 . 5

0 . 6

0 . 7

0 . 8

0 . 9

1 . 0

1 . 1

- 5 0 0

-3 0 0

- 1 0 0

3 0 0

5 0 0

7 0 0

- 4 0 0

- 2 0 0

2 0 0

4 0 0

6 0 0

1 0 0

T I M E ( n s )

NORM

I
Z
E
D
AM

P
L
I
T
UDE

T 1 .1 0 2 / 8 7 , T 1 .4 0 3 ,
C B 1 1 9 ( O c t . 7 9 ) , &
I.4 3 1 T e m p la te

- 0 .7 7
- 0 .3 9

- 0 .2 7
- 0 .2 7
- 0 .1 2

0 .0 0
0 .2 7
0 .3 5
0 .9 3

1 .1 6

- 5 0 0
- 2 5 5

- 1 7 5
- 1 7 5
- 7 5

0
1 7 5
2 2 5
6 0 0

7 5 0

0 .0 5
0 .0 5

0 .8 0
1 .1 5
1 .1 5

1 .0 5
1 .0 5
- 0 .0 7
0 .0 5

0 .0 5

- 0 .7 7
- 0 .2 3

- 0 .2 3
- 0 .1 5
0 .0 0

0 .1 5
0 .2 3
0 .2 3
0 .4 6

0 .6 6
0 .9 3
1 .1 6

- 5 0 0
- 1 5 0

- 1 5 0
- 1 0 0
0

1 0 0
1 5 0
1 5 0
3 0 0

4 3 0
6 0 0
7 5 0

- 0 .0 5
- 0 .0 5

0 .5 0
0 .9 5
0 .9 5

0 .9 0
0 .5 0
- 0 .4 5
- 0 .4 5

- 0 .2 0
- 0 .0 5
- 0 .0 5

U I

T im e

A m p .

M A X IM U M C U R V E

U I

T im e

A m p .

M IN IM U M C U R V E

- 0 .7 7

- 0 .3 9
- 0 .2 7
- 0 .2 7
- 0 .1 2

0 .0 0
0 .2 7
0 .3 4

0 .7 7
1 .1 6

- 5 0 0

- 2 5 5
- 1 7 5
- 1 7 5
- 7 5

0
1 7 5
2 2 5

6 0 0
7 5 0

0 .0 5

0 .0 5
0 .8 0
1 .2 0
1 .2 0

1 .0 5
1 .0 5
- 0 .0 5

0 .0 5
0 .0 5

- 0 .7 7

- 0 .2 3
- 0 .2 3
- 0 .1 5
0 .0 0

0 .1 5
0 .2 3
0 .2 3

0 .4 6
0 .6 1
0 .9 3

1 .1 6

- 5 0 0

- 1 5 0
- 1 5 0
- 1 0 0
0

1 0 0
1 5 0
1 5 0

3 0 0
4 3 0
6 0 0

7 5 0

- 0 .0 5

- 0 .0 5
0 .5 0
0 .9 5
0 .9 5

0 .9 0
0 .5 0
- 0 .4 5

- 0 .4 5
- 0 .2 6
- 0 .0 5

- 0 .0 5

U I

T im e

A m p .

M A X IM U M C U R V E

U I

T im e

A m p .

M IN IM U M C U R V E

D S X - 1 T e m p l a t e ( p e r A N S I T 1 . 1 0 2 - 1 9 9 3 )

D S 1 T e m p l a t e ( p e r A N S I T 1 .4 0 3 - 1 9 9 5 )

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Table 5-5. LIU Front-End Values

MODE COMPONENT

W COAX, 120W TWISTED PAIR, 100/110W TWISTED PAIR

Tx Capacitance

560pF typical. Adjust for board parasitics for optimal return
loss.

Tx Protection

International Rectifier 11DQ04 or 10BQ060
Motorola MBR0540T1

Rx Transformer RTR 1:1

TFr

Pulse TX1475

Tx Transformer 1:2

TFt

Halo TG83-S005NU

Rx Transformer RTR 1:2

TFr

Pulse T1124 (0°C to +70°C)

Tx Transformer 1:2

TFt

Pulse T1114 (-40°C to +85°C)

Tx Decoupling (TVDDn)

Common decoupling for all 16 channels = 68

mF.

Tx Decoupling (TVDDn)

Recommended decoupling per channel = 0.1

mF.

Rx Decoupling (AVDD)

Common decoupling for all 16 channels = 68

mF.

Rx Decoupling (AVDD)

Decouple all six pins separately with a 0.1

mF capacitor.

Rx Termination

Rx capacitance for all 16 channels = 0.1

mF.

Rx Termination RTR 1:1

Needed two resistors for all modes = 60.4

W ±1%.

Rx Termination RTR 1:2

Needed two resistors for all modes = 15.0

W ±1%.

Voltage Protection

TVS1

SGS-Thomson SMLVT 3V3 (3.3V Transient Suppressor)

Only use if necessary for application.

5.4.3 Dual

Rail

Dual-rail mode consists of TPOS, TNEG and TCLK pins on the System side. NRZ data is sampled on the falling
edge of TCLK as shown in

Figure 9-12

. The Zero substitution B8ZS or HDB3 is not allowed. The data that appears

on the TPOS pin will be output on TTIP and data on the TNEG will be output on TRING after pulse shaping. Single-
Rail Select Register (

SRMS)

is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS

and TNEG can be overwritten in the maintenance mode by setting the BERT Control Register (

BTCR

5.4.4 Single-Rail

Mode

Single-rail mode consists of TPOS, TNEG and TCLK pins on the system side. NRZ data is sampled on the falling
edge of TCLK as shown in

Figure 9-12

. The Zero substitution B8ZS or HDB3 is allowed. The TPOS data will be

encoded in AMI or B8ZS/HDB3 format on the TTIP and TRING pins after pulse shaping. Single-Rail Mode Select
(

SRMS)

is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS can be overwritten

in the maintenance mode by setting in BERT Control Register (

BTCR

5.4.5 Zero Suppression--B8ZS or HDB3

B8ZS coding is available when the device is in T1 mode (selected by TS2, TS1 and TS0 bits in the

B8ZS/HDB3 coding are enabled by default in single-rail mode. Setting the LCS bit in the

LCS

B8ZS/HDB3. Note that if the individual LIU is configured in E1 mode then HDB3 code substitution will be selected.
Bipolar violations can be inserted via the BEIR register or Transmit Maintenance Register settings only if B8ZS or
HDB3 coding is turned off.

B8ZS substitution is defined in ANSI T1.102 and HDB3 in ITUT G.703 standards.

5.4.6 Transmit

Power-Down

The Transmitter will be powered down if the relevant bits in the

TPDE

are set. The TTIP/TRING outputs will be

High-Z when TPDE is set.

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5.4.7 Transmit

All

Ones

When Transmit All Ones is invoked continuous Ones are transmitted using MCLK as the Timing Reference. Data
input at TPOS and TNEG is ignored.

Transmit All ones can be sent by setting bits in the

TAOE

ATAOS

are set and the corresponding receiver goes into LOS state in status register

LOSS.

5.4.8 Drive

Failure

Monitor

The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short or Open Circuit on the
Secondary side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected.
The

DFMS

status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver

failure.

5.5

Receiver

The 16 receivers of DS26324 are all identical. Either a 2:1 or 1:1 transformer can be used on the receive side
(selected by the RTR bit). The DS26324 is designed to be fully software-selectable for E1 and T1/J1 without the
need to change any external resistors for the receive-side. The receive impedance match settings are controlled by
the transmit template/impedance selection. See

Figure 5-8

and

Table 5-5

for external component values. Internal

impedance matching is enabled via the RIMPON bit.

The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data
recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery
system derives E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form a 16 times
over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding
performance to meet jitter tolerance specifications. Dependent on selection options B8ZS/HDB3/AMI decoding is
performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection
of single rail or dual rail is done by settings in the

SRMS

The receiver is capable of recovering signals up to 18dB worth of attenuation. The receiver contains functionality to
provide resistive gain up to 20dB for monitor mode.

5.5.1 Receiver Monitor Mode

The receive equalizer is equipped with a monitor mode function that allows for resistive gain up to 20dB along with
cable attenuation of 6dB to 24dB as shown in the

RSMM14

5.5.2 Peak Detector and Slicer

The Slicer determines the polarity and presence of the received data. The output of the Slicer is sent to the Clock
and Data Recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for
determination of the slicing threshold.

5.5.3 Receive Level Indicator

The DS26324 will report the signal strength at RTIP and RRING in increments described in

Table 6-18

via register

bits CnRL3-CnRL0 located in the

RSL14

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5.5.4 Clock and Data Recovery

The resultant E1 or T1 clock derived from the 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL
and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16
times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding
performance to meet jitter tolerance specifications.

5.5.5 Loss of Signal

The DS26324 uses both the Digital and Analog loss detection method in compliance with the latest T1.231 for
T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation.

LOS is detected if the receiver level falls bellow a threshold analog voltage for a certain duration. Alternatively this
can be termed as having received "zeros" for certain duration. The signal level and timing duration are defined in
accordance with the T1.231 or G.775 or ETSI 300 233 specifications.

The Loss Detection Thresholds are based on cable loss of 18dB for both T1 and E1 modes.

RCLK is replaced by MCLK when the receiver detects a Loss of signal. If the AISEL bit is set in the

the

IAISEL

bit is set, the RPOS/RNEG data is replaced by AIS. The loss state is exited when the receiver detects a

certain number of ones density at a higher signal level than the loss detection level. The loss detection signal level
and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between "LOS" and
"no LOS" states.

The following Table outlines the specifications governing the loss function:

Table 5-6. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications

STANDARD

CRITERIA

T1.231

ITU G.775

ETSI 300 233

Loss
Detection
Criteria

No pulses are detected for 175
±75 bits.

No pulses are detected for
duration of 10 to 255 bit
periods.

No pulses are detected for a
duration of 2048 bit periods or
1ms.

Loss Reset
Criteria

Loss is terminated if a duration
of 12.5% ones are detected
over duration of 175 ±75 bits.
Loss is not terminated if 8
consecutive zeros are found if
B8ZS encoding is used. If
B8ZS is not used loss is not
terminated if 100 consecutive
pulses are zero.

The incoming signal has
transitions for duration of 10 to
255 bit periods.

Loss reset criteria is not
defined.

5.5.5.1 4.5.3.1 ANSI T1.231 for T1 and J1 Modes

Loss is detected if the received signal level is less than 200mV for duration of 192 bit periods. LOS is reset if the all
of the following criteria are met:

· 24 or more ones are detected in 192-bit period with a detection threshold of 300mV measured at

RTIP and RRING.

· During the 192 bits less than 100 consecutive zeros are detected.

· 8 consecutive zeros are not detected if B8ZS is set.

5.5.5.2 4.5.3.1 ITU G.775 for E1 Modes

LOS is detected if the received signal level is less than 200mV for a continuous duration of 192 bit periods. LOS is
reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.

5.5.5.3 4.5.3.1 ETSI 200 233 for E1 Modes

LOS is detected if the received signal level is less than 200mV for a continuous duration of 2048 (1ms) bit periods.
LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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5.5.6 AIS

Table 5-7

outlines the DS26324 AIS related specifications.

Table 5-8

states the AIS functionality in the DS26324.

The registers related to the AIS detection are shown in

Table 5-9

Table 5-7. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications

STANDARD

CRITERIA

ITU G.775 for E1

ETSI 300233 for E1

ANSI T1.231 for T1

AIS
Detection
Criteria

2 or fewer zeros in each of 2
consecutive 512-bit streams
received.

Less than 3 zeros detected in
512-bit period.

Fewer than 9 zeros detected in
a 8192-bit period (a ones
density of 99.9% over a period
of 5.3ms) are received.

AIS
Clearance
Criteria

3 or more zeros in each of 2
consecutive 512-bit streams
received.

3 or more zeros in a 512 bits
received.

9 or more zeros detected in a
8192-bit period are received.

Table 5-8. AIS Detection and Reset Criteria

STANDARD

CRITERIA

ITU G.775 for E1

ETSI 300233 for E1

ANSI T1.231 for T1

AIS
Detection
Criteria

2 or less zeros in each of 2
consecutive 512-bit streams
received.

Less than 3 zeros detected in
512-bit period.

Fewer than 9 zeros contained
in 8192 bits.

AIS
Clearance
Criteria

3 or more zeros in each of 2
consecutive 512-bit streams
received.

3 or more zeros in 512 bits
received.

9 or more bits received in a
8192-bit stream.

Table 5-9. Registers Related to AIS Detection

REGISTER ACRONYM

POINTER

FUNCTIONALITY

LOS/AIS Criteria

LASCS

Section criteria for AIS (T1.231, G.775, ETSI 300233 for E1)

AIS Register

AIS

Set when AIS is detected.

AIS Enable Register

AISIE

If reset interrupt due to AIS is not generated.

AIS Interrupt

AISI

Latched if there is a change in AIS and the interrupt is
enabled.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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5.5.7 Bipolar Violation and Excessive Zero detector

DS26324 detects code violations, BPV and excessive zero errors. The reporting of the errors is done through the
pin RNEGn/CVn.

Excessive zeros are detected if 8 consecutive zeros are detected with B8ZS enabled and 4 consecutive zeros are
detected with HDB3 enabled. Excessive Zero detection is selectable when single-rail mode and HDB3/B8ZS
encoding/decoding is selected.

The bits in

EZDE

and

CVDEB

registers determine the combinations that are reported.

Table 5-10

outlines the

functionality:

Table 5-10. BPV, Code Violation, and Excessive Zero Error Reporting

CONDITIONS

CVn PIN REPORTS

EZDE is reset, CVDEB is reset

BPV + Code violation

EZDE is set, CVDEB is reset

BPV + Code violation + Excessive zero

EZDE is reset, CVDEB is set

BPV

EZDE is set, CVDEB is set

BPV + Excessive zero

5.6 Jitter

Attenuator

The DS26324 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS
bit in register

GC.

It can also be controlled on an individual LIU basis by settings in the

IJAFDS

The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay sensitive applications. The characteristics of the attenuation are shown in

Figure 5-9

. The jitter attenuator

can be placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE
bits in register

. These selections can be changed on an individual LIU basis by settings in the

IJAPS

and

IJAE

In order for the jitter attenuator to operate properly, a 2.048MHz or multiple thereof or 1.544MHz clock or multiple
thereof must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1
Applications. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board circuitry
adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create
a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
jittery clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either
120UI

P-P

(buffer depth is 128 bits) or 28UI

P-P

(buffer depth is 32 bits), then the DS26324 will divide the internal

nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer
from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bits
in the

IJAFLT

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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5.8.3 Remote

Loopback

The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS and TNEG are
ignored during a remote loopback. This loopback is conceptually shown in

Figure 5-12

Note: Remote loopback does not take precedence over Transmit Power-Down and requires TCLK to operate. The
transmitters will use the recovered RCLK in remote loopback. TCLK is still required because if it is removed the
transmitters will power-down (TCLK held low) or transmit all ones (TCLK held high).

Figure 5-12. Remote Loopback

Line
Driver

H D B 3 /
B 8 Z S

E n c o d e r

O p t i o n a l
J i t t e r

A t t e n u a t o r

T r a n s m i t
D i g i t a l

T r a n s m i t
A n a l o g

TCLK

TPOS

TNEG

H D B 3 /

B 8 Z S
D e c o d e r

O p t i o n a l
J i t t e r
A t t e n u a t o r

R e c e i v e
D i g i t a l

R e c e i v e
A n a l o g

RCLK

RPOS

RNEG

RTIP

RRING

TPOS

TNEG

5.9 BERT

There are two bit error rate testers available on the DS26324. One BERT can be mapped into LIUs 1-8 and the
other into LIUs 9-16 via the

BTCR

registers. The two BERTs operate independently of each other.

5.9.1 General

Description

The BERT is a software programmable test pattern generator and monitor capable of meeting most error
performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom
patterns with a generation polynomial of the form x

+ x

+ 1, where n and y can take on values from 1 to 32 and to

repetitive patterns of any length up to 32 bits.

The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.

The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern.

Features
· Programmable PRBS pattern The Pseudo Random Bit Sequence (PRBS) polynomial (x

+ x

+ 1) and seed

are programmable (length n = 1 to 32, tap y = 1 to n 1, and seed = 0 to 2

1).

· Programmable repetitive pattern The repetitive pattern length and pattern are programmable (the length n

= 1 to 32 and pattern = 0 to 2

1).

· 24-bit error count and 32-bit bit count registers

· Programmable bit error insertion Errors can be inserted individually, on a pin transition, or at a specific

rate. The rate 1/10

is programmable (n = 1 to 7).

· Pattern synchronization at a 10

-3

BER Pattern synchronization will be achieved even in the presence of a

random Bit Error Rate (BER) of 10

-3

TTIP

TRING

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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5.9.2 Configuration

and

Monitoring

Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send
and receive common patterns.

Table 5-11. Pseudorandom Pattern Generation

BPCR REGISTER

BERT.CR

PATTERN TYPE

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS QRSS

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

TPIC,

RPIC

-1

O.153 (511 type)

0x0408

0xFFFF 0xFFFF

-1

O.152 and O.153

(2047 type)

08 0A

0x080A

0xFFFF

-1

O.151 0D

0x0D0E

0xFFFF

-1

O.153 10

0x1013

0xFFFF

-1

O.151 QRSS

0x0253

0xFFFF 0xFFFF

-1

O.151 11

0x1116

0xFFFF

Table 5-12. Repetitive Pattern Generation

BPCR REGISTER

PATTERN TYPE

PTF[4:0]

(hex)

PLF[4:0]

(hex)

PTS QRSS

BERT.

PCR

BERT.

SPR2

BERT.

SPR1

All ones

0x0020

0xFFFF

All zeros

0x0020

0xFFFF

0xFFFE

Alternating ones and zeros

0x0021

0xFFFF

0xFFFE

Double alternating and zeros NA 03

0 0x0023

0xFFFF

0xFFFC

3 in 24

0x0037

0xFF20

0x0022

1 in 16

0 0x002F

0xFFFF

0x0001

1 in 8

0 0x0027

0xFFFF

0xFF01

1 in 4

0x0023

0xFFFF

0xFFF1

After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on

BCR

.TNPL and

BCR

.RNPL

Monitoring the BERT requires reading the

BSR

of Synchronization (OOS) bit.

The BEC bit will be one when the bit error counter is one or more.

The OOS will be

one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it
receives a minimum 6 bit errors within a 64 bit window.

The Receive BERT Bit Count Register (

RBCR

) and the

Receive BERT Bit Error Count Register (

RBECR

) will be updated upon the reception of a Performance Monitor

Update signal (e.g.

BCR.

LPMU).

This signal will update the registers with the values of the counters since the last

update and will reset the counters.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

36 of 112

5.9.3 Receive Pattern Detection

The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x

+ x

+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is

bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if
the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will
be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection
performs either PRBS synchronization or repetitive pattern synchronization.

5.9.3.1 Receive PRBS Synchronization

PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern re-synchronization can be disabled.

See

Figure 5-13

for the PRBS synchronization diagram.

Figure 5-13. PRBS Synchronization State Diagram

Sync

Load

Verify

1 bit error

32 bits loaded

its

ith

t e

6 o

f 6

4 b

its

ith

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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5.9.3.2 Receive Repetitive Pattern Synchronization

Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be
disabled.

Figure 5-14 shows the repetitive pattern synchronization state diagram.

Figure 5-14. Repetitive Pattern Synchronization State Diagram

Sync

Match

Verify

1 bit error

Pattern Matches

its

ith

t e

6 o

f 6

4 b

its

ith

5.9.3.3 Receive Pattern Monitoring

Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts
the incoming bits. An Out Of Synchronization (OOS) condition is declared when the synchronization state machine
is not in the "Sync" state. An OOS condition is terminated when the synchronization state machine is in the "Sync"
state.

Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they
do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit
count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

38 of 112

5.9.4 Transmit Pattern Generation

Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x

+ x

+ 1), the

feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is
enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all
zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits
1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value
before pattern generation starts. The seed/pattern value is programmable (0 2

1).

5.9.4.1 Transmit Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of
one out of every 10

bits. The value of n is programmable (1 to 7 or off). Single bit error insertion can be initiated

from the microprocessor interface, or by the manual error insertion input (TMEI). The method of single error
insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the
overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Table 6-1. Primary Register Set

ADDRESS FOR CH 18

ADDRESS FOR CH 916

NAME SYMBOL

HEX

FOR CH

18

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7A1

(HEX)

HEX FOR

CH 916

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7-A1

(HEX)

Identification

xx000000

x000000

Not used

Analog Loopback Configuration

ALBC

xx000001

x000001

xx100001

x100001

Remote Loopback Configuration

RLBC

xx000010

x000010

xx100010

x100010

Transmit All Ones Enable

TAOE

xx000011

x000011

xx100011

x100011

LOS Status

LOSS

xx000100

x000100

xx100100

x100100

Driver Fault Monitor Status

DFMS

xx000101

x000101

xx100101

x100101

LOS

Interrupt

Enable

LOSIE 06 xx000110 x000110 26 xx100110

x100110

Driver Fault Monitor Interrupt Enable

DFMIE

xx000111

x000111

xx100111

x100111

LOS Interrupt Status

LOSIS

xx001000

x001000

xx101000

x101000

Driver Fault Monitor Interrupt
Status

DFMIS 09 xx001001 x001001 29 xx101001

x101001 R

Software Reset

SWR

xx001010

x001010

xx101010

x101010

G.772

Monitor

Configuration

GMC 0B xx001011 x001011 2B xx101011

x101011

Digital Loopback Configuration

DLBC

xx001100

x001100

xx101100

x101100

LOS/AIS Criteria Selection

LASCS

xx001101

x001101

xx101101

x101101

Automatic Transmit All Ones
Select

ATAOS 0E xx001110 x001110 2E xx101110

x101110

Global

Configuration

GC 0F xx001111 x001111 2F xx101111

x101111

Template Select Transceiver
Register

TST 10 xx010000

x010000 30 xx110000

x110000

Template Select

xx010001

x010001

xx110001

x110001

Output Enable

xx010010

x010010

xx110010

x110010

Alarm Indication Signal

AIS

xx010011

x010011

xx110011

x110011

AIS Interrupt Enable

AISIE

xx010100

x010100

xx110100

x110100

AIS Interrupt Status

AISIS

xx010101

x010101

xx110101

x110101

Reserved --

161E

xx010110

xx011110

x010110

x011110

363E

xx110110

x111110

x110110

x111110

Address Pointer for Bank Selection

ADDP

xx011111

x011111

xx111111

x111111

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

42 of 112

Table 6-3. Individual LIU Register Set

ADDRESS FOR

CHANNELS 18

ADDRESS FOR

CHANNELS 916

NAME SYMBOL

HEX
FOR

CH 18

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7A1

(HEX)

HEX
FOR

CH 916

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7A1 (HEX)

Individual JA Enable

IJAE

xx000000

x000000

xx100000

x100000

Individual JA Position Select

IJAPS

xx000001

x000001

xx100001

x100001

Individual JA FIFO Depth
Select

IJAFDS 02 xx000010 x000010 22 xx100010 x100010

Individual JA FIFO Limit Trip

IJAFLT

xx000011

x000011

xx100011

x100011

Individual Short Circuit
Protection Disable

ISCPD 04 xx000100

x000100 24 xx100100 x100100

Individual AIS Select

IAISEL

xx000101

x000101

xx100101

x100101

Master Clock Select

xx000110

x000110

Not used

Receive Sensitivity Monitor
Mode 14

RSMM14 080B

xx001000

xx001011

x001000

x001011

282B

xx101000

xx101011

x101000

x101011

Receive Signal Level
Indicator 14

RSL14 0C0F

xx001100

xx001111

x001100

x001111

2C2F

xx101100

xx101111

x101100

x101111

Bit Error Rate Tester Control
Register

BTCR 10 xx010000

x010000 30 xx110000

x110000

Line Violation Detect Status

LVDS

xx010010

x010010

xx110010

x110010

Receive Clock Invert

RCLKI

xx010011

x010011

xx110011

x110011

Transmit Clock Invert

TCLKI

xx010100

x010100

xx110100

x110100

Clock Control Register

CCR

xx010101

x010101

Not used

RCLK Disable Upon LOS
Register

RDULR 16 xx010110 x010110 36 xx110110 x110110

Global Interrupt Status
Control

GISC

xx011110

x011110

Not used

Address Pointer for Bank
Selection

ADDP 1F xx011111

x011111 3F xx111111 x111111

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

43 of 112

Table 6-4. BERT Register Set

ADDRESS FOR

CHANNELS 18

ADDRESS FOR CHANNELS

916

NAME SYMBOL

HEX
FOR

CH 18

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7A1

(HEX)

HEX
FOR

CH 916

PARALLEL

INTERFACE

A7A0

(HEX)

SERIAL

INTERFACE

A7A1

(HEX)

BERT Control Register

BCR

xx000000

x000000

xx100000

x100000

Reserved --

xx000001

x000001

xx100001

x100001

BERT Pattern Configuration 1

BPCR1

xx000010

x000010

xx100010

x100010

BERT Pattern Configuration 2

BPCR2

xx000011

x000011

xx100011

x100011

BERT Seed/Pattern 1

BSPR1

xx000100

x000100

xx100100

x100100

BERT Seed/Pattern 2

BSPR2

xx000101

x000101

xx100101

x100101

BERT Seed/Pattern 3

BSPR3

xx000110

x000110

xx100110

x100110

BERT Seed/Pattern 4

BSPR4

xx000111

x000111

xx100111

x100111

Transmit Error Insertion Control

TEICR

xx001000

x001000

xx101000

x101000

Reserved --

090A

xx001001

x001010

-- 292A

xx101001

x101010

-- --

BERT Status Register

BSR

xx001100

x001100

xx101100

x101100

Reserved

xx001101

x001101

xx101101

x101101

BERT Status Register Latched

BSRL

xx010011

x010011

xx110011

x110011

BERT Status Register Interrupt
Enable

BSRIE 10 xx010000 x010000 30 xx110000 x110000

Reserved --

1113

xx010001

xx010011

x010001

x010011

3133

xx110001

xx110011

x110001

x110011

Receive Bit Error Count Register
1

RBECR1 14 xx010100 x010100 34

xx110100 x110100 R

Receive Bit Error Count Register
2

RBECR2 15 xx010101 x010101 35

xx110101 x110101 R

Receive Bit Error Count Register
3

RBECR3 16 xx010110 x010110 36

xx110110 x110110 R

Receive Bit Error Count Register
4

RBECR4 17 xx010111 x010111 37

xx110111 x110111 R

Receive Bit Count Register 1

RBCR1

xx011000

x011000

xx111000

x111000

Receive Bit Count Register 2

RBCR2

xx011001

x011001

xx111001

x111001

Receive Bit Count Register 3

RBCR3

xx011010

x011010

xx111010

x111010

Receive Bit Count Register 4

RBCR4

xx011011

x011011

xx111011

x111011

Reserved --

1C1E

xx011100

xx011110

x011100

x011110

3C3E

xx111100

xx111110

x111100

x111110

Address Pointer for Bank
Selection

ADDP 1F xx011111 x011111 3F xx111111 x111111

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

44 of 112

Table 6-5. Primary Register Set Bit Map

REGISTER

ADDRESS

FOR LIUS

1-8

R/W

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ID 00

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

ALBC

RW ALC8 ALBC7 ALBC6 ALBC5 ALBC4 ALBC3 ALBC2 ALBC1

RLBC

RW RLBC8 RLBC7 RLBC6 RLBC5 RLBC4 RLBC3 RLBC2 RLBC1

TAOE

RW TAOE8 TAOE7 TAOE6 TAOE5 TAOE4 TAOE3 TAOE2 TAOE1

LOSS

RW LOSS8 LOSS7 LOSS6 LOSS5 LOSS4 LOSS3 LOSS2 LOSS1

DFMS 05

DFMS8

DFMS7

DFMS6

DFMS5 DFMS4 DFMS3 DFMS2 DFMS1

LOSIE

RW LOSIE8 LOSIE7 LOSIE6 LOSIE5 LOSIE4 LOSIE3 LOSIE2 LOSIE1

DFMIE

RW DFMIE8 DFMIE7 DFMIE6 DFMIE5 DFMIE4 DFMIE3 DFMIE2 DFMIE1

LOSIS 08

LOSIS8 LOSIS7 LOSIS6 LOSIS5 LOSIS4 LOSIS3 LOSIS2 LOSIS1

DFMIS 09 R

DFMIS8 DFMIS7 DFMIS6 DFMIS5 DFMIS4 DFMIS3 DFMIS2 DFMIS1

SWR

W SWRL SWRL SWRL SWRL SWRL SWRL SWRL SWRL

GMC 0B

GMC4 GMC3 GMC2 GMC1

DLBC

RW DLBC8 DLBC7 DLBC6 DLBC5 DLBC4 DLBC3 DLBC2 DLBC1

LASCS

RW LASCS8 LASCS7 LASCS6 LASCS5 LASCS4 LASCS3 LASCS2 LASCS1

ATAOS

RW ATAOS8 ATAOS7 ATAOS6 ATAOS5 ATAOS4 ATAOS3 ATAOS2 ATAOS1

GC 0F

AISEL

SCPD

CODE

JADS

RTCTL

JAPS

JAE

TST 10

TST2 TST1 TST0

TS 11

RIMPON

TIMPOFF

TIMPRM TS2 TS1 TS0

12 RW

OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1

AIS 13

AIS8 AIS7 AIS6 AIS5 AIS4 AIS3 AIS2 AIS1

AISIE

RW AISIE8 AISIE7 AISIE6 AISIE5 AISIE4 AISIE3 AISIE2 AISIE1

AISI 15

AISI8 AISI7 AISI6 AISI5 AISI4 AISI3 AISI2 AISI1

Not Used

16-1E

ADDP

RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

REGISTER

ADDRESS

FOR LIUs

916

R/W

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Not Used

ALBC

RW ALC16 ALBC15 ALBC14 ALBC13 ALBC12 ALBC11 ALBC10 ALBC9

RLBC

RW RLBC16 RLBC15 RLBC14 RLBC13 RLBC12 RLBC11 RLBC10 RLBC9

TAOE

RW TAOE16 TAOE15 TAOE14 TAOE13 TAOE12 TAOE11 TAOE10 TAOE9

LOSS

RW LOSS16 LOSS15 LOSS14 LOSS13 LOSS12 LOSS11 LOSS10 LOSS9

DFMS

RW DFMS16 DFMS15 DFMS14 DFMS13 DFMS12 DFMS11 DFMS10 DFMS9

LOSIE

RW LOSIE16 LOSIE15 LOSIE14 LOSIE13 LOSIE12 LOSIE11 LOSIE10 LOSIE9

DFMIE

RW DFMIE16 DFMIE15 DFMIE14 DFMIE13 DFMIE12 DFMIE11 DFMIE10 DFMIE9

LOSIS 28

LOSIS16 LOSIS15 LOSIS14 LOSIS13 LOSIS12 LOSIS11 LOSIS10 LOSIS9

DFMIS 29 R

DFMIS16 DFMIS15 DFMIS14 DFMIS13 DFMIS12 DFMIS11 DFMIS10 DFMIS9

SWR

W SWRU SWRU SWRU SWRU SWRU SWRU SWRU SWRU

GMC 2B

GMC4 GMC3 GMC2 GMC1

DLBC

RW DLBC16 DLBC15 DLBC14 DLBC13 DLBC12 DLBC11 DLBC10 DLBC9

LASCS

RW LASCS16 LASCS15 LASCS14 LASCS13 LASCS12 LASCS11 LASCS10 LASCS9

ATAOS 2E

ATAOS16 ATAOS15 ATAOS14 ATAOS13 ATAOS12 ATAOS11 ATAOS10 ATAOS9

GC 2F

AISEL

SCPD

CODE

JADS

JAPS

JAE

TST 30

TST2 TST1 TST0

TS 31

RIMPON

TIMPOFF

TIMPRM

TS2 TS1 TS0

32 RW OE16 OE15 OE14 OE13 OE12 OE11 OE10 OE9

AIS 33

AIS16 AIS15 AIS14 AIS13 AIS12 AIS11 AIS10 AIS9

AISIE

RW AISIE16 AISIE15 AISIE14 AISIE13 AISIE12 AISIE11 AISIE10 AISIE9

AISI 35

AISI16 AISI15 AISI14 AISI13 AISI12 AISI11 AISI10 AISI9

Not Used

36-3E

ADDP

RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

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Table 6-7. Individual LIU Register Set Bit Map

REGISTER

ADDRESS

FOR LIUs

18

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IJAE

00 RW IJAE8 IJAE7 IJAE6 IJAE5 IJAE4 IJAE3 IJAE2 IJAE1

IJAPS

RW IJAPS8 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAPS3 IJAPS2 IJAPS1

IJAFDS

RW IJAFDS8 IJAFDS7 IJAFDS6 IJAFDS5 IJAFDS4 IJAFDS3 IJAFDS2 IJAFDS1

IJAFLT 03

IJAFLT8 IJAFLT7 IJAFLT6 IJAFLT5 IJAFLT4 IJAFLT3 IJAFLT2 IJAFLT1

ISCPD

RW ISCPD8 ISCPD7 ISCPD6 ISCPD5 ISCPD4 ISCPD3 ISCPD2 ISCPD1

IAISEL

RW IAISEL8 IAISEL7 IAISEL6 IAISEL5 IAISEL4 IAISEL3 IAISEL2 IAISEL1

MC 06

PCLKI1

PCLKI0

TECLKE

CLKAE

MPS1

MPS0

FREQS

PLLE

RSMM1

RW RTR2 C2RSM2 C2RSM1 C2RSM0 RTR1 C1RSM2 C1RSM1 C1RSM0

RSMM2

RW RTR4 C4RSM2 C4RSM1 C4RSM0 RTR3 C3RSM2 C3RSM1 C3RSM0

RSMM3

RW RTR6 C6RSM2 C6RSM1 C6RSM0 RTR5 C5RSM2 C5RSM1 C5RSM0

RSMM4

RW RTR8 C8RSM2 C8RSM1 C8RSM0 RTR7 C7RSM2 C7RSM1 C7RSM0

RSL1 0C

C2RSL3 C2RSL2 C2RSL1 C2RSL0 C1RSL3 C1RSL2 C1RSL1 C1RSL0

RSL2 0D

C4RSL3 C4RSL2 C4RSL1 C4RSL0 C3RSL3 C3RSL2 C3RSL1 C3RSL0

RSL3 0E

C6RSL3 C6RSL2 C6RSL1 C6RSL0 C5RSL3 C5RSL2 C5RSL1 C5RSL0

RSL4 0F

C8RSL3 C8RSL2 C8RSL1 C8RSL0 C7RSL3 C7RSL2 C7RSL1 C7RSL0

BTCR

10 RW BTS2 BTS1 BTS0 --

BERTE

BEIR

11 RW BEIR8 BEIR7 BEIR6 BEIR5 BEIR4 BEIR3 BEIR2 BEIR1

LVDS 12

LVDS8 LVDS7 LVDS6 LVDS5 LVDS4 LVDS3 LVDS2 LVDS1

RCLKI

RW RCLKI8 RCLKI7 RCLKI6 RCLKI5 RCLKI4 RCLKI3 RCLKI2 RCLKI1

TCLKI

RW TCLKI8 TCLKI7 TCLKI6 TCLKI5 TCLKI4 TCLKI3 TCLKI2 TCLKI1

CCR

RW PCLKS2

PCLKS1

PCLKS0

TECLKS CLKA3 CLKA2 CLKA1 CLKA0

RDULR

RW RDULR8 RDULR7 RDULR6 RDULR5 RDULR4 RDULR3 RDULR2 RDULR1

GISC 1E

INTM CWE

ADDP

RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

REGISTER

ADDRESS

FOR

LIUs 916

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IJAE

RW IJAE16 IJAE15 IJAE14 IJAE13 IJAE12 IJAE11 IJAE10 IJAE9

IJAPS

RW IJAPS16 IJAPS15 IJAPS14 IJAPS13 IJAPS12 IJAPS11 IJAPS10 IJAPS9

IJAFDS

RW IJAFDS16 IJAFDS15 IJAFDS14 IJAFDS13 IJAFDS12 IJAFDS11 IJAFDS10 IJAFDS9

IJAFLT 23 R

IJAFLT16 IJAFLT15 IJAFLT14 IJAFLT13 IJAFLT12 IJAFLT11 IJAFLT10 IJAFLT9

ISCPD

RW ISCPD16 ISCPD15 ISCPD14 ISCPD13 ISCPD12 ISCPD11 ISCPD10 ISCPD9

IAISEL

RW IAISEL16 IAISEL15 IAISEL14 IAISEL13 IAISEL12 IAISEL11 IAISEL10 IAISEL9

Not Used

RSMM1 28

RTR10

C10RSM2

C10RSM1

C10RSM0

RTR9

C9RSM2

C9RSM1

C9RSM0

RSMM2 29

RTR12

C12RSM2

C12RSM1

C12RSM0

RTR11

C11RSM2

C11RSM1

C11RSM0

RSMM3 2A

RTR14

C14RSM2

C14RSM1

C14RSM0

RTR13

C13RSM2

C13RSM1

C13RSM0

RSMM4 2B

RTR8

C16RSM2

C16RSM1

C16RSM0

RTR16

C16RSM2

C16RSM1

C16RSM0

RSL1 2C

C10RSL3 C10RSL2 C10RSL1 C10RSL0 C9RSL3 C9RSL2 C9RSL1 C9RSL0

RSL2 2D

C12RSL3 C12RSL2 C12RSL1 C12RSL0 C11RSL3 C11RSL2 C11RSL1 C11RSL0

RSL3 2E

C14RSL3 C14RSL2 C14RSL1 C14RSL0 C13RSL3 C13RSL2 C13RSL1 C13RSL0

RSL4 2F

C16RSL3 C16RSL2 C16RSL1 C16RSL0 C15RSL3 C15RSL2 C15RSL1 C15RSL0

BTCR 30

BTS2

BTS1

BTS0

BERTE

BEIR

RW BEIR16 BEIR15 BEIR14 BEIR13 BEIR12 BEIR11 BEIR10 BEIR9

LVDS 32

LVDS16 LVDS15 LVDS14 LVDS13 LVDS12 LVDS11 LVDS10 LVDS9

RCLKI

RW RCLKI16 RCLKI15 RCLKI14 RCLKI13 RCLKI12 RCLKI11 RCLKI10 RCLKI9

TCLKI

RW TCLKI16 TCLKI15 TCLKI14 TCLKI13 TCLKI12 TCLKI11 TCLKI10 TCLKI9

Not Used

RDULR

RW RDULR16 RDULR15 RDULR14 RDULR13 RDULR12 RDULR11 RDULR10 RDULR9

GISC 3E

INTM CWE

ADDP

RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Table 6-8. BERT Register Bit Map

REG

ADDRESS

FOR

LIUs 18

ADDRESS

FOR

LIUs 916

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BCR

20 RW

PMUM

LPMU

RNPL

RPIC

MPR

APRD

TNPL

TPIC

Not Used

BPCR1 02

22 RW -- QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0

BPCR2 03

PTF4 PTF3 PTF2 PTF1 PTF0

BSPR1 04

24 RW BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0

BSPR2 05

BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8

BSPR3

RW BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16

BSPR4 07

-- BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24

TEICR 08

28 RW

TEIR2 TEIR1 TEIR0 BEI TSEI MEIMS

Not Used

090B

292B -- --

BSR 0C 2C

R/W

PMS --

BEC OOS

Not Used

BSRL 0E 2E

RL/W

PMSL BEL BECL OOSL

Not Used

2F -- --

BSRIE 10

30 RW

PMSIE BEIE BECIE OOSIE

Not Used

1113

3133 -- --

RBECR1 14

34 R BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0

RBECR2 15

35 R

BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8

RBECR3 16

36 R

BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16

Not Used

RBCR1 18

38 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

RBCR2 19

39 R

BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8

RBCR3 1A

3A R

BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16

RBCR4 1B

3B R

BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24

Not Used

1C1E

3C3E

ADDP

RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

Note: Underlined bits are read only.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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6.1 Register

Description

This sections details the register description(s) of each bit. Whenever the variable "n" in italics is used in any of the
register descriptions, it represents 116. Note that in the register descriptions, there are duplicate registers for LIUs
18 and LIUs 916. There are registers in LIUs 18 that do not have a duplicate in the register set for LIUs 916.
For these registers, only one address is listed. All other registers list two addresses, one for LIUs 18 and one for
LIUs 916.

6.1.1 Primary Register Bank

The ADDP register must be set to 00h to access this bank.

ID Register

00h

Bit

# 7 6 5 4 3 2 1 0

Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Bits 7: Device CODE ID Bit 7 (ID7). This bit is `zero' for short-haul operation.

Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device
contains.

Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID2 to ID0). These bits tell the user the revision of the part. Contact the
factory for details.

ALBC

Analog Loopback Control

01h

Bit

# 7 6 5 4 3 2 1 0

Name ALBC8 ALBC7 ALBC6 ALBC5 ALBC4 ALBC3 ALBC2 ALBC1
Default

0 0 0 0 0 0 0 0

21h

Bit

# 7 6 5 4 3 2 1 0

Name ALBC16 ALBC15 ALBC14 ALBC13 ALBC12 ALBC11 ALBC10 ALBC9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in Analog
Loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. LOS
Detector is still in operation. The jitter attenuator is in use if enabled for the Transmitter or Receiver.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RLBC

Remote Loopback Control

02h

Bit

# 7 6 5 4 3 2 1 0

Name RLBC8 RLBC7 RLBC6 RLBC5 RLBC4 RLBC3 RLBC2 RLBC1
Default

0 0 0 0 0 0 0 0

22h

Bit

# 7 6 5 4 3 2 1 0

Name RLBC16 RLBC15 RLBC14 RLBC13 RLBC12 RLBC11 RLBC10 RLBC9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, Remote Loopback is
enabled on LIUn. The Analog Received Signal goes through the Receive Digital and is looped back to the
Transmitter. The data at TPOS and TNEG is ignored. The jitter attenuator is in use if enabled.

TAOE

Transmit All Ones Enable

03h

Bit

# 7 6 5 4 3 2 1 0

Name TAOE8 TAOE7 TAOE6 TAOE5 TAOE4 TAOE3 TAOE2 TAOE1
Default

0 0 0 0 0 0 0 0

23h

Bit

# 7 6 5 4 3 2 1 0

Name TAOE16 TAOE15 TAOE14 TAOE13 TAOE12 TAOE11 TAOE10 TAOE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Transmit All Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of All ones
on TTIP and TRING are sent on Channel n. MCLK is used as a reference clock for Transmit All Ones Signal. The
data arriving at TPOS and TNEG is ignored.

LOSS

Loss of Signal Status

04h

Bit

# 7 6 5 4 3 2 1 0

Name LOS8 LOS7 LOS6 LOS5 LOS4 LOS3 LOS2 LOS1
Default

0 0 0 0 0 0 0 0

24h

Bit

# 7 6 5 4 3 2 1 0

Name LOS16 LOS15 LOS14 LOS13 LOS12 LOS11 LOS10 LOS9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Loss of Signal Status Channel n (LOSn). When this bit is set, a LOS condition has been detected on
LIUn. The criteria and conditions of LOS are described in Loss of Signal.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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DFMS

Driver Fault Monitor Status

05h

Bit

# 7 6 5 4 3 2 1 0

Name DFMS8 DFMS7 DFMS6 DFMS5 DFMS4 DFMS3 DFMS2 DFMS1
Default

0 0 0 0 0 0 0 0

25h

Bit

# 7 6 5 4 3 2 1 0

Name DFMS16 DFMS15 DFMS14 DFMS13 DFMS12 DFMS11 DFMS10 DFMS9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short
or open circuit at the Transmit Driver for LIUn.

LOSIE

Loss of Signal Interrupt Enable

06h

Bit

# 7 6 5 4 3 2 1 0

Name LOSIE8 LOSIE7 LOSIE6 LOSIE5 LOSIE4 LOSIE3 LOSIE2 LOSIE1
Default

0 0 0 0 0 0 0 0

26h

Bit

# 7 6 5 4 3 2 1 0

Name LOSIE16 LOSIE15 LOSIE14 LOSIE13 LOSIE12 LOSIE11 LOSIE10 LOSIE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Loss of Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in LOS Status for
LIUn can generate an Interrupt.

DFMIE

Driver Fault Monitor Interrupt Enable

07h

Bit

# 7 6 5 4 3 2 1 0

Name DFMIE8 DFMIE7 DFMIE6 DFMIE5 DFMIE4 DFMIE3 DFMIE2 DFMIE1
Default

0 0 0 0 0 0 0 0

27h

Bit

# 7 6 5 4 3 2 1 0

Name DFMIE16 DFMIE15 DFMIE14 DFMIE13 DFMIE12 DFMIE11 DFMIE10 DFMIE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM
Status can generate an Interrupt in Monitor n.

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LOSIS

Loss of Signal Interrupt Status

08h

Bit

# 7 6 5 4 3 2 1 0

Name LOSIS8 LOSIS7 LOSIS6 LOSIS5 LOSIS4 LOSIS3 LOSIS2 LOSIS1
Default

0 0 0 0 0 0 0 0

28h

Bit

# 7 6 5 4 3 2 1 0

Name LOSIS16 LOSIS15 LOSIS14 LOSIS13 LOSIS12 LOSIS11 LOSIS10 LOSIS9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Loss of Signal Interrupt Status Channel n (LOSISn). When this bit is set, it indicates a LOS status
has transition from a "0 to 1" or "1 to 0" and was detected for LIUn. The bit for LIUn is enabled by register
LOSIE(06h). This bit when latched is cleared on a read operation.

DFMIS

Driver Fault Monitor Interrupt Status

09h

Bit

# 7 6 5 4 3 2 1 0

Name DFMIS8 DFMIS7 DFMIS6 DFMIS5 DFMIS4 DFMIS3 DFMIS2 DFMIS1
Default

0 0 0 0 0 0 0 0

29h

Bit

# 7 6 5 4 3 2 1 0

Name DFMIS16 DFMIS15 DFMIS14 DFMIS13 DFMIS12 DFMIS11 DFMIS10 DFMIS9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has
transitioned from "0 to 1" or "1 to 0" and was detected for LIUn. The bit for LIUn is enabled by register DFMIE(07h).
This bit when latched is cleared on a read operation.

SWR

Software Reset

0Ah

Bit

# 7 6 5 4 3 2 1 0

Name SWRL SWRL SWRL SWRL SWRL SWRL SWRL SWRL
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be
generated that resets the lower set of registers (LIUs 1-8). All the registers will be restored to their default values. A
read operation will always read back all zeros.

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2Ah

Bit

# 7 6 5 4 3 2 1 0

Name SWRU SWRU SWRU SWRU SWRU SWRU SWRU SWRU
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be
generated that resets the upper set of registers (LIUs 9-16). All the registers will be restored to their default values.
A read operation will always read back all zeros.

GMC

G.772 Monitoring Control

0Bh

Bit

# 7 6 5 4 3 2 1 0

Name

-- -- -- --

GMC3

GMC2

GMC1

GMC0

Default

0 0 0 0 0 0 0 0

Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive
monitoring. Receiver 1 is used to monitor channels 2 to 8 of one receiver from RTIP2-8/RRING2-8 or of one
transmitter from TTIP2-8/TRING2-8. See

Table 6-9

2Bh

Bit

# 7 6 5 4 3 2 1 0

Name

-- -- -- --

GMC3

GMC2

GMC1

GMC0

Default

0 0 0 0 0 0 0 0

Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive
monitoring. Receiver 9 is used to monitor channels 10 to 16 of one receiver from RTIP10-16/RRING10-16 or of one
transmitter from TTIP10-16/TRING10-16. See

Table 6-10

Table 6-9. G.772 Monitoring Control (LIU 1)

GMC3 GMC2 GMC1 GMC0

SELECTION

0 0 0 0

Monitoring

0 0 0 1

Receiver

0 0 1 0

Receiver

0 0 1 1

Receiver

0 1 0 0

Receiver

0 1 0 1

Receiver

0 1 1 0

Receiver

0 1 1 1

Receiver

1 0 0 0

Monitoring

1 0 0 1

Transmitter

1 0 1 0

Transmitter

1 0 1 1

Transmitter

1 1 0 0

Transmitter

1 1 0 1

Transmitter

1 1 1 0

Transmitter

1 1 1 1

Transmitter

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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LASCS

LOS/AIS Criteria Selection

0Dh

Bit

# 7 6 5 4 3 2 1 0

Name LASCS8 LASCS7 LASCS6

LASCS5 LASCS4 LASCS3 LASCS2 LASCS1

Default

0 0 0 0 0 0 0 0

2Dh

Bit

# 7 6 5 4 3 2 1 0

Name

LASCS16 LASCS15 LASCS14 LASCS13 LASCS12 LASCS11 LASCS10 LASCS9

Default

0 0 0 0 0 0 0 0

Bit 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). This bit is used for LOS/AIS Selection Criteria for
LIUn. In E1 mode if set it uses ETSI (300233) mode selections. If reset it uses G.775 criteria. In T1/J1 mode
T1.231 criteria is selected.

ATAOS

Automatic Transmit All Ones Select

0Eh

Bit

# 7 6 5 4 3 2 1 0

Name ATAOS8 ATAOS7 ATAOS6

ATAOS5 ATAOS4 ATAOS3 ATAOS2 ATAOS1

Default

0 0 0 0 0 0 0 0

2Eh

Bit

# 7 6 5 4 3 2 1 0

Name

ATAOS16 ATAOS15 ATAOS14 ATAOS13 ATAOS12 ATAOS11 ATAOS10 ATAOS9

Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Automatic Transmit All Ones Select Channel n (ATAOSn). When this bit is set All Ones Signal is
sent if a Loss of Signal is detected for LIUn. "All Ones Signal" uses MCLK as the reference clock.

Global Configuration

0Fh

Bit

# 7 6 5 4 3 2 1 0

Name

AISEL SCPD CODE JADS RTCTL JAPS JAE

Default

0 0 0 0 0 0 0 0

RTCTL controls all 16 LIUs. All other bits are for LIUs 1-8 only.

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting
LOS for each channel. The individual LIU Register

IAISEL

settings will be ignored when this bit is set.

When reset,

the

IAISEL

Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the
transmitters. The individual LIU Register

ISCPD

settings will be ignored when this bit is set.

When reset, the

ISCPD

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Bit 4: Code. If this bit is set AMI encoder/decoder is selected.

The

LCS

bit is set.

If reset, the

LCS

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
settings in the

IJAFDS

If reset the

IJAFDS

Bit 2: Receive Termination Control (RTCTL).

If this bit is set the OE pin has been granted control over all the

internal termination of all the LIU Receivers.

Otherwise, see the RIMPON bit.

Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA will be in the Receive path
and when default or set low in the Transmit path. These settings can be changed for an individual LIU by settings in
Register

IJAPS

. Note that when bit JAE is set, the settings in Register

IJAPS

will be ignored.

Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the

IJAE

be ignored if this register is set. If reset, the IJAE register will have control.

2Fh

Bit

# 7 6 5 4 3 2 1 0

Name - AISEL

SCPD

CODE

JADS - JAPS

JAE

Default

0 0 0 0 0 0 0 0

Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting
LOS for each channel. The individual LIU Register

IAISEL

settings will be ignored when this bit is set. When reset,

the

IAISEL

Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the
transmitters. The individual LIU Register

ISCPD

settings will be ignored when this bit is set. When reset, the

ISCPD

Bit 4: Code.

If this bit is set AMI encoder/decoder is selected. The

LCS

bit is set. If reset, the

LCS

Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
settings in the

IJAFDS

IJAPS

. Note that when bit JAE is set, the settings in Register

IJAPS

will be ignored.

Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the

IJAE

be ignored if this register is set. If reset, the IJAE register will have control.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Template Select Register

11h

31h

Bit

# 7 6 5 4 3 2 1 0

Name

RIMPON

TIMPOFF

-- --

TIMPRM

TS2 TS1 TS0

Default

0 0 0 0 0 0 0 0

Bit 7: Receive Impedance Match On (RIMPON). If this bit is set Receive Impedance matching is turned ON.
Otherwise the receiver is in High Z. Note that the OE pin can have control instead of this bit when the GC.RTCTL
bit is set.

Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set all the internal Transmit Terminating
Impedance is turned Off.

Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal Transmit Termination
impedance and Receive Impedance Match for E1 mode and T1/J1 mode.

W for E1 mode or 100W for T1 mode.

120

W for E1 mode or 110W for J1 mode.

Bit 2 to 0: Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the Template,
and the settings for various cable lengths. The impedance Termination for the Transmitter and Impedance Match
for the Receiver are specified by bit TIMPRM. See

Table 6-14

for bit selection of TS[2:0].

Table 6-14. Template Selection

TEMPLATE SELECTION

TS[2:0]

LINE LENGTH

(ft)

CABLE LOSS

(dB)

IMPEDANCE

(

011 0133

ABAM

0.6

100/110

100 133266

ABAM

1.2

100/110

101 266399

ABAM

1.8

100/110

110 399533

ABAM

2.4

100/110

111 533655

ABAM

3.0

100/110

000

G.703 Coaxial & Twisted pair cable

75/120

001 and 010

Reserved

Output Enable

12h

Bit

# 7 6 5 4 3 2 1 0

Name OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1
Default

0 0 0 0 0 0 0 0

32h

Bit

# 7 6 5 4 3 2 1 0

Name OE16 OE15 OE14 OE13 OE12 OE11 OE10 OE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Output Enable Channel n (OEn). When this bit is in default the Transmitter output for LIUn is in High-Z.
When this bit is set the Transmitter output for LIUn is enabled. Note that the OE pin will override this setting when
low.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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AISI

AIS Interrupt

15h

Bit

# 7 6 5 4 3 2 1 0

Name AISI8 AISI7 AISI6 AISI5 AISI4 AISI3 AISI2 AISI1
Default

0 0 0 0 0 0 0 0

35h

Bit

# 7 6 5 4 3 2 1 0

Name AISI16 AISI15 AISI14 AISI13 AISI12 AISI11 AISI10 AISI9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: AIS Interrupt Channel n (AISIn). This bit is set when AIS Transitions from a "0 to 1" or "1 to 0" and
Interrupts are enabled by

AISIE

(14) register for LIUn. This bit if set, is cleared on a read operation or when the

interrupt enable register is disabled.

ADDP

Address Pointer

1Fh

3Fh

Bit

# 7 6 5 4 3 2 1 0

Name ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the Primary Registers, the
Secondary Registers, Individual Registers, and BERT Registers. See

Table 6-15

for bank selection. The register

space contains control for channels 1 to 8 from address 00 hex to 1F hex and a duplicate set of registers for control
of channels 9 to 16 from address 20 hex to 3F hex. The ADDP at address 1F hex select the banks for the set of
registers for LIUs 1-8. The ADDP register at address 3F select the banks for the set of registers for LIUs 9-16.

Table 6-15. Address Pointer Bank Selection

ADDP7ADDP0

(HEX)

BANK NAME

00 Primary

Bank

AA Secondary

Bank

Individual LIU Bank

02 BERT

Bank

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RPDE

Receive Power-Down Enable

03h

Bit

# 7 6 5 4 3 2 1 0

Name RPDE8 RPDE7 RPDE6 RPDE5 RPDE4 RPDE3 RPDE2 RPDE1
Default

0 0 0 0 0 0 0 0

23h

Bit

# 7 6 5 4 3 2 1 0

Name RPDE16 RPDE15 RPDE14 RPDE13 RPDE12 RPDE11 RPDE10 RPDE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Receive Power-Down Enable Channel n (RPDEn).

When this bit is set the Receiver for LIUn is

powered down.

TPDE

Transmit Power-Down Enable

04h

Bit

# 7 6 5 4 3 2 1 0

Name TPDE8 TPDE7 TPDE6 TPDE5 TPDE4 TPDE3 TPDE2 TPDE1
Default

0 0 0 0 0 0 0 0

24h

Bit

# 7 6 5 4 3 2 1 0

Name TPDE16 TPDE15 TPDE14 TPDE13 TPDE12 TPDE11 TPDE10 TPDE9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Transmit Power-Down Enable Channel n(TPDEn).

When this bit is set the Transmitter for LIUn is

powered down.

EZDE

Excessive Zero Detect Enable

05h

Bit

# 7 6 5 4 3 2 1 0

Name EXZDE8 EXZDE7 EXZDE6 EXZDE5 EXZDE4 EXZDE3 EXZDE2 EXZDE1
Default

0 0 0 0 0 0 0 0

25h

Bit

# 7 6 5 4 3 2 1 0

Name

EXZDE16 EXZDE15 EXZDE14 EXZDE13 EXZDE12 EXZDE11 EXZDE10 EXZDE9

Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset Excessive Zero detection is
disabled for LIUn. When this bit is set Excessive Zero Detect Enable is enabled. Excessive Zero Detection is only
relevant in single-rail mode with HDB3 or B8ZS encoding.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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IJAPS

Individual Jitter Attenuator Position Select

01h

Bit #

7 6 5 4 3 2 1 0

Name IJAPS8 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAPS3 IJAPS2 IJAPS1
Default

0 0 0 0 0 0 0 0

21h

Bit #

7 6 5 4 3 2 1 0

Name IJAPS16 IJAPS15 IJAPS14 IJAPS13 IJAPS12 IJAPS11 IJAPS10 IJAPS9
Default

0 0 0 0 0 0 0 0

Bit 7-0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high the JA is in
the Receive path n, and when this bit is default or set low then the JA is in the Transmit path n. Note that if the

.JAE register bit is set, this register will be ignored.

IJAFDS

Individual Jitter Attenuator Fifo Depth Select

02h

Bit #

7 6 5 4 3 2 1 0

Name IJAFDS8 IJAFDS7 IJAFDS6 IJAFDS5 IJAFDS4 IJAFDS3 IJAFDS2 IJAFDS1
Default

0 0 0 0 0 0 0 0

22h

Bit #

7 6 5 4 3 2 1 0

Name

IJAFDS16 IJAFDS15 IJAFDS14 IJAFDS13 IJAFDS12 IJAFDS11 IJAFDS10 IJAFDS9

Default

0 0 0 0 0 0 0 0

Bit 7-0: Individual Jitter Attenuator Fifo Depth Select n (IJAFDSn). When this bit is set for LIUn the JA Fifo
depth will be 128 bits. When reset the JA FIFO depth will be 32 bits. Note that if the

.IJAFDS register bit is set

this register will be ignored.

IJAFLT

Individual Jitter Attenuator FIFO Limit Trip

03h

Bit

# 7 6 5 4 3 2 1 0

Name IJAFLT8 IJAFLT7 IJAFLT6 IJAFLT5 IJAFLT4 IJAFLT3 IJAFLT2 IJAFLT1
Default

0 0 0 0 0 0 0 0

23h

Bit

# 7 6 5 4 3 2 1 0

Name IJAFLT16 IJAFLT15 IJAFLT14 IJAFLT13 IJAFLT12 IJAFLT11 IJAFLT10 IJAFLT9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO reaches
to within 4 bits of its useful limit for Transmitter n. This bit will be cleared when read.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Master Clock Select

06h

Bit

# 7 6 5 4 3 2 1 0

Name PCLKI1

PCLKI0

TECLKE

CLKAE MPS1 MPS0 FREQS PLLE

Default

0 0 0 0 0 0 0 0

Bit 7 to 6: PLL Clock Input [1:0] (PCLKI[1:0]). These bits select the input into to the PLL.

00 MCLK is used.

01 RCLK1 to 8 is used based on the selection in register

CCR.

10 RCLK9 to 16 is used based on the selection in register CCR.

Reserved.

Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK will be
disabled and the TECLK output is a LOS output. TECLK requires PLLE to be set for correct functionality.

Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set CLKA will be disabled
and the CLKA output is a LOS output. CLKA requires PLLE to be set for correct functionality.

Bit 3 to 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK frequency for
the DS26324. See

Table 6-16

for details. This register when written to will also controller functionality of channels 9

to 16.

Bit 1: Frequency Select(FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the
DS26324. If this bit is set the external Master clock can be 1.544 MHz or multiple thereof. If not set the external
master clock can be 2.048 MHz or multiple thereof. See

Table 6-16

for details. This register when written to will

also controller functionality of channels 9 to 16.

Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If not set MCLK will
be the applied input clock.

Table 6-16. MCLK Selections for the DS26324

PLLE MPS1,

MPS0

MCLK

MHz, ±50ppm

FREQS

T1 OR E1

MODE

0 xx

1.544

x T1

0 xx

2.048

x E1

1.544

T1/J1 or E1

3.088

T1/J1 or E1

6.176

T1/J1 or E1

12.352

T1/J1 or E1

2.048

T1/J1 or E1

4.096

T1/J1 or E1

8.192

T1/J1 or E1

16.384

T1/J1 or E1

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RSMM1

Receive Sensitivity Monitor Mode 1

08h

Bit

# 7 6 5 4 3 2 1 0

Name

RTR2 C2RSM2 C2RSM1 C2RSM0 RTR1 C1RSM2 C1RSM1 C1RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 2(RTR2). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 6 4: Channel 2 Receive Sensitivity/Monitor Select [2:0] (C2RSM[2:0]). When bits C2RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 1(RTR1). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 2 0: Channel 1 Receive Sensitivity/Monitor Select [2:0] (C1RSM[2:0]). When bits C1RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

28h

Bit

# 7 6 5 4 3 2 1 0

Name

RTR10 C10RSM2 C10RSM1 C10RSM0 RTR9

C9RSM2 C9RSM1 C9RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 10(RTR10). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 10 Receive Sensitivity/Monitor Select [2:0] (C10RSM[2:0]). When bits C10RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 9(RTR9). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 9 Receive Sensitivity/Monitor Select [2:0] (C9RSM[2:0]). When bits C9RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RSMM2

Receive Sensitivity Monitor Mode 2

09h

Bit

# 7 6 5 4 3 2 1 0

Name

RTR4 C4RSM2 C4RSM1 C4RSM0 RTR3 C3RSM2 C3RSM1 C3RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 4(RTR4). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 4 Receive Sensitivity/Monitor Select [2:0] (C4RSM[2:0]). When bits C4RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 3(RTR3). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 3 Receive Sensitivity/Monitor Select [2:0] (C3RSM[2:0]). When bits C3RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

29h

Bit

# 7 6 5 4 3 2 1 0

Name

RTR12 C12RSM2 C12RSM1 C12RSM0 RTR11 C11RSM2 C11RSM1 C11RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 12(RTR12). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 12 Receive Sensitivity/Monitor Select [2:0] (C12RSM[2:0]). When bits C12RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 11(RTR11). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 11 Receive Sensitivity/Monitor Select [2:0] (C11RSM[2:0]). When bits C11RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RSMM3

Receive Sensitivity Monitor Mode 3

0Ah

Bit

# 7 6 5 4 3 2 1 0

Name

RTR6 C6RSM2 C6RSM1 C6RSM0 RTR5 C5RSM2 C5RSM1 C5RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 6(RTR6). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 6 Receive Sensitivity/Monitor Select [2:0] (C6RSM[2:0]). When bits C6RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 5(RTR5). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 5 Receive Sensitivity/Monitor Select [2:0] (C5RSM[2:0]). When bits C5RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

2Ah

Bit

# 7 6 5 4 3 2 1 0

Name

RTR14 C14RSM2 C14RSM1 C14RSM0 RTR13 C13RSM2 C13RSM1 C13RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 14(RTR14). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 14 Receive Sensitivity/Monitor Select [2:0] (C14RSM[2:0]). When bits C14RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 13(RTR13). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 13 Receive Sensitivity/Monitor Select [2:0] (C13RSM[2:0]). When bits C13RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RSMM4

Receive Sensitivity Monitor Mode 4

0Bh

Bit

# 7 6 5 4 3 2 1 0

Name

RTR8 C8RSM2 C8RSM1 C8RSM0 RTR7 C7RSM2 C7RSM1 C7RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 8(RTR8). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 8 Receive Sensitivity/Monitor Select [2:0] (C8RSM[2:0]). When bits C8RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 7(RTR7). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 7 Receive Sensitivity/Monitor Select [2:0] (C7RSM[2:0]). When bits C7RSM[2:0] are used to
select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

2Bh

Bit

# 7 6 5 4 3 2 1 0

Name

RTR16 C16RSM2 C16RSM1 C16RSM0 RTR15 C15RSM2 C15RSM1 C15RSM0

Default

0 0 0 0 0 0 0 0

Bit 7: Receiver Transformer Turns Ratio Channel 16(RTR16). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive
internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1.

Bit 64: Channel 16 Receive Sensitivity/Monitor Select [2:0] (C16RSM[2:0]). When bits C16RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Bit 3: Receiver Transformer Turns Ratio Channel 15(RTR15). If this bit is set the Turns Ratio is 1:1 on the
Receiver Side. This bit should be set when a 1:1 Receiver transformer is used.

Bit 20: Channel 15 Receive Sensitivity/Monitor Select [2:0] (C15RSM[2:0]). When bits C15RSM[2:0] are used
to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See

Table 6-17

Table 6-17. Receiver Sensitivity/Monitor Mode Gain Selection

RECEIVER

MONITOR

MODE

DISABLED

CNRSM [2:0],

T1/E1 MODE

RECEIVER

SENSITIVITY

(MAXIMUM

LOSS) (dB)

RECEIVER

MONITOR

MODE GAIN

SETTINGS

(dB)

LOSS

DECLARATION

LEVEL

(dB)

No flat gain

000

No flat gain

001

Receiver

monitor mode

enabled

CnRSM [2:0]

Max cable loss

Receiver

monitor mode

gain settings

Flat gain

100

Flat gain

101

22.5

45.5

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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RSL2

Receive Signal Level Indicator 2

0Dh

Bit

# 7 6 5 4 3 2 1 0

Name C4RSL3 C4RSL2 C4RSL1 C4RSL0 C3RSL3 C3RSL2 C3RSL1 C3RSL0
Default

0 0 0 0 0 0 0 0

Bit 7 to 4: Channel 4 Receive Signal Level [3:0] (C4RSL[3:0]). C4RSL[3:0] bits provide the Receive Signal Level
as shown in

Table 6-18

Bit 3 to 0: Channel 3 Receive Signal Level [3:0] (C3RSL[3:0]). C3RSL[3:0] bits provide the Receive Signal Level
as shown in

Table 6-18

2Dh

Bit

# 7 6 5 4 3 2 1 0

Name C12RSL3 C12RSL2 C12RSL1 C12RSL0 C11RSL3 C11RSL2 C11RSL1 C11RSL0
Default

0 0 0 0 0 0 0 0

Bit 7 to 4: Channel 12 Receive Signal Level [3:0] (C12RSL[3:0]). C12RSL[3:0] bits provide the Receive Signal
Level as shown in

Table 6-18

Bit 3 to 0: Channel 11 Receive Signal Level [3:0] (C11RSL[3:0]). C11RSL[3:0] bits provide the Receive Signal
Level as shown in

Table 6-18

RSL3

Receive Signal Level Indicator 3

0Eh

Bit

# 7 6 5 4 3 2 1 0

Name C6RSL3 C6RSL2 C6RSL1 C6RSL0 C5RSL3 C5RSL2 C5RSL1 C5RSL0
Default

0 0 0 0 0 0 0 0

Bit 7 to 4: Channel 6 Receive Signal Level [3:0] (C6RSL[3:0]). C6RSL[3:0] bits provide the Receive Signal Level
as shown in

Table 6-18

Bit 3 to 0: Channel 5 Receive Signal Level [3:0] (C5RSL[3:0]). C5RSL[3:0] bits provide the Receive Signal Level
as shown in

Table 6-18

2Eh

Bit

# 7 6 5 4 3 2 1 0

Name C14RSL3 C14RSL2 C14RSL1 C14RSL0 C13RSL3 C13RSL2 C13RSL1 C13RSL0
Default

0 0 0 0 0 0 0 0

Bit 7 to 4: Channel 14 Receive Signal Level [3:0] (C14RSL[3:0]). C14RSL[3:0] bits provide the Receive Signal
Level as shown in

Table 6-18

Bit 3 to 0: Channel 13 Receive Signal Level [3:0] (C13RSL[3:0]). C13RSL[3:0] bits provide the Receive Signal
Level as shown in

Table 6-18

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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BTCR

Bit Error Rate Tester Control Register

10h

Bit

# 7 6 5 4 3 2 1 0

Name

BTS2

BTS1

BTS0

-- -- -- --

BERTE

Default

0 0 0 0 0 0 0 0

This register enables the LIU1-8 BERT. The BERT can only connect to one LIU at a time. The LIU1-8 BERT
operates independently of the LIU9-16 BERT.

Bit 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]) These bits BTS[2:0] select the LIU that the BERT
applies too (see

Table 6-19

). This is only applicable if the BERTE bit is set.

Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2

mseconds have past, the Bit Error Rate

Tester (BERT) will be enabled. The BERT Register Set should be written and read to only after being enabled. The
BERT is only active for one LIU at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode
with HDB3/B8ZS encoding enabled.

30h

Bit

# 7 6 5 4 3 2 1 0

Name

BTS2

BTS1

BTS0

-- -- -- --

BERTE

Default

0 0 0 0 0 0 0 0

This register enables the LIU9-16 BERT. The BERT can only connect to one LIU at a time. The LIU9-16 BERT
operates independently of the LIU1-8 BERT.
Bit 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]) These bits BTS[2:0] select the LIU that the BERT
applies too (see

Table 6-20

). This is only applicable if the BERTE bit is set.

Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2

ms have past, the Bit Error Rate Tester

(BERT) will be enabled. The BERT Register Set should be written and read to only after being enabled. The BERT
is only active for one LIU at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode with
HDB3/B8ZS encoding enabled.

Table 6-19. Bit Error Rate Transceiver Select for Channels 18

REGISTER

ADDRESS

BTS2 BTS1 BTS0

CHANNEL BERT

APPLIES TO

10h 0 0 0 Channel

10h 0 1 0 Channel

10h 0 1 1 Channel

10h 1 0 0 Channel

10h 1 0 1 Channel

10h 1 1 0 Channel

10h 1 1 1 Channel

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

74 of 112

Table 6-20. Bit Error Rate Transceiver Select for Channels 916

REGISTER

ADDRESS

BTS2 BTS1 BTS0

CHANNEL BERT

APPLIES TO

30h 0 0 0 Channel

30h 0 1 0 Channel

30h 0 1 1 Channel

30h 1 0 0 Channel

30h 1 0 1 Channel

30h 1 1 0 Channel

30h 1 1 1 Channel

BEIR

BPV Error Insertion Register

11h

Bit

# 7 6 5 4 3 2 1 0

Name BEIR8 BEIR7 BEIR6 BEIR5 BEIR4 BEIR3 BEIR2 BEIR1
Default

0 0 0 0 0 0 0 0

31h

Bit

# 7 6 5 4 3 2 1 0

Name BEIR16 BEIR15 BEIR14 BEIR13 BEIR12 BEIR11 BEIR10 BEIR9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: BPV Error Insertion Register n (BEIRn). A 0 to 1 transition on this bit will cause a single bipolar
violation (BPV) to be inserted into the transmit data stream channel n. This bit must be cleared and set again for a
subsequent error to be inserted. This is only applicable in single-rail mode.

LVDS

Line Violation Detect Status

12h

Bit

# 7 6 5 4 3 2 1 0

Name LVDS8 LVDS7 LVDS6 LVDS5 LVDS4 LVDS3 LVDS2 LVDS1
Default

0 0 0 0 0 0 0 0

32h

Bit

# 7 6 5 4 3 2 1 0

Name LVDS16 LVDS15 LVDS14 LVDS13 LVDS12 LVDS11 LVDS10 LVDS9
Default

0 0 0 0 0 0 0 0

Bit 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros will
cause the associated LVDSn bit to latch. This bit will be cleared on a read operation. The LVDS register captures
the first violation within a three clock period window. If a second violation occurs after the first violation within the
three clock period window, then the second violation will not be latched even if a read to the LVDS register was
performed. Excessive zeros need to be enabled by the

EZDE

are only relative when in HDB3 mode and can be disabled for detection by this register by setting the

CVDEB

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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CCR

Clock Control Register

15h

Bit

# 7 6 5 4 3 2 1 0

Name PCLKS2 PCLKS1 PCLKS0 TECLKS CLKA3 CLKA2 CLKA1

CLKA0

Default

0 0 0 0 0 0 0 0

Bit 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the
PLL. If a LOS is detect for the channel that RCLK is recovered from, the PLL will switch to MCLK until the LOS is
cleared. When the LOS is cleared RCLK will be used again. See

Table 6-21

for RCLK selection. MC.PCLKI[1:0]

must be set to `01' or `10' in order for these settings to take affect.

Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is
reset the T1/E1 clock rate is 1.544MHz

Bit 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See

Table 6-22

for

available frequencies. For best jitter performance, select MCLK as the source for CLKA and input a 2.048 MHz
MCLK.

Table 6-21. PLL Clock Select

PCLKS2 TO

PCLKS0

PLL CLOCK

SELECTED

MC.

PCLKI[1:0]=01

PLL CLOCK

SELECTED

MC.

PCLKI[1:0]=10

000 RCLK1

RCLK9

001 RCLK2

RCLK10

010 RCLK3

RCLK11

011 RCLK4

RCLK12

100 RCLK5

RCLK13

101 RCLK6

RCLK14

110 RCLK7

RCLK15

111 RCLK8

RCLK16

Table 6-22. Clock A Select

CLKA3 TO CLKA0

CLKA (Hz)

0000 2.048M
0001 4.096M
0010 8.192M
0011 16.384M
0100 1.544M
0101 3.088M
0110 6.176M
0111 12.352M
1000 1.536M
1001 3.072M
1010 6.144M
1011 12.288M
1100 32k
1101 64k
1110 128k
1111 256k

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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6.1.4 BERT

Registers

BCR

BERT Control Register

00h

20h

Bit

# 7 6 5 4 3 2 1 0

Name PMUM LPMU RNPL RPIC MPR APRD TNPL TPIC
Default

0 0 0 0 0 0 0 0

Bit 7: Performance Monitoring Update Mode (PMUM). When 0, a performance monitoring update is initiated by
the LPMU register bit. When 1, a performance monitoring update is initiated by the receive performance monitoring
update signal (RPMU). Note: If RPMU or LPMU is one, changing the state of this bit may cause a performance
monitoring update to occur.

Bit 6: Local Performance Monitoring Update (LPMU). This bit causes a performance monitoring update to be
initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance
monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance
monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit
goes high, an update might not be performed. This bit has no affect when PMUM=1.

Bit 5: Receive New Pattern Load (RNPL). A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit
must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the
receive pattern generator out of the "Sync" state which causes a resynchronization to be initiated. Note: QRSS,
PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four
RXCK clock cycles after this bit transitions from 0 to 1.

Bit 4: Receive Pattern Inversion Control (RPIC). When 0, the received incoming data stream is not altered.
When 1, the received incoming data stream is inverted.

Bit 3: Manual Pattern Resynchronization (MPR). A zero to one transition of this bit will cause the receive pattern
generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another
resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator out of the
"Sync" state.

Bit 2: Automatic Pattern Resynchronization Disable (APRD) When 0, the receive pattern generator will
automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern
generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is
prevented by not allowing the receive pattern generator to automatically exit the "Sync" state.

Bit 1: Transmit New Pattern Load (TNPL). A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit
must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0],
and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this
bit transitions from 0 to 1.

Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered.
When 1, the transmit outgoing data stream is inverted.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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BPCR1

BERT Pattern Configuration Register 1

02h

22h

Bit

# 7 6 5 4 3 2 1 0

Name -- QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0
Default

0 0 0 0 0 0 0 0

Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x

+ x

+ 1. The output of the pattern generator will be forced to one if the next fourteen

output bits are all zero.

Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.

Bit 4-0: Pattern Length Feedback (PLF[4:0]). These five bits control the "length" feedback of the pattern
generator. The "length" feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.

BPCR 2

BERT Pattern Configuration Register 2

03h

23h

Bit

# 7 6 5 4 3 2 1 0

Name --

-- PTF4 PTF3 PTF2 PTF1 PTF0

Default

0 0 0 0 0 0 0 0

Bit 4-0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS "tap" feedback of the pattern
generator. The "tap" feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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TEICR

Transmit Error Insertion Control Register

08h

28h

Bit

# 7 6 5 4 3 2 1 0

Name

-- TEIR2 TEIR1 TEIR0 BEI TSEI MEIMS

Default

0 0 0 0 0 0 0 0

Bit 5-3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are inserted
in the output data stream. One out of every 10

bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0

disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10

bit being inverted. A TEIR[2:0]

value of 2 results in every 100

bit being inverted. Error insertion starts when this register is written to with a

TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process, the new
error rate will be started after the next error is inserted.

Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.

Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be
inserted.

Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause a bit error to be inserted.

BSR

BERT Status Register

0Ch

2Ch

Bit

# 7 6 5 4 3 2 1 0

Name

-- -- -- --

PMS -- BEC OOS

Default

0 0 0 0 0 0 0 0

Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low.

Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more.

Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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BSRL

BERT Status Register Latched

0Eh

2Eh

Bit

# 7 6 5 4 3 2 1 0

Name

-- -- -- --

PMSL BEL BECL OOSL

Default

0 0 0 0 0 0 0 0

Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from
0 to 1. A read operation clears this bit.

Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected. A read operation clears this bit.

Bit 1: Bit Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1. A read operation
clears this bit.

Bit 0: Out Of Synchronization Latched (OOSL). This bit is set when the OOS bit changes state. A read operation
clears this bit.

BSRIE

BERT Status Register Interrupt Enable

10h

30h

Bit

# 7 6 5 4 3 2 1 0

Name

-- -- -- --

PMSIE

BEIE

BECIE

OOSIE

Default

0 0 0 0 0 0 0 0

Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the
PMSL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 2: Bit Error Interrupt Enable (BEIE). This bit enables an interrupt if the BEL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set.

0 = interrupt disabled

1 = interrupt enabled

Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set.

0 = interrupt disabled

1 = interrupt enabled

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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7.1 TAP Controller State Machine

The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCLK. The
state diagram is shown in

Figure 7-2.

Test-Logic-Reset

Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally. This state is automatically entered during
power-up. This state is entered from any state if the TMS is held high for at least 5 clocks.

Run-Test-Idle

The run-test-idle is used between scan operations or during specific tests. The instruction register and test
registers will remain idle. The controller remains in this state when TMS is held low. When the TMS is high and
rising edge of TCLK is applied the controller moves to the Select-DR-Scan State.

Select-DR-Scan

All test registers retain their previous state. With TMS LOW, a rising edge of TCLK moves the controller into the
capture-DR state and will initiate a scan sequence. TMS HIGH during a rising edge on TCLK moves the controller
to the select-IR-scan state.

Capture-DR

Data can be parallel-loaded into the test-data registers if the current instruction is EXTEST or SAMPLE/PRELOAD.
If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of TCLK, the controller will go to the shift-DR state if
TMS is LOW or it will go to the exit1-DR state if TMS is HIGH.

Shift-DR

The test-data register selected by the current instruction will be connected between TDI and TDO and will shift data
one stage towards its serial output on each rising edge of TCLK. If a test register selected by the current instruction
is not placed in the serial path, it will maintain its previous state. When the TAP Controller is in this state and a
rising edge of TCLK is applied, the controller enters the EXIT1-DR state if TMS is high or remains in SHIFT-DR
state if TMS is low.

Exit1-DR

While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the
scanning process, if TMS is HIGH. A rising edge on TCLK with TMS LOW will put the controller in the Pause-DR
state.

Pause-DR

Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while TMS is LOW. A rising edge on TCLK with
TMS HIGH will put the controller in the exit2-DR state.

Exit2-DR

A rising edge on TCLK with TMS HIGH while in this state will put the controller in the update-DR state and
terminate the scanning process. A rising edge on TCLK with TMS LOW will enter the shift-DR state.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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Update-DR

A falling edge on TCLK while in the update-DR state will latch the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.

Select-IR-Scan

All test registers retain their previous state. The instruction register will remain unchanged during this state. With
TMS LOW, a rising edge on TCLK moves the controller into the capture-IR state and will initiate a scan sequence
for the instruction register. TMS HIGH during a rising edge on TCLK puts the controller back into the Test-logic-
reset state.

Capture-IR

The capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of TCLK. If TMS is HIGH on the rising edge of TCLK, the controller will enter the exit1-IR
state. If TMS is LOW on the rising edge of TCLK, the controller will enter the shift-IR state.

Shift-IR

In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one
stage for every rising edge of TCLK towards the serial output. The parallel registers as well as all test registers
remain at their previous states. A rising edge on TCLK with TMS HIGH will move the controller to the exit1-IR state.
A rising edge on TCLK with TMS LOW will keep the controller in the shift-IR state while moving data one stage
thorough the instruction shift register.

Exit1-IR

A rising edge on TCLK with TMS LOW will put the controller in the pause-IR state. If TMS is HIGH on the rising
edge of TCLK, the controller will enter the update-IR state and terminate the scanning process.

Pause-IR

Shifting of the instruction shift register is halted temporarily. With TMS HIGH, a rising edge on TCLK will put the
controller in the Exit2-IR state. The controller will remain in the Pause-IR state if TMS is LOW during a rising edge
on TCLK.

Exit2-IR

A rising edge on TCLK with TMS High will put the controller in the Update-IR state. The controller will loop back to
shift-IR if TMS is LOW during a rising edge of TCLK in this state.

Update-IR

The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of
TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising
edge on TCLK with TMS LOW will put the controller in the run-test-idle state. With TMS HIGH, the controller will
enter the select-DR-scan state.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

89 of 112

7.2 Instruction

Register

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the shift-IR state, the instruction shift register will be connected between TDI and TDO. While
in the shift-IR state, a rising edge on TCLK with TMS LOW will shift the data one stage towards the serial output at
TDO. A rising edge on TCLK in the exit1-IR state or the exit2-IR state with TMS HIGH will move the controller to
the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS26324 and its respective operational binary codes are
shown in

Table 7-1

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture

INSTRUCTION SELECTED

REGISTER INSTRUCTION

CODES

EXTEST Boundary

Scan

000

HIGHZ Bypass 010

CLAMP Bypass 011

SAMPLE/PRELOAD Boundary

Scan

100

IDCODE Device

Identification

110

BYPASS Bypass

111

EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins will be driven. The boundary scan register will be connected between TDI and TDO. The Capture-DR will
sample all digital inputs into the boundary scan register.

HIGHZ
All digital outputs of the device will be placed in a high-Z state. The BYPASS register will be connected between
TDI and TDO.

CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between TDI and TDO. The outputs will not change during the CLAMP instruction.

SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the
device can be sampled at the boundary scan register without interfering with the normal operation of the device by
using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan
register via TDI using the shift-DR state.

IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code will be loaded into the identification register on the rising edge of TCLK
following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via TDO.
During test-logic-reset, the identification code is forced into the instruction register's parallel output. The ID code
will always have a 1 in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number
of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 7-2. Table 7-3 lists the
device ID code for the DS26324.

BYPASS
When the BYPASS instruction is latched into the parallel instruction register, TDI connects to TDO through the one-
bit bypass test register. This allows data to pass from TDI to TDO not affecting the device's normal operation.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

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8 DC ELECTRICAL CHARACTERIZATION

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Lead with Respect to V

(except V

)....................................................-0.3V to +5.5V

Supply Voltage (V

) Range with Respect to V

....................................................................

0.3V to +3.63V

Operating Temperature Range for DS26324G..........................................................................0°C to +70°C
Operating Temperature Range for DS26324GN......................................................................-40°C to +85°C
Storage Temperature.......................................................................................................-55°C to +125°C
Soldering Temperature...................................................................See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

Table 8-1. DC Pin Logic Levels
RECOMMENDED DC OPERATING CONDITIONS

= -40°C to +85°C for DS26324GN.)

PARAMETER SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1

2.0 5.5 V

Logic 0

0.3 +0.8 V

Supply V

3.135 3.3

3.465 V

Table 8-2. Pin Capacitance
CAPACITANCE

= +25°C)

PARAMETER SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Capacitance

7 pF

Output Capacitance

OUT

7 pF

Table 8-3. Supply Current and Output Voltage
DC CHARACTERISTICS

= 3.135 to 3.465V, T

= -40°C to +85°C.)

PARAMETER SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Supply Current at 3.465V

1100 mA 1,

Supply Current at 3.3V

500

Input Leakage

10.0 +10.0

Tri-State Output Leakage

10.0 +10.0

Output Voltage (I

= 4.0mA)

2.4 V

Output Voltage (I

= +4.0mA)

0.4

Note 1:

RCLK1-n = TCLK1-n = 1.544MHz.

Note 2:

Supply current with all ports active, TTIP and TRING driving a 25

W load, for an all-ones data density.

DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit

109

112

10 PIN CONFIGURATION

Figure 10-1. 256-Ball TEBGA

RTIP1

RRING1

MODESEL

RTIP16

VDDT16

TTIP16

TTIP15

VDDT15

RTIP15

VDDT14

TTIP14

TTIP13

VDDT13

RTIP14

TDO

RTIP13

AVDD

AVSS

MOTEL

RRING16

RSTB

TRING16

TRING15

LOS14

RRING15

LOS13

TRING14

TRING13

TMS

RRING14

TDI

RRING13

RTIP2

RRING2

TNEG1

TNEG16

TNEG15

RNEG15

RPOS15

RNEG14

RPOS14

TCLK13

RPOS13

SDO/RDY/ACKB

TPOS12

AVSS

AVDD

VDDT1

LOS1

RCLK1

GNDT1

TPOS16

GNDT16

INTB

GNDT15

GNDT14

GNDT13

TCLK16

TCLK14

GNDT12

TCK

RRING12

RTIP12

TTIP1

TRING1

RNEG1

RPOS16

RCLK16

TPOS14

RCLK13

RCLK14

RNEG13

LOS15

TCLK12

TNEG12

RPOS12

TRSTB

VDDT12

TTIP2

TRING2

RPOS2

RPOS1

TCLK1

TPOS1

TNEG14

RCLK15

TPOS13

LOS16

RNEG12

RCLK12

RNEG11

TCLK11

TRING12

TTIP12

VDDT2

LOS2

TCLK2

RNEG2

RCLK2

TPOS2

TNEG13

TCLK3

TNEG4

TPOS11

RPOS11

RCLK11

SDI/WRB/DSB

TRING11

TTIP11

RTIP3

RRING3

GNDT2

TCLK4

AVDD

DVDD

DVSS

AVSS

TNEG11

MCLK

GNDT11

RDB/RWB

LOS12

VDDT11

VDDT3

LOS3

RNEG16

GNDT3

TNEG3

TPOS3

AVSS

DVSS

DVDD

AVDD

TPOS10

TNEG10

GNDT10

TNEG2

RRING11

RTIP11

TTIP3

TRING3

RCLK3

RNEG3

RCLK4

TPOS4

RPOS5

TNEG8

RNEG8

TCLK9

TCLK10

RPOS10

RCLK10

LOS11

VDDT10

TTIP4

TRING4

RPOS3

RPOS4

RNEG5

TCLK6

TPOS5

TCLK7

TPOS9

TNEG9

RCLK9

RNEG10

TRING10

TTIP10

VDDT4

LOS4

RNEG4

TNEG5

TCLK5

RCLK6

RPOS6

RNEG6

TPOS8

RPOS8

RNEG9

RPOS9

TRING9

TTIP9

RTIP4

RRING4

GNDT4

TPOS6

GNDT5

TCLK15

GNDT6

GNDT7

GNDT8

TPOS15

GNDT9

SCLK/ALE/ASB

LOS10

VDDT9

AVDD

AVSS

RCLK5

TNEG6

TNEG7

RPOS7

TCLK8

RCLK7

RNEG7

TPOS7

RCLK8

CSB

RRING10

RTIP10

RRING5

LOS5

RRING6

LOS7

TRING5

TRING6

LOS8

RRING7

DVSS

TRING7

TRING8

RRING8

LOS9

AVSS

AVDD

RTIP5

LOS6

RTIP6

VDDT5

TTIP5

TTIP6

VDDT6

RTIP7

VDDT7

TTIP7

TTIP8

VDDT8

RTIP8

CLKE/MUX

RRING9

RTIP9

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