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REV: 032405
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.
GENERAL DESCRIPTION
The DS26502 is a building-integrated timing-
supply (BITS) clock-recovery element. It also
functions as a basic T1/E1 transceiver. The
receiver portion can recover a clock from T1,
E1, 64kHz composite clock (64KCC), and
6312kHz synchronization timing interfaces. In
T1 and E1 modes, the Synchronization Status
Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1,
or 64KCC synchronization interfaces as well as
source the SSM in T1 and E1 modes. The
DS26502 can translate between any of the
supported inbound synchronization clock rates to
any supported outbound rate. A separate output
is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
APPLICATIONS
BITS Timing
Rate Conversion
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26502L
0C to +70C
64 LQFP
DS26502LN -40C to +85C 64 LQFP
FEATURES
G.703 2048kHz Synchronization Interface
Compliant
G.703 64kHz Centralized (Option A) and
Codirectional Timing Interface Compliant
G.703 Appendix II 64kHz and 6312kHz
Japanese Synchronization Interface
Compliant
Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
Interface to CMI-Coded T1/J1 and E1
Short- and Long-Haul Line Interface
Transmit and Receive T1 and E1 SSM
Messages with Message Validation
T1/E1 Jitter Attenuator with Bypass Mode
Fully Independent Transmit and Receive
Functionality
Internal Software-Selectable Receive- and
Transmit-Side Termination for
75/100/110/120 T1, E1, and
Composite Clock Interfaces
Monitor Mode for Bridging Applications
Accepts 16.384MHz, 8.192MHz, 4.096MHz,
or 2.048MHz Master Clock
64kHz, 8kHZ, and 400Hz Outputs in
Composite Clock Mode
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
Serial (SPI) Control Port
Hardware Control Mode
Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
IEEE 1149.1 JTAG Boundary Scan
3.3V Supply with 5V-Tolerant Inputs and
Outputs
DS26502
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
DS26502 T1/E1/J1/64KCC BITS Element
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TABLE OF CONTENTS
1.
FEATURES......................................................................................................................7
1.1
G
ENERAL
........................................................................................................................7
1.2
L
INE
I
NTERFACE
...............................................................................................................7
1.3
J
ITTER
A
TTENUATOR
(T1/E1 M
ODES
O
NLY
) ......................................................................7
1.4
F
RAMER
/F
ORMATTER
.......................................................................................................8
1.5
T
EST AND
D
IAGNOSTICS
...................................................................................................8
1.6
C
ONTROL
P
ORT
...............................................................................................................8
2.
SPECIFICATIONS COMPLIANCE ...................................................................................9
3.
BLOCK DIAGRAMS .......................................................................................................11
4.
PIN FUNCTION DESCRIPTION .....................................................................................14
4.1
T
RANSMIT
PLL...............................................................................................................14
4.2
T
RANSMIT
S
IDE
..............................................................................................................14
4.3
R
ECEIVE
S
IDE
................................................................................................................15
4.4
C
ONTROLLER
I
NTERFACE
................................................................................................16
4.5
JTAG ...........................................................................................................................20
4.6
L
INE
I
NTERFACE
.............................................................................................................20
4.7
P
OWER
.........................................................................................................................21
5.
PINOUT...........................................................................................................................22
6.
HARDWARE CONTROLLER INTERFACE....................................................................25
6.1
T
RANSMIT
C
LOCK
S
OURCE
.............................................................................................25
6.2
I
NTERNAL
T
ERMINATION
..................................................................................................25
6.3
L
INE
B
UILD
-O
UT
.............................................................................................................26
6.4
R
ECEIVER
O
PERATING
M
ODES
........................................................................................26
6.5
T
RANSMITTER
O
PERATING
M
ODES
..................................................................................27
6.6
MCLK P
RE
-S
CALER
......................................................................................................27
6.7
O
THER
H
ARDWARE
C
ONTROLLER
M
ODE
F
EATURES
.........................................................28
7.
PROCESSOR INTERFACE ............................................................................................29
7.1
P
ARALLEL
P
ORT
F
UNCTIONAL
D
ESCRIPTION
.....................................................................29
7.2
SPI S
ERIAL
P
ORT
I
NTERFACE
F
UNCTIONAL
D
ESCRIPTION
.................................................29
7.2.1
Clock Phase and Polarity .........................................................................................29
7.2.2
Bit Order...................................................................................................................29
7.2.3
Control Byte .............................................................................................................29
7.2.4
Burst Mode...............................................................................................................29
7.2.5
Register Writes.........................................................................................................30
7.2.6
Register Reads ........................................................................................................30
7.3
R
EGISTER
M
AP
..............................................................................................................31
7.3.1
Power-Up Sequence ................................................................................................33
7.3.2
Test Reset Register .................................................................................................33
7.3.3
Mode Configuration Register....................................................................................34
7.4
I
NTERRUPT
H
ANDLING
....................................................................................................37
7.5
S
TATUS
R
EGISTERS
.......................................................................................................37
7.6
I
NFORMATION
R
EGISTERS
...............................................................................................38
DS26502 T1/E1/J1/64KCC BITS Element
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7.7
I
NTERRUPT
I
NFORMATION
R
EGISTERS
..............................................................................38
8.
T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................39
8.1
T1 C
ONTROL
R
EGISTERS
...............................................................................................39
9.
E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................45
9.1
E1 C
ONTROL
R
EGISTERS
...............................................................................................45
9.2
E1 I
NFORMATION
R
EGISTERS
..........................................................................................47
10.
I/O PIN CONFIGURATION OPTIONS ............................................................................51
11.
T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................54
11.1
T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
................................................................54
11.2
T
RANSMIT
BOC.............................................................................................................54
11.3
R
ECEIVE
BOC...............................................................................................................55
12.
E1 SYNCHRONIZATION STATUS MESSAGE ..............................................................63
12.1
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
CRC4 M
ULTIFRAME
...........................................................63
12.2
A
LTERNATE
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
D
OUBLE
-F
RAME
...............................................73
13.
LINE INTERFACE UNIT (LIU) ........................................................................................76
13.1
LIU O
PERATION
............................................................................................................77
13.2
LIU R
ECEIVER
..............................................................................................................77
13.2.1
Receive Level Indicator............................................................................................77
13.2.2
Receive G.703 Section 10 Synchronization Signal ..................................................78
13.2.3
Monitor Mode ...........................................................................................................78
13.3
LIU T
RANSMITTER
.........................................................................................................78
13.3.1
Transmit Short-Circuit Detector/Limiter ....................................................................79
13.3.2
Transmit Open-Circuit Detector................................................................................79
13.3.3
Transmit BPV Error Insertion ...................................................................................79
13.3.4
Transmit G.703 Section 10 Synchronization Signal (E1 Mode)................................79
13.4
MCLK P
RE
-S
CALER
......................................................................................................79
13.5
J
ITTER
A
TTENUATOR
......................................................................................................79
13.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
...........................................................................80
13.7
LIU C
ONTROL
R
EGISTERS
.............................................................................................81
13.8
R
ECOMMENDED
C
IRCUITS
..............................................................................................89
14.
LOOPBACK CONFIGURATION.....................................................................................94
15.
64KHZ SYNCHRONIZATION INTERFACE....................................................................95
15.1
R
ECEIVE
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
............................................95
15.2
T
RANSMIT
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
..........................................96
16.
6312KHZ SYNCHRONIZATION INTERFACE................................................................97
16.1
R
ECEIVE
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
........................................97
16.2
T
RANSMIT
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.......................................97
17.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................98
17.1
I
NSTRUCTION
R
EGISTER
...............................................................................................102
17.2
T
EST
R
EGISTERS
.........................................................................................................103
DS26502 T1/E1/J1/64KCC BITS Element
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17.3
B
OUNDARY
S
CAN
R
EGISTER
.........................................................................................103
17.4
B
YPASS
R
EGISTER
......................................................................................................103
17.5
I
DENTIFICATION
R
EGISTER
............................................................................................103
18.
FUNCTIONAL TIMING DIAGRAMS .............................................................................106
18.1
P
ROCESSOR
I
NTERFACE
...............................................................................................106
18.1.1
Parallel Port Mode..................................................................................................106
18.1.2
SPI Serial Port Mode..............................................................................................106
19.
OPERATING PARAMETERS .......................................................................................109
20.
AC TIMING PARAMETERS AND DIAGRAMS ............................................................111
20.1
M
ULTIPLEXED
B
US
.......................................................................................................111
20.2
N
ONMULTIPLEXED
B
US
................................................................................................114
20.3
S
ERIAL
B
US
................................................................................................................117
20.4
R
ECEIVE
S
IDE
AC C
HARACTERISTICS
...........................................................................119
20.5
T
RANSMIT
S
IDE
AC C
HARACTERISTICS
.........................................................................121
21.
REVISION HISTORY ....................................................................................................123
22.
PACKAGE INFORMATION ..........................................................................................124
DS26502 T1/E1/J1/64KCC BITS Element
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LIST OF FIGURES
Figure 3-1. Block Diagram ..................................................................................................................... 11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ...................................................................... 12
Figure 3-3. Transmit PLL Clock Mux Diagram ....................................................................................... 12
Figure 3-4. Master Clock PLL Diagram.................................................................................................. 13
Figure 13-1. Basic Network Connection................................................................................................. 76
Figure 13-2. Typical Monitor Application................................................................................................ 78
Figure 13-3. CMI Coding ....................................................................................................................... 80
Figure 13-4. Software-Selected Termination, Metallic Protection........................................................... 89
Figure 13-5. Software-Selected Termination, Longitudinal Protection.................................................... 90
Figure 13-6. E1 Transmit Pulse Template ............................................................................................. 91
Figure 13-7. T1 Transmit Pulse Template.............................................................................................. 91
Figure 13-8. Jitter Tolerance (T1 Mode) ................................................................................................ 92
Figure 13-9. Jitter Tolerance (E1 Mode) ................................................................................................ 92
Figure 13-10. Jitter Attenuation (T1 Mode) ............................................................................................ 93
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................ 93
Figure 15-1. 64kHz Composite Clock Mode Signal Format.................................................................... 95
Figure 17-1. JTAG Functional Block Diagram........................................................................................ 98
Figure 17-2. TAP Controller State Diagram ......................................................................................... 101
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................. 106
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................. 106
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................. 106
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................. 107
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................. 107
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................. 107
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................. 108
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................. 108
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)............................................................. 112
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00).............................................................. 112
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ................................................................ 113
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01).............................................................. 115
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ................................................. 118
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ................................................. 118
Figure 20-10. Receive Timing, T1, E1, 64KCC Mode .......................................................................... 120
Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode ......................................................................... 122
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