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REV: 070105
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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.
GENERAL DESCRIPTION
The DS26504 is a building-integrated timing-supply
(BITS) clock-recovery element. It also functions as a
basic T1/E1 transceiver. The receiver portion can
recover a clock from T1, E1, 64kHz composite clock
(64KCC), and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the Synchronization
Status Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1, or
64KCC synchronization interfaces as well as source
the SSM in T1 and E1 modes. The DS26504 can
translate between any of the supported inbound
synchronization clock rates to any supported
outbound rate. The DS26504 can also accept an 8kHz
as well as a 19.44MHz reference clock. A separate
output is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
APPLICATIONS
BITS Timing
Rate Conversion
FEATURES
Accepts 8kHz and 19.44MHz References in
Addition to T1, E1, and 64kHz Composite Clock
GR378 Composite Clock Compliant
G.703 2048kHz Synchronization Interface
Compliant
G.703 64kHz Option A & B Centralized Clock
Synchronization Interface Compliant
G.703 64kHz Japanese Composite Clock
Synchronization Interface Compliant
G.703 6312kHz Japanese Synchronization
Interface Compliant
Interfaces to Standard T1/J1 (1.544MHz) and E1
(2.048MHz)
Interface to CMI-Coded T1/J1 and E1
T1/E1 Transmit Payload Clock Output
Short- and Long-Haul Line Interface
Transmit and Receive T1 BOC SSM Messages
with Receive Message Change of State and
Validation Indication
Transmit and Receive E1 Sa(n) Bit SSM
Messages with Receive Message Change of State
Indication
Crystal-Less Jitter Attenuator with Bypass Mode
for T1 and E1 Operation
Fully Independent Transmit and Receive
Functionality
Internal Software-Selectable Receive and
Transmit Side Termination for
75/100/110/120/133
Monitor Mode for Bridging Applications
Accepts 16.384MHz, 12.8MHz, 8.192MHz,
4.096MHz, 2.048MHz, or 1.544MHz Master
Clock
64kHz, 8kHz, and 400Hz Outputs in Composite
Clock Mode
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
Serial (SPI) Control Port and Hardware Control
Mode
Provides LOS, AIS, and LOF Indications through
Hardware Output Pins
Fast Transmitter Output Disable through Device
Pin for Protection Switching
IEEE 1149.1 JTAG Boundary Scan
3.3V Supply with 5V Tolerant Inputs and
Outputs
Pin and Software Compatible with the DS26502
and DS26503
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26504L
0C to +70C
64 LQFP
DS26504LN -40C to +85C 64 LQFP
DS26504
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
DS26502 T1/E1/J1/64KCC BITS Element
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TABLE OF CONTENTS
1.
FEATURES
............................................................................................................................ 7
1.1
G
ENERAL
.................................................................................................................................. 7
1.2
L
INE
I
NTERFACE
........................................................................................................................ 7
1.3
J
ITTER
A
TTENUATOR
(T1/E1 M
ODES
O
NLY
)................................................................................ 7
1.4
F
RAMER
/F
ORMATTER
................................................................................................................. 8
1.5
T
EST AND
D
IAGNOSTICS
............................................................................................................. 8
1.6
C
ONTROL
P
ORT
......................................................................................................................... 8
2.
SPECIFICATIONS COMPLIANCE
............................................................................... 9
3.
BLOCK DIAGRAMS
......................................................................................................... 11
4.
PIN FUNCTION DESCRIPTION
................................................................................... 14
4.1
T
RANSMIT
PLL ........................................................................................................................ 14
4.2
T
RANSMIT
S
IDE
....................................................................................................................... 14
4.3
R
ECEIVE
S
IDE
......................................................................................................................... 15
4.4
C
ONTROLLER
I
NTERFACE
......................................................................................................... 16
4.5
JTAG...................................................................................................................................... 20
4.6
L
INE
I
NTERFACE
...................................................................................................................... 21
4.7
P
OWER
................................................................................................................................... 21
5.
PINOUT
................................................................................................................................. 22
6.
HARDWARE CONTROLLER INTERFACE
............................................................ 25
6.1
T
RANSMIT
C
LOCK
S
OURCE
....................................................................................................... 25
6.2
I
NTERNAL
T
ERMINATION
........................................................................................................... 25
6.3
L
INE
B
UILD
-O
UT
...................................................................................................................... 26
6.4
R
ECEIVER
O
PERATING
M
ODES
................................................................................................. 27
6.5
T
RANSMITTER
O
PERATING
M
ODES
........................................................................................... 27
6.6
MCLK P
RE
-S
CALER
................................................................................................................ 28
6.7
P
AYLOAD
C
LOCK
O
UTPUT
........................................................................................................ 28
6.8
O
THER
H
ARDWARE
C
ONTROLLER
M
ODE
F
EATURES
.................................................................. 29
7.
PROCESSOR INTERFACE
........................................................................................... 30
7.1
P
ARALLEL
P
ORT
F
UNCTIONAL
D
ESCRIPTION
.............................................................................. 30
7.2
SPI S
ERIAL
P
ORT
I
NTERFACE
F
UNCTIONAL
D
ESCRIPTION
.......................................................... 30
7.2.1
Clock Phase and Polarity ..................................................................................................................... 30
7.2.2
Bit Order ............................................................................................................................................... 30
7.2.3
Control Byte ......................................................................................................................................... 30
7.2.4
Burst Mode........................................................................................................................................... 30
7.2.5
Register Writes..................................................................................................................................... 31
7.2.6
Register Reads .................................................................................................................................... 31
7.3
R
EGISTER
M
AP
........................................................................................................................ 32
7.3.1
Power-Up Sequence ............................................................................................................................ 34
7.3.2
Test Reset Register ............................................................................................................................. 34
7.3.3
Mode Configuration Register ............................................................................................................... 35
7.4
I
NTERRUPT
H
ANDLING
.............................................................................................................. 37
7.5
S
TATUS
R
EGISTERS
................................................................................................................. 37
7.6
I
NFORMATION
R
EGISTERS
........................................................................................................ 38
7.7
I
NTERRUPT
I
NFORMATION
R
EGISTERS
....................................................................................... 38
DS26504 T1/E1/J1/64KCC BITS Element
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8.
T1 FRAMER/FORMATTER CONTROL REGISTERS
......................................... 39
8.1
T1 C
ONTROL
R
EGISTERS
......................................................................................................... 39
9.
E1 FRAMER/FORMATTER CONTROL REGISTERS
........................................ 45
9.1
E1 C
ONTROL
R
EGISTERS
......................................................................................................... 45
9.2
E1 I
NFORMATION
R
EGISTERS
................................................................................................... 48
10.
I/O PIN CONFIGURATION OPTIONS
....................................................................... 52
11.
T1 SYNCHRONIZATION STATUS MESSAGE
..................................................... 55
11.1
T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
.......................................................................... 55
11.2
T
RANSMIT
BOC ....................................................................................................................... 55
11.3
R
ECEIVE
BOC ......................................................................................................................... 56
12.
E1 SYNCHRONIZATION STATUS MESSAGE
..................................................... 64
12.1
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
CRC4 M
ULTIFRAME
.................................................................... 64
12.1.1
Sa Bit Change of State......................................................................................................................... 65
12.2
A
LTERNATE
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
D
OUBLE
-F
RAME
........................................................ 76
13.
LINE INTERFACE UNIT (LIU)
...................................................................................... 79
13.1
LIU O
PERATION
....................................................................................................................... 80
13.2
LIU R
ECEIVER
......................................................................................................................... 80
13.2.1
Receive Level Indicator........................................................................................................................ 80
13.2.2
Receive G.703 Section 10 Synchronization Signal ............................................................................. 81
13.2.3
Monitor Mode ....................................................................................................................................... 81
13.3
LIU T
RANSMITTER
................................................................................................................... 81
13.3.1
Transmit Short-Circuit Detector/Limiter................................................................................................ 82
13.3.2
Transmit Open-Circuit Detector ........................................................................................................... 82
13.3.3
Transmit BPV Error Insertion ............................................................................................................... 82
13.3.4
Transmit G.703 Section 10 Synchronization Signal (E1 Mode)........................................................... 82
13.4
MCLK P
RE
-S
CALER
................................................................................................................ 82
13.5
J
ITTER
A
TTENUATOR
................................................................................................................ 82
13.6
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
..................................................................................... 83
13.7
LIU C
ONTROL
R
EGISTERS
........................................................................................................ 84
13.8
R
ECOMMENDED
C
IRCUITS
........................................................................................................ 92
13.9
C
OMPONENT
S
PECIFICATIONS
.................................................................................................. 94
14.
LOOPBACK CONFIGURATION
.................................................................................. 98
15.
64KHZ SYNCHRONIZATION INTERFACE
............................................................ 99
15.1
R
ECEIVE
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
...................................................... 99
15.2
T
RANSMIT
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.................................................. 100
16.
6312KHZ SYNCHRONIZATION INTERFACE
..................................................... 101
16.1
R
ECEIVE
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
................................................ 101
16.2
T
RANSMIT
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.............................................. 101
17.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
.............. 102
17.1
I
NSTRUCTION
R
EGISTER
......................................................................................................... 106
17.2
T
EST
R
EGISTERS
................................................................................................................... 107
17.3
B
OUNDARY
S
CAN
R
EGISTER
.................................................................................................. 107
17.4
B
YPASS
R
EGISTER
................................................................................................................. 107
DS26504 T1/E1/J1/64KCC BITS Element
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17.5
I
DENTIFICATION
R
EGISTER
..................................................................................................... 107
18.
FUNCTIONAL TIMING DIAGRAMS
......................................................................... 110
18.1
P
ROCESSOR
I
NTERFACE
........................................................................................................ 110
18.1.1
Parallel Port Mode.............................................................................................................................. 110
18.1.2
SPI Serial Port Mode.......................................................................................................................... 110
19.
OPERATING PARAMETERS
..................................................................................... 113
20.
AC TIMING PARAMETERS AND DIAGRAMS
.................................................... 115
20.1
M
ULTIPLEXED
B
US
................................................................................................................. 115
20.2
N
ONMULTIPLEXED
B
US
.......................................................................................................... 118
20.3
S
ERIAL
B
US
........................................................................................................................... 121
20.4
R
ECEIVE
S
IDE
AC C
HARACTERISTICS
..................................................................................... 123
20.5
T
RANSMIT
S
IDE
AC C
HARACTERISTICS
................................................................................... 125
21.
REVISION HISTORY
...................................................................................................... 127
22.
PACKAGE INFORMATION
......................................................................................... 128
DS26504 T1/E1/J1/64KCC BITS Element
5 of 128
LIST OF FIGURES
Figure 3-1. Block Diagram ......................................................................................................................................... 11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ......................................................................................... 12
Figure 3-3. Transmit PLL Clock Mux Diagram .......................................................................................................... 12
Figure 3-4. Master Clock PLL Diagram ..................................................................................................................... 13
Figure 13-1. Basic Network Connection .................................................................................................................... 79
Figure 13-2. Typical Monitor Application ................................................................................................................... 81
Figure 13-3. CMI Coding ........................................................................................................................................... 83
Figure 13-4. Basic Interface....................................................................................................................................... 92
Figure 13-5. Protected Interface Using Internal Receive Termination ...................................................................... 93
Figure 13-6. E1 Transmit Pulse Template................................................................................................................. 95
Figure 13-7. T1 Transmit Pulse Template ................................................................................................................. 95
Figure 13-8. Jitter Tolerance (T1 Mode) .................................................................................................................... 96
Figure 13-9. Jitter Tolerance (E1 Mode).................................................................................................................... 96
Figure 13-10. Jitter Attenuation (T1 Mode)................................................................................................................ 97
Figure 13-11. Jitter Attenuation (E1 Mode) ............................................................................................................... 97
Figure 15-1. 64kHz Composite Clock Mode Signal Format ...................................................................................... 99
Figure 17-1. JTAG Functional Block Diagram ......................................................................................................... 102
Figure 17-2. TAP Controller State Diagram............................................................................................................. 105
Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 ............................................................... 110
Figure 18-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0 ............................................................... 110
Figure 18-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1 ............................................................... 110
Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 ............................................................... 111
Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 ............................................................... 111
Figure 18-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0 ............................................................... 111
Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 ............................................................... 112
Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 ............................................................... 112
Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) ............................................................................... 116
Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ................................................................................ 116
Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00)................................................................................... 117
Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 119
Figure 20-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01) ................................................................................ 119
Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 120
Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01) ......................................................................... 120
Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10.................................................................... 122
Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10.................................................................... 122
Figure 20-10. Receive Timing--T1, E1, 64KCC Mode............................................................................................ 124
Figure 20-11. Transmit Timing--T1, E1, 64KCC Mode........................................................................................... 126
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