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091405
FEATURES
16-Bit Bidirectional Current Measurement
1.56
mV LSB, 51.2mV Dynamic Range
104
mA LSB, 3.4A Dynamic Range (RSNS =
15m
W)
Current Accumulation Register Resolution
6.25
mVhr LSB, 204.8mVh Range
0.417mAhr LSB, 13.65Ah Range
(R
SNS
= 15m
W)
11-Bit Voltage Measurement
4.88mV LSB, 0V to 5V Input Range
11-Bit Temperature Measurement
0.125C Resolution, -20C to +70C
Industry Standard I
2
C* Interface
Low Power Consumption:
Active Current:
70
mA typical, 100mA max
Sleep Current:
1
mA typical, 3mA max
BLOCK DIAGRAM
VDD
VIN
SCL
SNS
VSS
SDA
Sense
DS2745
Li+
Protector
Fuel Gauge
Algorithm
P
PACK-
COMM
PACK+
PIN CONFIGURATION
DESCRIPTION
The DS2745 provides current-flow, voltage, and
temperature measurement data to support battery-
capacity monitoring in cost-sensitive applications. The
DS2745 can be mounted on either the host side or
pack side of the application. Current measurement
and coulomb counting is accomplished by monitoring
the voltage drop across an external sense resistor,
voltage measurement is accomplished through a
separate voltage-sense input, and temperature
measurement takes place on-chip. A standard I
2
C
interface with software programmable address gives
the controlling microprocessor access to all data and
status registers inside the DS2745. A low-power sleep
mode state conserves energy when the cell pack is in
storage.
APPLICATIONS
Cellular
GPS
PDAs
Handheld Products
Table 1.
ORDERING INFORMATION
PART MARKING
PIN-PACKAGE
DS2745U+
2745
mMAX package
DS2745U+/T&R
2745
DS2745U+ in Tape-and-Reel
+Denotes lead-free package.
*I
2
C is a trademark of Philips Corp. Purchase of I
2
C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated
Companies, conveys a license under the Philips I
2
C Patent Rights to use these components in an I
2
C system, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
DS2745
Low-Cost I
2
C Battery Monitor
www.maxim-ic.com
mMAX
SDA
VDD
VIN
CTG
VSS
SNS
PIO
SCL
6
8
7
5
3
1
2
4
See Table 1 for Ordering Information.
DS2745 Low-Cost I
2
C Battery Monitor
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ABSOLUTE MAXIMUM RATINGS*
Voltage on All Pins Relative to V
SS
-0.3V to +6V
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-55C to +125C
Soldering Temperature
See IPC/JEDECJ-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(2.5V
V
DD
5.5V; T
A
= 0
C to +70C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
UNITS
Supply Voltage
V
DD
(Note
1)
2.5
5.5
V
Serial Data I/O Pin
SDA
(Note 1)
-0.3
+5.5
V
Serial Clock Pin
SCL
(Note 1)
-0.3
+5.5
V
Programmable I/O Pin
PIO
(Note 1)
-0.3
+5.5
V
VIN Pin
V
IN
(Note
1)
-0.3 V
DD
+0.3
V
DC ELECTRICAL CHARACTERISTICS
(2.5V
V
DD
4.5V; T
A
= 0
C to +70C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP
MAX
UNITS
70
100
Active Current
I
ACTIVE
V
DD
= 5.5V
105
mA
Sleep-Mode Current
I
SLEEP
SCL = SDA = V
SS
,
PIO = V
SS
1 3 mA
Current Resolution
I
LSB
1.56 mV/R
Current Full-Scale
Magnitude
I
FS
(Note
1)
51.2 mV/R
Current Offset
I
OERR
(Note 2)
- 7.82
+ 12.5
mV/R
Current Gain Error
I
GERR
-
1.0
+1.0
% of
reading
Accumulated Current
Resolution
q
CA
6.25 mVh/R
Accumulated Current
Offset
q
OERR
V
SNS
= V
SS
, (Notes 4, 5)
- 188
+ 0
Vh/R
per day
Voltage Resolution
V
LSB
4.88
mV
Voltage Full-Scale
V
FS
0
4.992 V
Voltage Error
V
GERR
(Note 12)
- 25
+ 25
mV
Temperature Resolution
T
LSB
0.125 C
Temperature Error
T
ERR
- 3
+ 3
C
Current Sample Clock
Frequency
f
SAMP
18.6
kHz
Timebase Accuracy
t
ERR
V
DD
= 3.8V, T
A
= +25C
1
%
DS2745 Low-Cost I
2
C Battery Monitor
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2
-20C T
A
+70C,
2.5V V
DD
5.5V
3
Input Resistance, VIN
R
IN
15
MW
Input Logic High:
SCL, SDA
V
IH
(Note
1)
1.5
V
Input Logic Low:
SCL, SDA
V
IL
(Note
1)
0.6 V
Output Logic Low:
SDA, PIO
V
OL
I
OL
= 4mA (Note 1)
0.4
V
Pulldown Current: SCL,
SDA
I
PD
0.25
mA
Input Capacitance: SCL,
SDA
C
BUS
50
pF
SLEEP Timeout
t
SLEEP
(Note 3)
2.2 S
Input Logic High:
PIO
V
IH
(Note
1)
V
DD
x 0.7
V
Input Logic Low:
PIO
V
IL
(Note
1)
V
DD
x 0.3
V
2-WIRE INTERFACE TIMING SPECIFICATIONS
(V
DD
= 2.5V to 5.5V, T
A
= -20
C to +70C.)
PARAMETER SYMBOL CONDITIONS MIN TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 6)
0
400
KHz
Bus Free Time Between a
STOP and START Condition
tBUF
1.3
s
Hold Time (Repeated)
START Condition
tHD:STA
(Note 7)
0.6
s
Low Period of SCL Clock
tLOW
1.3
s
High Period of SCL Clock
tHIGH
0.6
s
Setup Time for a Repeated
START Condition
tSU:STA
0.6
s
Data Hold Time
tHD:DAT
(Note 8, 9)
0
0.9
s
Data Setup Time
tSU:DAT
(Note 8)
100
ns
Rise Time of Both SDA and
SCL Signals
tR
20 + 0.1C
B
300 ns
Fall Time of Both SDA and
SCL Signals
tF
20 + 0.1C
B
300 ns
Setup Time for STOP
Condition
tSU:STO
0.6
s
Spike Pulse Widths
Suppressed by Input Filter
tSP
(Note 10)
0
50
ns
Capacitive Load for Each
Bus
Line
CB
(Note 11)
400
pF
SCL, SDA Input
Capacitance
C
BIN
60
pF
DS2745 Low-Cost I
2
C Battery Monitor
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Note 1:
All voltages are referenced to V
SS
.
Note 2:
Offset specified after auto-calibration cycle and Current Offset Bias register (COBR) set to 00h.
Note 3:
To properly enter sleep mode, SMOD=1, and the application should hold SDA and SCL low for longer
than the maximum t
SLEEP
.
Note 4:
NBEN = 0, Current Offset Bias Register (COBR) set to 00h, and Accumulation Bias Register (ABR)
set to 00h.
Note 5:
Parameters guaranteed by design.
Note 6:
Timing must be fast enough to prevent the DS2745 from entering sleep mode due to SDA,SCL low
for period >
t
SLEEP
.
Note 7:
f
SCL
must meet the minimum clock low time plus the rise/fall times.
Note 8:
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL
signal.
Note 9:
This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the
VIHmin of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10:
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 11:
C
B
total capacitance of one bus line in pF.
Note 12:
The first voltage measurement after writing the ACR or after device POR is not valid.
Figure 1. I
2
C Bus Timing Diagram
SDA
SCL
t
F
t
R
t
SU;DAT
t
LOW
S
t
HD;STA
t
HD;DAT
t
F
t
SU;STA
t
HD;STA
t
SU;STO
t
R
t
BUF
t
SP
Sr
P
S
DS2745 Low-Cost I
2
C Battery Monitor
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PIN DESCRIPTION
PIN SYMBOL
FUNCTION
1
SCL
Serial Clock Input. 2-Wire clock line. Input only. Connect this pin to the CLOCK
terminal of the battery pack. Pin has an internal pulldown (I
PD
) for sensing
disconnection.
2
SDA
Serial Data Input/Output. 2-Wire data line. Open-drain output driver. Connect this pin
to the DATA terminal of the battery pack. Pin has an internal pulldown (I
PD
) for sensing
disconnection.
3
PIO
General Purpose Input/Output. Open-drain output driver with input sense. Connect
to a pull up resistor for bidirectional operation.
4
SNS
Sense Resistor Connection. Connect to the negative terminal of the battery pack.
Connect the sense resistor between V
SS
and SNS.
5 V
SS
Device Ground. Connect to the negative terminal of the Li+ cell outside the cell
protection FETs. Connect the sense resistor between V
SS
and SNS.
6
CTG
Connect to Ground. Connect to the negative terminal of the Li+ cell outside the cell
protection FETs.
7
VIN
Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin.
8 V
DD
Power-Supply Input. Connect to the positive terminal of the Li+ cell through a
decoupling network.
Figure 2. BLOCK DIAGRAM
2-WIRE
INTERFACE
VOLTAGE
REFERENCE
THERMAL
SENSE
ADC1
SCL
VIN
TIMEBASE
M
U
X
S
+
-
TEMPERATURE
VOLTAGE
CURRENT
ACR
STATUS
chip
ground
SNS
VSS
VDD
BIAS
1k
W
1k
W
SDA
ADC2
PIO
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