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REV: 111703

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS2762 high-precision Li+ battery monitor is a
data-acquisition, information-storage, and safety-
protection device tailored for cost-sensitive battery
pack applications. This low-power device integrates
precise temperature, voltage, and current
measurement, nonvolatile (NV) data storage, and Li+
protection into the small footprint of either a TSSOP
package or flip-chip package. The DS2762 is a key
component in applications including remaining
capacity estimation, safety monitoring, and battery-
specific data storage.

PIN CONFIGURATIONS

FEATURES

§ Li+ Safety Circuit

Overvoltage Protection
Overcurrent/Short-Circuit Protection
Undervoltage Protection

§ Host Alerted When Accumulated Current or

Temperature Exceeds User-Selectable Limits

§ 0V Battery Recovery Charge
§ Available in Two Configurations:

Internal 25m

W Sense Resistor

External User-Selectable Sense Resistor

§ Current Measurement

12-Bit Bidirectional Measurement
Internal Sense Resistor Configuration:

0.625mA LSB and ±1.9A Dynamic Range

External Sense Resistor Configuration:

15.625

mV LSB and ±64mV Dynamic Range

§ Current Accumulation:

Internal Sense Resistor: 0.25mAhr LSB
External Sense Resistor: 6.25

mVhr LSB

§ Voltage Measurement with 4.88mV Resolution
§ Temperature Measurement Using Integrated

Sensor with 0.125°C Resolution

§ System Power Management and Control

Feature Support

§ 32 Bytes of Lockable EEPROM
§ 16 Bytes of General-Purpose SRAM
§ Dallas 1-Wire

Interface with Unique 64-Bit

Device Address

§ Low-Power Consumption:

Active Current: 60

mA typ, 90mA max

Sleep Current: 1

mA typ, 2mA max

APPLICATIONS

PDAs
Cell Phones/Smartphones
Digital Cameras

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

DS2762BE

-20°C to +70°C

16 TSSOP

Selector Guide appears at end of data sheet, for additional
options.

DS2762

High-Precision Li+ Battery Monitor With Alerts

www.maxim-ic.com

TOP VIEW

PIO

IS1

TSSOP

IS2

SNS

2
3

SNS

PLS

1-Wire is registered trademark of Dallas Semiconductor.

FLIP CHIP

(top view bumps on bottom)

PLS

DC DQ

CC IS2

IS1

PIO

SNS

1 2 3 4

A
B

E
F

SNS
PROBE

PROBE

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on PLS and

CC Pin, Relative to V

-0.3V to +18V

Voltage Range on PIO Pin, Relative to V

-0.3V to +12V

Voltage Range on Any Other Pin, Relative to V

-0.3V to +6V

Continuous Internal Sense Resistor Current

±2.5A

Pulsed Internal Sense Resistor Current

±50A for <100µs/s, <1000 pulses

Operating Temperature Range

-40°C to +85°C

Storage Temperature Range

-55°C to +125°C

Soldering Temperature

See IPC/JEDEC J-STD-020A Specification

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

RECOMMENDED DC OPERATING CONDITIONS

(2.5V

£ V

£ 5.5V, T

= -20°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

(Note 1)

2.5

5.5

Data Pin

(Note 1)

-0.3

+5.5

DC ELECTRICAL CHARACTERISTICS

(2.5V

£ V

£ 5.5V, T

= -20°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Active Current

ACTIVE

DQ = V

, normal operation

Sleep Mode Current

SLEEP

DQ = 0V, no activity,

PS floating

Input Logic High: DQ, PIO

(Note 1)

1.5

Input Logic High:

(Note 1)

- 0.2V

Input Logic Low: DQ, PIO

(Note 1)

0.4

Input Logic Low:

(Note 1)

0.2

Output Logic High:

= -0.1mA (Note 1)

PLS

- 0.4V

Output Logic High:

= -0.1mA (Note 1)

- 0.4V

Output Logic Low:

CC, DC

= 0.1mA (Note 1)

0.4

Output Logic Low: DQ, PIO

= 4mA (Note 1)

0.4

DQ Pulldown Current

Input Resistance: V

Internal Current-Sense Resistor

SNS

+25°C

DQ Low to Sleep time

SLEEP

2.1

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ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY

(2.5V

£ V

£ 5.5V, T

= 0°C to +50°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

4.325

4.350

4.375

Overvoltage Detect

(Notes 1, 2)

4.250

4.275

4.300

Charge Enable

(Note 1)

4.10

4.15

4.20

Undervoltage Detect

(Note 1)

2.5

2.6

2.7

Overcurrent Detect

(Note 3)

1.8

1.9

2.0

Overcurrent Detect

(Note 1, 4)

47.5

Short-Circuit Detect

(Note 3)

5.0

8.0

Short-Circuit Detect

(Note 1)

150

200

250

Overvoltage Delay

OVD

0.8

1.2

Undervoltage Delay

UVD

100

110

Overcurrent Delay

OCD

Short-Circuit Delay

SCD

160

200

240

Test Threshold

0.5

1.0

1.5

Test Current

TST

Recovery Charge Current

(Note 5)

0.5

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ELECTRICAL CHARACTERISTICS: TEMPERATURE, VOLTAGE, CURRENT

(2.5V

£ V

£ 5.5V, T

= -20°C to +50°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Temperature Resolution

LSB

0.125

°C

Temperature Full-Scale Magnitude

127

°C

Temperature Error

ERR

(Note 6)

±3

°C

Voltage Resolution

LSB

4.88

Voltage Full-Scale Magnitude

4.75

Voltage Offset Error

OERR

(Note 7)

LSB

Voltage Gain Error

GERR

(Note 3)

0.625

Current Resolution

LSB

(Note 4)

15.625

(Notes 3, 4)

1.9

2.56

Current Full-Scale Magnitude

(Note 8)

Current Offset Error

OERR

(Note 9)

LSB

(Notes 3, 10)

Current Gain Error

GERR

(Note 4)

(Note 3)

0.25

mAhr

Accumulated Current Resolution

(Note 4)

6.25

µVhr

Current Sampling Frequency

SAMP

1456

ERR1

(Note 11)

±1

±3

Internal Timebase Accuracy

ERR2

(Note 11)

±6.5

EEPROM RELIABILITY SPECIFICATION

(2.5V

£ V

£ 5.5V, T

= -20

°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Copy to EEPROM Time

EEC

EEPROM Copy Endurance

EEC

(Note 12)

25,000

cycles

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ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE

(2.5V

£ V

£ 5.5V, T

= -20

°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Time Slot

SLOT

120

Recovery Time

REC

Write 0 Low Time

LOW0

120

Write 1 Low Time

LOW1

Read Data Valid

RDV

Reset Time High

RSTH

480

Reset Time Low

RSTL

480

960

Presence Detect High

PDH

Presence Detect Low

PDL

240

SWAP Timing Pulse Width

SWL

0.2

120

SWAP Timing Pulse Falling Edge to

Release

SWOFF

(Note 13)

SWAP Timing Pulse Rising Edge to

Engage

SWON

(Note 13)

DQ Capacitance

Note 1:

All voltages are referenced to V

Note 2:

See the Selector Guide section to determine the corresponding part number for each V

value.

Note 3:

Internal current-sense resistor configuration.

Note 4:

External current-sense resistor configuration.

Note 5:

Test conditions are PLS = 4.1V, V

= 2.5V. Maximum current for conditions of PLS = 15V, V

= 0V is 10mA.

Note 6:

Self-heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions.

Note 7:

Voltage offset measurement is with respect to V

at +25°C.

Note 8:

The current register supports measurement magnitudes up to 2.56A using the internal sense resistor option and 64mV with the
external resistor option. Compensation of the internal sense resistor value for process and temperature variation can reduce the
maximum reportable magnitude to 1.9A.

Note 9:

Current offset error null to ±1LSB typically requires 3.5s in-system calibration by user.

Note 10:

Current gain error specification applies to gain error in converting the voltage difference at IS1 and IS2, and excludes any error
remaining after the DS2762 compensates for the internal sense resistor's temperature coefficient of 3700ppm/

°C to an accuracy

±500ppm/°C. The DS2762 does not compensate for external sense resistor characteristics, and any error terms arising from

the use of an external sense resistor should be taken into account when calculating total current measurement error.

Note 11:

Typical value for t

ERR1

is specified at 3.6V and +25

°C, max value is specified for 0°C to +50°C. Max value for t

ERR2

is specified

for -20°C to +70°C.

Note 12:

Four-year data retention at +70

°C.

Note 13:

Typical load capacitance on

DC and CC is 1000pF.

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PIN DESCRIPTION

PIN

TSSOP

FLIP

CHIP

SYMBOL

FUNCTION

Charge Protection Control Output. Controls an external P-channel high-side charge
protection FET.

PLS

Battery Pack Positive Terminal Input. The DS2762 monitors the pack plus terminal
through PLS to detect overcurrent and overload conditions, as well as the presence of a
charge source. Additionally, a charge path to recover a deeply depleted cell is provided
from PLS to V

. In sleep mode (with SWEN = 0), any capacitance or voltage source

connected to PLS is discharged internally to V

through 200µA (nominal) to assure

reliable detection of a valid charge source. For details of other internal connections to
PLS and associated conditions see the Li+ Protection Circuitry section.

Discharge Protection Control Output. Controls an external P-channel high-side
discharge protection FET.

4, 5, 6

SNS

Sense Resistor Connection. Connect to the negative terminal of the battery pack. In
the internal sense resistor configuration, the sense resistor is connected between V

and SNS.

Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the DATA
terminal of the battery pack. Pin has an internal 1

mA pulldown for sensing disconnection.

IS2

Current-Sense Input. This pin is internally connected to SNS through a 4.7k

W resistor.

IS1

Current-Sense Input. This pin is internally connected to V

through a 4.7k

W resistor.

Connect a 0.1

mF capacitor between IS1 and IS2 to complete a lowpass input filter.

Power Switch Sense Input. The device wakes up from sleep mode when it senses the
closure of a switch to V

on this pin. Pin has an internal 1

mA pullup to V

11, 12, 13

Device Ground. Connect directly to the negative terminal of the Li+ cell. For the external
sense resistor configuration, connect the sense resistor between V

and SNS.

PIO

Programmable I/O Pin. Can be configured to be used to control and monitor user-
defined external circuitry or as an interrupt output to alert the host when preset current
accumulator or temperature limits are exceeded. Open drain to V

Power-Supply Input. Connect to the positive terminal of the Li+ cell through a
decoupling network.

Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin. This
pin has a weak pullup to V

SNS

Probe

Do not connect.

Probe

Do not connect.

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Figure 1. Block Diagram

DETAILED DESCRIPTION

The DS2762 high-precision Li+ battery monitor is a data-acquisition, information-storage, and safety-protection
device tailored for cost-sensitive battery pack applications. This low-power device integrates precise temperature,
voltage, and current measurement, nonvolatile (NV) data storage, and Li+ protection into the small footprint of
either a TSSOP package or flip-chip package. The DS2762 is a key component in applications including remaining
capacity estimation, safety monitoring, and battery-specific data storage.

Through its 1-Wire interface, the DS2762 gives the host system read/write access to status and control registers,
instrumentation registers, and general-purpose data storage. Each device has a unique factory-programmed 64-bit
net address that allows it to be individually addressed by the host system, supporting multibattery operation.

The DS2762 is capable of performing temperature, voltage, and current measurement to a resolution sufficient to
support process monitoring applications such as battery charge control, remaining capacity estimation, and safety
monitoring. Temperature is measured using an on-chip sensor, eliminating the need for a separate thermistor.
Bidirectional current measurement and accumulation are accomplished using either an internal 25m

W sense

resistor or an external device. The DS2762 also features a programmable I/O pin that allows the host system to
sense and control other electronics in the pack, including switches, vibration motors, speakers, and LEDs. This pin
may also be used to alert the host when preset accumulated current or temperature limits are exceeded.

Three types of memory are provided on the DS2762 for battery information storage: EEPROM, lockable EEPROM,
and SRAM. EEPROM memory saves important battery data in true NV memory that is unaffected by severe battery
depletion, accidental shorts, or ESD events. Lockable EEPROM becomes ROM when locked to provide additional
security for unchanging battery data. SRAM provides inexpensive storage for temporary data.

1-Wire

INTERFACE

AND

ADDRESS

THERMAL

SENSE

MUX

VOLTAGE

REFERENCE

ADC

REGISTERS AND

USER MEMORY

25m

CHIP GROUND

LOCKABLE EEPROM

SRAM

TEMPERATURE

VOLTAGE

CURRENT

ACCUM. CURRENT

STATUS/CONTROL

Li+ PROTECTION

IS1

IS2

SNS

IS2

IS1

CC
DC

PLS

PIO

TIMEBASE

INTERNAL SENSE RESISTOR

CONFIGURATION ONLY

DS2762

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POWER MODES

The DS2762 has two power modes: active and sleep. While in active mode, the DS2762 continually measures
current, voltage, and temperature to provide data to the host system and to support current accumulation and Li+
safety monitoring. In sleep mode, the DS2762 ceases these activities. The DS2762 enters sleep mode when any of
the following conditions occurs:

§ The PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than 2s (pack

disconnection).

§ The voltage on V

drops below undervoltage threshold V

for t

UVD

(cell depletion).

§ The pack is disabled through the issuance of a SWAP command (SWEN bit = 1).

The DS2762 returns to active mode when any of the following occurs:

§ The PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high (pack

connection).

§ The

PS pin is pulled low (power switch).

§ The voltage on PLS becomes greater than the voltage on V

(charger connection) with the SWEN bit set to 0.

§ The pack is enabled through the issuance of a SWAP command (SWEN bit = 1).

The DS2762 defaults to active mode when power is first applied.

Li+ PROTECTION CIRCUITRY

During active mode, the DS2762 constantly monitors cell voltage and current to protect the battery from overcharge
(overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents (overcurrent, short
circuit). Conditions and DS2762 responses are described in the following sections and summarized in Table 1 and
Figure 3.

Table 1. Li+ Protection Conditions and DS2762 Responses

ACTIVATION

CONDITION

THRESHOLD

DELAY

RESPONSE

RELEASE THRESHOLD

Overvoltage

> V

OVD

CC high

< V

, or

-2mV

Undervoltage

< V

UVD

CC, DC high,

Sleep Mode

PLS

> V

(1)

(charger connected)

Overcurrent, Charge

> V

(2)

OCD

CC, DC high

PLS

< V

- V

(3)

Overcurrent, Discharge

< -V

(2)

OCD

DC high

PLS

> V

- V

(4)

Short Circuit

SNS

> V

SCD

DC high

PLS

> V

- V

(4)

= V

IS1

- V

IS2

. Logic high = V

PLS

for

CC and V

for

All voltages are with respect to V

. I

SNS

references current delivered from pin SNS.

Note 1:

If V

< 2.2V, release is delayed until the recovery charge current (I

) passed from PLS to V

charges the battery and allows V

to exceed 2.2V.

Note 2:

For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: I

SNS

> I

for charge

direction and I

SNS

< -I

for discharge direction.

Note 3:

With test current I

TST

flowing from PLS to V

(pulldown on PLS).

Note 4:

With test current I

TST

flowing from V

to PLS (pullup on PLS).

Overvoltage. If the cell voltage on V

exceeds the overvoltage threshold, V

, for a period longer than overvoltage

delay, t

OVD

, the DS2762 shuts off the external charge FET and sets the OV flag in the protection register. When the

cell voltage falls below charge enable threshold V

, the DS2762 turns the charge FET back on (unless another

protection condition prevents it). Discharging remains enabled during overvoltage, and the DS2762 re-enables the
charge FET before V

< V

if a discharge current of -80mA (V

-2mV) or less is detected.

Undervoltage. If the voltage of the cell drops below undervoltage threshold, V

, for a period longer than

undervoltage delay, t

UVD

, the DS2762 shuts off the charge and discharge FETs, sets the UV flag in the protection

DS2762 High-Precision Li+ Battery Monitor With Alerts

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) recovery charge path from PLS to

to gently charge severely depleted cells. The recovery path is enabled when 0

£ V

< 3V (typ). Once V

reaches 3V (typ), the DS2762 returns to normal operation, awaiting connection of a charger to turn on the charge
FET and pull out of sleep mode.

Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (V

= V

IS1

IS2

) is the

filtered voltage drop across the current-sense resistor. If V

exceeds overcurrent threshold V

for a period longer

than overcurrent delay t

OCD

, the DS2762 shuts off both external FETs and sets the COC flag in the protection

- V

. The

DS2762 provides a test current of value I

TST

from PLS to V

to pull PLS down to detect the removal of the

offending charge current source.

Overcurrent, Discharge Direction. If V

is less than -V

for a period longer than t

OCD

, the DS2762 shuts off the

external discharge FET and sets the DOC flag in the protection register. The discharge current path is not re-
established until the voltage on PLS rises above V

- V

. The DS2762 provides a test current of value I

TST

from

to PLS to pull PLS up to detect the removal of the offending low-impedance load.

Short Circuit. If the voltage on the SNS pin with respect to V

exceeds short-circuit threshold V

for a period

longer than short-circuit delay t

SCD

, the DS2762 shuts off the external discharge FET and sets the DOC flag in the

protection register. The discharge current path is not re-established until the voltage on PLS rises above V

- V

The DS2762 provides a test current of value I

TST

from V

to PLS to pull PLS up to detect the removal of the short

circuit.

Figure 3. Li+ Protection Circuitry Example Waveforms

Summary. All of the protection conditions described above are ORed together to affect the

CC and DC outputs.

DC = (Undervoltage) or (Overcurrent, Either Direction) or (Short Circuit) or (Protection Register Bit DE = 0)

or (Sleep Mode)

CC = (Overvoltage) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register bit CE = 0)

or (Sleep Mode)

SLEEP

MODE

CELL

CHARGE

DISCHARGE

-V

SCD

OCD

UVD

OVD

PLS

ACTIVE

INACTIVE

OVD

(NOTE 1)

NOTE 1: TO ALLOW THE DEVICE TO REACT QUICKLY TO SHORT CIRCUITS, DETECTION OCCURS ON THE SNS PIN RATHER THAN ON THE
FILTERED IS1 AND IS2 PINS. THE ACTUAL SHORT-CIRCUIT DETECT CONDITION IS V

SNS

> V

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CURRENT MEASUREMENT

In active mode, the DS2762 continually measures the current flow into and out of the battery by measuring the
voltage drop across a current-sense resistor. The DS2762 is available in two configurations: 1) internal 25m

current-sense resistor and 2) external user-selectable sense resistor. In either configuration, the DS2762 considers
the voltage difference between pins IS1 and IS2 (V

= V

IS1

- V

IS2

) to be the filtered voltage drop across the sense

resistor. A positive V

value indicates current is flowing into the battery (charging), while a negative V

value

indicates current is flowing out of the battery (discharging).

is measured with a signed resolution of 12 bits. The current register is updated in two's-complement format

every 88ms with an average of 128 readings. Currents outside the register range are reported at the range limit.
Figure 4 shows the format of the current register.

For the internal sense resistor configuration, the DS2762 maintains the current register in units of amps, with a
resolution of 0.625mA and full-scale range of no less than

±1.9A (see Note 7 on I

spec for more details). The

DS2762 automatically compensates for internal sense resistor process variations and temperature effects when
reporting current.

For the external sense resistor configuration, the DS2762 writes the measured V

voltage to the current register,

with a 15.625

mV resolution and a full-scale ±64mV range.

Figure 4. Current Register Format

MSB--Address 0E

LSB--Address 0F

MSb

LSb

MSb

LSb

Units: 0.625mA for Internal Sense Resistor

15.625

mV for External Sense Resistor

CURRENT ACCUMULATOR

The current accumulator facilitates remaining capacity estimation by tracking the net current flow into and out of the
battery. Current flow into the battery increments the current accumulator while current flow out of the battery
decrements it. Data is maintained in the current accumulator in two's-complement format. Figure 5 shows the
format of the current accumulator.

When the internal sense resistor is used, the DS2762 maintains the current accumulator in units of amp-hours, with
a 0.25mAhrs resolution and full-scale

±8.2Ahrs range. When using an external sense resistor, the DS2762

maintains the current accumulator in units of volt-hours, with a 6.25

mVhrs resolution and a full-scale ±205mVhrs

range.

The current accumulator is a read/write register that can be altered by the host system as needed.

Figure 5.

Current Accumulator Format

MSB--Address 10

LSB--Address 11

MSb

LSb

MSb

LSb

Units: 0.25mAhrs for Internal Sense Resistor

6.25

mVhrs for External Sense Resistor

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CURRENT OFFSET COMPENSATION

Current measurement and current accumulation are internally compensated for offset on a continual basis
minimizing error resulting from variations in device temperature and voltage. Additionally, a constant bias can be
used to alter any other sources of offset. This bias resides in EEPROM address 33h in two's-complement format
and is subtracted from each current measurement. The current offset bias is applied to the internal and external
sense resistor configurations. The factory default for the current offset bias is 0.

Figure 6. Current Offset Bias

Address 33

MSb

LSb

Units: 0.625mA for Internal Sense Resistor

15.625

mV for External Sense Resistor

VOLTAGE MEASUREMENT

The DS2762 continually measures the voltage between pins V

and V

over a 0 to 4.75V range. The voltage

register is updated in two's-complement format every 3.4ms with a 4.88mV resolution. Voltages above the
maximum register value are reported as the maximum value. Figure 7 shows the voltage register format.

Figure 7. Voltage Register Format

MSB--Address 0C

LSB--Address 0D

MSb

LSb

MSb

LSb

Units: 4.88mV

TEMPERATURE MEASUREMENT

The DS2762 uses an integrated temperature sensor to continually measure battery temperature. Temperature
measurements are placed in the temperature register every 220ms in two's-complement format with a 0.125°C
resolution over a

±127°C range. Figure 8 shows the temperature register format.

Figure 8. Temperature Register Format

MSB--Address 18

LSB--Address 19

MSb

LSb

MSb

LSb

Units: 0.125

°C

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PROGRAMMABLE I/O

To use the PIO pin as described in this section, the IE bit (bit 2) of the Status Register must be set to 0.

To use the PIO pin as an output, write the desired output value to the PIO bit in the special feature register. Writing
a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to V

. Writing a 1 to the PIO bit disables the

output driver, allowing the PIO pin to be pulled high or used as an input. To sense the value on the PIO pin, read
the PIO bit. The DS2762 turns off the PIO output driver and sets the PIO bit high when in sleep mode or when DQ
is low for more than 2s, regardless of the state of the PMOD bit.

ALARM COMPARATORS

The PIO pin can be programmed as an interrupt output (active low) to alert the host system of critical events. To
use the Interrupt feature, the Interrupt Enable (IE) bit (bit 2) of the Status Register must be set to a 1. Interrupt
threshold values can be programmed by the user in the designated SRAM memory registers in the formats and
locations found in Figure 9. Since these thresholds are located in SRAM memory, they must be reprogrammed if a
loss of power to the DS2762 occurs. The PIO line will go low to interrupt the system host and indicate that one of
the following events has occurred:

· Accumulated

Current

³ Current Accumulator Interrupt High Threshold

· Accumulated

Current

£ Current Accumulator Interrupt Low Threshold

· Temperature

³ Temperature Interrupt High Threshold

· Temperature

£ Temperature Interrupt Low Threshold

The host may then poll the DS2762 to determine which threshold has been met or exceeded.

Figure 9. Interrupt Threshold Register Formats

Current Accumulator Interrupt High Threshold

MSB--Address 80

LSB--Address 81

MSb

LSb

MSb

LSb

Units: 0.25mAhrs for Internal Sense Resistor

6.25

mVhrs for External Sense Resistor

Current Accumulator Interrupt Low Threshold

MSB--Address 82

LSB--Address 83

MSb

LSb

MSb

LSb

Units: 0.25mAhrs for Internal Sense Resistor

6.25

mVhrs for External Sense Resistor

DS2762 High-Precision Li+ Battery Monitor With Alerts

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Temperature Interrupt High Threshold

Address 84

MSb

LSb

Units: 1.0°C

Temperature Alarm Low Threshold

Address 85

MSb

LSb

Units: 1.0°C

POWER SWITCH INPUT

The DS2762 provides a power control function that uses the discharge protection FET to gate battery power to the
system. The

PS pin, internally pulled to V

through a 1

mA current source, is continuously monitored for a low-

impedance connection to V

. If the DS2762 is in sleep mode, the detection of a low on the

PS pin causes the

device to transition into active mode, turning on the discharge FET. If the DS2762 is already in active mode, activity
on

PS has no effect other than the latching of its logic low level in the PS bit in the special feature register. The

reading of a 0 in the

PS bit should be immediately followed by writing a 1 to the PS bit to ensure that a subsequent

low forced on the

PS pin is latched into the PS bit.

MEMORY

The DS2762 has a 256-byte linear address space with registers for instrumentation, status, and control in the lower
32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining address space. All
EEPROM memory is general purpose except addresses 30h, 31h, and 33h, which should be written with the
default values for the protection register, status register, and current offset register, respectively. All SRAM memory
is general purpose. When the MSB of any two-byte register is read, both the MSB and LSB are latched and held for
the duration of the read data command to prevent updates during the read and ensure synchronization between
the two register bytes. For consistent results, always read the MSB and the LSB of a two-byte register during the
same read data command sequence.

EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to
be verified by the host system before being copied to EEPROM. All reads and writes to/from EEPROM memory
actually access the shadow RAM. In unlocked EEPROM blocks, the write data command updates shadow RAM. In
locked EEPROM blocks, the write data command is ignored. The copy data command copies the contents of
shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The recall-data
command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or
not.

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Table 2. Memory Map

ADDRESS (HEX)

DESCRIPTION

READ/WRITE

Protection Register

R/W

Status Register

0206

Reserved

EEPROM Register

R/W

Special Feature Register

R/W

090B

Reserved

Voltage Register MSB

Voltage Register LSB

Current Register MSB

Current Register LSB

Accumulated Current Register MSB

R/W

Accumulated Current Register LSB

R/W

1217

Reserved

Temperature Register MSB

Temperature Register LSB

1A1F

Reserved

202F

EEPROM, block 0

R/W*

303F

EEPROM, block 1

R/W*

407F

Reserved

SRAM (Optional Accumulated Current Interrupt
High Threshold MSB)

R/W

SRAM (Optional Accumulated Current Interrupt
High Threshold LSB)

R/W

SRAM (Optional Accumulated Current Interrupt
Low Threshold MSB)

R/W

SRAM (Optional Accumulated Current Interrupt
Low Threshold LSB)

R/W

SRAM (Optional Temperature Interrupt High
Threshold)

R/W

SRAM (Optional Temperature Interrupt Low
Threshold)

R/W

86-8F

SRAM

R/W

90FF

Reserved

* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.

PROTECTION REGISTER

The protection register consists of flags that indicate protection circuit status and switches that give conditional
control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when corresponding
protection conditions occur and remain set until cleared by the host system. The default values of the CE and DE
bits of the protection register are stored in lockable EEPROM in the corresponding bits in address 30h. A recall
data command for EEPROM block 1 recalls the default values into CE and DE. Figure 10 shows the format of the
protection register. The function of each bit is described in detail in the following paragraphs.

Figure 10. Protection Register Format

ADDRESS 00

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

COC

DOC

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OV--Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition.
This bit must be reset by the host system.

UV--Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an undervoltage
condition. This bit must be reset by the host system.

COC--Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a charge-
direction overcurrent condition. This bit must be reset by the host system.

DOC--Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a discharge-
direction overcurrent condition. This bit must be reset by the host system.

CC--CC Pin Mirror. This read-only bit mirrors the state of the CC output pin.

DC--DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.

CE--Charge Enable. Writing a 0 to this bit disables charging (

CC output high, external charge FET off) regardless

of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the presence of any
protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to active
mode.

DE--Discharge Enable. Writing a 0 to this bit disables discharging (

DC output high, external discharge FET off)

regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to override by the presence
of any protection conditions. The DS2762 automatically sets this bit to 1 when it transitions from sleep mode to
active mode.

STATUS REGISTER

The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of address
31h. A recall data command for EEPROM block 1 recalls the default values into the status register bits. The format
of the status register is shown in Figure 11. The function of each bit is described in detail in the following
paragraphs.

Figure 11. Status Register Format

ADDRESS 01

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PMOD

RNAOP

SWEN

X--Reserved Bits.

PMOD--Sleep Mode Enable. A value of 1 in this bit enables the DS2762 to enter sleep mode when the DQ line
goes low for greater than 2s and to leave sleep mode when the DQ line goes high. A value of 0 disables DQ-
related transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5
of address 31h. The factory default is 0.

RNAOP--Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address command to
33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should be set in bit 4 of
address 31h. The factory default is 0.

SWEN--SWAP Command Enable. A value of 1 in this bit location enables the recognition of a SWAP command. If
set to 0, SWAP commands are ignored. The desired default value should be set in bit 3 of address 31h. This bit is
read-only. The factory default is 0.

IE--Interrupt Enable. A value of 1 in this bit location enables the PIO pin to be used as an interrupt to the host
system when either the user-programmed thresholds for Accumulated Current and Temperature are met or
exceeded. If set to 0, the PIO pin performs as noted in the PIO section. This bit is read-only. The desired default
value should be set in bit 2 of address 31h. The factory default is 0.

DS2762 High-Precision Li+ Battery Monitor With Alerts

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EEPROM REGISTER

The format of the EEPROM register is shown in Figure 12. The function of each bit is described in detail in the
following paragraphs.

Figure 12. EEPROM Register Format

ADDRESS 07

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EEC

LOCK

BL1

BL0

EEC--EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress. While this
bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data may be written to unlocked
EEPROM blocks.

LOCK--EEPROM Lock Enable. When this bit is 0, the lock command is ignored. Writing a 1 to this bit enables the
lock command. After the lock command is executed, the LOCK bit is reset to 0. The factory default is 0.

BL1--EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 30 to 3F) is
locked (read-only) while a 0 indicates block 1 is unlocked (read/write).

BL0--EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20 to 2F) is
locked (read-only) while a 0 indicates block 0 is unlocked (read/write).

X--Reserved Bits.

SPECIAL FEATURE REGISTER

The format of the special feature register is shown in Figure 13. The function of each bit is described in detail in the
following paragraphs.

Figure 13. Special Feature Register Format

ADDRESS 08

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PIO

MSTR

PS--PS Pin Latch. This bit latches a low state on the PS pin, and is cleared only by writing a 1 to this location.
Writing this bit to a 1 immediately upon reading of a 0 value is recommended.

PIO--PIO Pin Sense and Control. See the Programmable I/O section for details on this read/write bit.

MSTR--SWAP Master Status Bit. This bit indicates whether a device has been selected through the SWAP
command. Selection of this device through the SWAP command and the appropriate net address results in setting
this bit, indicating that this device is the master. A 0 signifies that this device is not the master.

X--Reserved Bits.

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1-Wire BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus
with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2762 is a slave device.
The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of four
topics: 64-bit net address, hardware configuration, transaction sequence, and 1-Wire signaling.

64-BIT NET ADDRESS

Each DS2762 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first eight bits are
the 1-Wire family code (30h for DS2762). The next 48 bits are a unique serial number. The last eight bits are a
cyclic redundancy check (CRC) of the first 56 bits (see Figure 14). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2762 to communicate through the 1-Wire protocol detailed in the 1-Wire
Bus System section of this data sheet.

Figure 14. 1-Wire Net Address Format

8-BIT CRC

48-BIT SERIAL NUMBER

8-BIT FAMILY

CODE (30H)

MSb

LSb

CRC GENERATION

The DS2762 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure error-free
transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and
compare it to the CRC from the DS2762. The host system is responsible for verifying the CRC value and taking
action as a result. The DS2762 does not compare CRC values and does not prevent a command sequence from
proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a
very high level of integrity.

The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in
Figure 15, or it can be generated in software. Additional information about the Dallas 1-Wire CRC is available in
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch
Memory Products (

www.maxim-ic.com/appnoteindex

In the circuit in Figure 15, the shift register bits are initialized to 0. Then, starting with the least significant bit of the
family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial
number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value.

Figure 15. 1-Wire CRC Generation Block Diagram

MSb

XOR

LSb

XOR

INPUT

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HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain
or tri-state output drivers. The DS2762 used an open-drain output driver as part of the bidirectional interface
circuitry shown in Figure 16. If a bidirectional pin is not available on the bus master, separate output and input pins
can be connected together.

The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of
this resistor should be approximately 5k

W. The idle state for the 1-Wire bus is high. If, for any reason, a bus

transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. If the
bus is left low for more than 120

ms, slave devices on the bus begin to interpret the low period as a reset pulse,

effectively terminating the transaction.

Figure 16. 1-Wire Bus Interface Circuitry

TRANSACTION SEQUENCE

The protocol for accessing the DS2762 through the 1-Wire port is as follows:

§ Initialization

§ Net Address Command

§ Function

Command

§ Transaction/Data

The sections that follow describe each of these steps in detail.

All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the
bus master, followed by a presence pulse simultaneously transmitted by the DS2762 and any other slaves on the
bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For
more details, see the 1-Wire Signaling section.

(typ)

100

MOSFET

Rx = RECEIVE
Tx = TRANSMIT

PULLUP

(2.0V to 5.5V)

4.7k

BUS MASTER

DS2762 1-Wire PORT

DS2762 High-Precision Li+ Battery Monitor With Alerts

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NET ADDRESS COMMANDS

Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit
opcode for that command in square brackets. Figure 17 presents a transaction flowchart of the net address
commands.

Read Net Address [33h or 39h]. This command allows the bus master to read the DS2762's 1-Wire net address.
This command can only be used if there is a single slave on the bus. If more than one slave is present, a data
collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The
RNAOP bit in the status register selects the opcode for this command, with RNAOP = 0 indicating 33h, and
RNAOP = 1 indicating 39h.

Match Net Address [55h]. This command allows the bus master to specifically address one DS2762 on the 1-Wire
bus. Only the addressed DS2762 responds to any subsequent function command. All other slave devices ignore
the function command and wait for a reset pulse. This command can be used with one or more slave devices on
the bus.

Skip Net Address [CCh]. This command saves time when there is only one DS2762 on the bus by allowing the
bus master to issue a function command without specifying the address of the slave. If more than one slave device
is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at
the same time.

Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the
1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-
step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master
performs this simple three-step routine on each bit location of the net address. After one complete pass through all
64 bits, the bus master knows the address of one device. The remaining devices can then be identified on
additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton

Standards for a comprehensive

discussion of a net address search, including an actual example (

www.maxim-ic.com/iButtonBook

SWAP [AAh]. SWAP is a ROM level command specifically intended to aid in distributed multiplexing applications
and is described specifically with regards to power control using the 27xx series of products. The term power
control refers to the ability of the DS2762 to control the flow of power into or out the battery pack using control pins
DC and CC. The SWAP command is issued followed by the net address. The effect is to cause the addressed
device to enable power to or from the system while simultaneously (break-before-make) deselecting and powering
down (SLEEP) all other packs. This switching sequence is controlled by a timing pulse issued on the DQ line
following the net address. The falling edge of the pulse is used to disable power with the rising edge enabling
power flow by the selected device. The DS2762 recognizes a SWAP command, device address, and timing pulse
only if the SWEN bit is set.

FUNCTION COMMANDS

After successfully completing one of the net address commands, the bus master can access the features of the
DS2762 with any of the function commands described in the following paragraphs and summarized in Table 3. The
name of each function is followed by the 8-bit opcode for that command in square brackets.

Read Data [69h, XX]. This command reads data from the DS2762 starting at memory address XX. The LSb of the
data in address XX is available to be read immediately after the MSb of the address has been entered. Because
the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX
+ 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read
beyond address FFh, the DS2762 outputs logic 1 until a reset pulse occurs. Addresses labeled "Reserved" in the
memory map contain undefined data. The read data command can be terminated by the bus master with a reset
pulse at any bit boundary.

iButton is a registered trademark of Dallas Semiconductor.

DS2762 High-Precision Li+ Battery Monitor With Alerts

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Write Data [6Ch, XX]. This command writes data to the DS2762 starting at memory address XX. The LSb of the
data to be stored at address XX can be written immediately after the MSb of address has been entered. Because
the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX
+ 1 can be written immediately after the MSb to be stored at address XX. If the bus master continues to write
beyond address FFh, the DS2762 ignores the data. Writes to read-only addresses, reserved addresses and locked
EEPROM blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM blocks are to shadow
RAM rather than EEPROM. See the Memory section for more details.

Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte EEPROM
block containing address XX. Copy data commands that address locked blocks are ignored. While the copy data
command is executing, the EEC bit in the EEPROM register is set to 1 and writes to EEPROM addresses are
ignored. Reads and writes to non-EEPROM addresses can still occur while the copy is in progress. The copy data
command execution time, t

EEC

, is 2ms typical and starts after the last address bit is transmitted.

Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing address XX
to shadow RAM.

Lock [6Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory containing memory
address XX. The LOCK bit in the EEPROM register must be set to l before the lock command is executed. If the
LOCK bit is 0, the lock command has no effect. The lock command is permanent; a locked block can never be
written again.

Table 3. Function Commands

COMMAND

FUNCTION

COMMAND

PROTOCOL

BUS STATE AFTER

COMMAND PROTOCOL

BUS DATA

Read Data

Reads data from memory

starting at address XX

69h, XX

Master Rx

Up to 256 bytes of

data

Write Data

Writes data to memory

starting at address XX

6Ch, XX

Master Tx

Up to 256 bytes of

data

Copy Data

Copies shadow RAM data to

EEPROM block containing

address XX

48h, XX

Bus idle

None

Recall Data

Recalls EEPROM block

containing address XX to

shadow RAM

B8h, XX

Bus idle

None

Lock

Permanently locks the block

of EEPROM

containing address XX

6Ah, XX

Bus idle

None

DS2762 High-Precision Li+ Battery Monitor With Alerts

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Figure 17. Net Address Command Flow Chart

MASTER Tx

RESET PULSE

DS2762 Tx

PRESENCE PULSE

MASTER Tx

NET ADDRESS

COMMAND

55h

MATCH

33h / 39h

READ

F0h

CCh

SKIP

DS2762 Tx

FAMILY CODE

1 BYTE

DS2762 Tx

SERIAL NUMBER

6 BYTES

DS2762 Tx

CRC

1 BYTE

MASTER Tx

BIT 0

MATCH ?

MASTER TX

BIT 1

DS2762 Tx BIT 0

MASTER Tx BIT 0

BIT 0

MATCH ?

DS2762 Tx BIT 1

MASTER Tx BIT 1

BIT 1

MATCH ?

BIT 1

MATCH ?

MASTER TX

FUNCTION

COMMAND

MASTER TX

BIT 63

DS2762 Tx BIT 63

MASTER Tx BIT 63

BIT 63

MATCH ?

MASTER TX

FUNCTION

COMMAND

YES

AAh

SWAP

YES

MASTER TX

BIT 0

MATCH ?

MASTER TX

BIT 1

MATCH ?

MASTER TX

BIT 63

MATCH ?

YES

DS2762 TO

SLEEP MODE

FALLING EDGE

OF DQ

DS2762 TO

ACTIVE MODE

RISING EDGE

OF DQ

DS2762 High-Precision Li+ Battery Monitor With Alerts

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I/O SIGNALING

The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2762
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
The bus master initiates all these types of signaling except the presence pulse.

The initialization sequence required to begin any communication with the DS2762 is shown in Figure 18. A
presence pulse following a reset pulse indicates that the DS2762 is ready to accept a net address command. The
bus master transmits (Tx) a reset pulse for t

RSTL

. The bus master then releases the line and goes into receive mode

(Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin,
the DS2762 waits for t

PDH

and then transmits the presence pulse for t

PDL

Figure 18. 1-Wire Initialization Sequence

WRITE-TIME SLOTS

A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be t

SLOT

(60

ms to 120ms)

in duration with a 1

ms minimum recovery time, t

REC

, between cycles. The DS2762 samples the 1-Wire bus line

between 15

ms and 60ms after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when

sampled, a write 0 occurs (Figure 19). For the bus master to generate a write 1 time slot, the bus line must be
pulled low and then released, allowing the line to be pulled high within 15

ms after the start of the write time slot. For

the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the write-
time slot.

READ-TIME SLOTS

A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1

ms and then release it to allow the DS2762 to present valid

data. The bus master can then sample the data t

RDV

(15

ms) from the start of the read-time slot. By the end of the

read-time slot, the DS2762 releases the bus line and allows it to be pulled high by the external pullup resistor. All
read-time slots must be t

SLOT

(60

ms to 120ms) in duration with a 1ms minimum recovery time, t

REC

, between cycles.

See Figure 19 for more information.

RSTL

PDL

RSTH

PDH

PACK+

PACK-

LINE TYPE LEGEND:

BUS MASTER ACTIVE LOW

DS2762 ACTIVE LOW

RESISTOR PULLUP

BOTH BUS MASTER AND
DS2762 ACTIVE LOW

DS2762 High-Precision Li+ Battery Monitor With Alerts

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0

· Printed USA

25 of 25

SELECTOR GUIDE

PART

MARKING

PACKAGE INFORMATION

DS2762AE

DS2762A

TSSOP, External Sense Resistor, 4.275V V

DS2762BE

DS2762B

TSSOP, External Sense Resistor, 4.35V V

DS2762AE/T&R

DS2762A

DS2762AE on Tape-and-Reel

DS2762BE/T&R

DS2762B

DS2762BE on Tape-and-Reel

DS2762AE-025

2762A25

TSSOP, 25m

W Sense Resistor, 4.275V V

DS2762BE-025

2762B25

TSSOP, 25m

W Sense Resistor, 4.35V V

DS2762AE-025/T&R

2762A25

DS2762AE-025 in Tape-and-Reel

DS2762BE-025/T&R

2762B25

DS2762BE-025 in Tape-and-Reel

DS2762AX-025/T&R

DS2762AR

Flip-Chip, 25m

W Sense Resistor, Tape-and-Reel, 4.275V V

DS2762BX-025/T&R

DS2762BR

Flip-Chip, 25m

W Sense Resistor, Tape-and-Reel, 4.35V V

DS2762AX/T&R

DS2762A

Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.275V V

DS2762BX/T&R

DS2762B

Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.35V V

Note: Additional V

options are available, contact Maxim/Dallas Semiconductor sales.

PACKAGE INFORMATION

(For the latest package outline information, go to

www.maxim-ic.com/DallasPackInfo

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS2762BE

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DS2762BE