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REV: 062106
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.
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3100 is a complete central timing and
synchronization solution for SONET/SDH network
elements. With two multiprotocol BITS/SSU receivers
and 14 input clocks, the device directly accepts both
external timing and line timing from a large number of
line cards. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the stratum 3
and 3E requirements of GR1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3100 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward
compatible with Semtech's ACS8520 and ACS8530
timing card ICs.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
FEATURES
Synchronization Subsystem for Stratum 3E, 3,
4E and 4, SMC and SEC
Meets Requirements of GR-1244 Stratum 3/3E,
GR-253, G.812 Types I and III, and G.813
Stratum 3E Holdover Accuracy with Suitable
External Oscillator
Programmable Bandwidth, 0.5MHz to 70Hz
Hitless Reference Switching on Loss of Input
Phase Build-Out and Transient Absorption
Locks To and Generates 125MHz for Timing Over
Gigabit Ethernet per ITU-T G.pactiming
14 Input Clocks
10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
Two 64kHz Composite Clock Receivers
Continuous Input Clock Quality Monitoring
Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
One 64kHz Composite Clock Transmitter
One 1.544MHz/2.048MHz Output Clock
Two Sync Pulses: 8kHz and 2kHz
Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Two Multiprotocol BITS/SSU Transceivers
Receive and Transmit DS1, E1, 2048kHz, and
6312kHz Timing Signals
Insert and Extract SSM Messages (DS1, E1)
Automatically Invalidate Clocks on LOS, OOF, AIS,
and Other Defects
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS3100GN
-40
C to +85C
256 CSBGA (17mm
2
)
DS3100GN+ -40
C to +85C
256 CSBGA (17mm
2
)
+Denotes lead-free package.
DS3100
Stratum 3/3E Timing Card IC
www.maxim-ic.com
TIMING FROM
BITS/SSU
(DS1, E1, CC, ETC.)
TIMING FROM
LINE CARDS
(VARIOUS RATES)
14
2
LOCAL TCXO
OR OCXO
2
TIMING TO BITS/SSU
(DS1, E1, CC, ETC.)
11
TIMING TO
LINE CARDS
(VARIOUS RATES)
CONTROL STATUS
DS3100
SONET/SDH
SYNCHRONIZATION
IC
DS3100 Stratum 3/3E Timing Card IC
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TABLE OF CONTENTS
1.
STANDARDS COMPLIANCE ................................................................................................7
2.
BLOCK DIAGRAM.................................................................................................................8
3.
APPLICATION EXAMPLE .....................................................................................................9
4.
DETAILED DESCRIPTION ..................................................................................................10
5.
DETAILED FEATURES .......................................................................................................12
5.1
T0 DPLL F
EATURES
....................................................................................................................12
5.2
T4 DPLL F
EATURES
....................................................................................................................12
5.3
I
NPUT
C
LOCK
F
EATURES
.............................................................................................................12
5.4
O
UTPUT
C
LOCK
F
EATURES
..........................................................................................................13
5.5
R
EDUNDANCY
F
EATURES
.............................................................................................................13
5.6
BITS T
RANSCEIVER
F
EATURES
....................................................................................................13
5.6.1
General......................................................................................................................................... 13
5.6.2
Receiver ....................................................................................................................................... 13
5.6.3
Transmitter ................................................................................................................................... 14
5.7
C
OMPOSITE
C
LOCK
I/O F
EATURES
...............................................................................................14
5.8
G
ENERAL
F
EATURES
...................................................................................................................14
6.
PIN DESCRIPTIONS............................................................................................................15
7.
FUNCTIONAL DESCRIPTION.............................................................................................24
7.1
O
VERVIEW
..................................................................................................................................24
7.2
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
...................................................................................25
7.3
L
OCAL
O
SCILLATOR AND
M
ASTER
C
LOCK
C
ONFIGURATION
...........................................................25
7.4
I
NPUT
C
LOCK
C
ONFIGURATION
....................................................................................................26
7.4.1
Signal Format Configuration......................................................................................................... 26
7.4.2
Frequency Configuration .............................................................................................................. 28
7.5
I
NPUT
C
LOCK
Q
UALITY
M
ONITORING
............................................................................................29
7.5.1
Frequency Monitoring................................................................................................................... 29
7.5.2
Activity Monitoring ........................................................................................................................ 29
7.5.3
Selected Reference Activity Monitoring ....................................................................................... 30
7.5.4
Composite Clock Inputs ............................................................................................................... 30
7.6
I
NPUT
C
LOCK
P
RIORITY
, S
ELECTION
,
AND
S
WITCHING
..................................................................31
7.6.1
Priority Configuration.................................................................................................................... 31
7.6.2
Automatic Selection Algorithm ..................................................................................................... 31
7.6.3
Forced Selection .......................................................................................................................... 32
7.6.4
Ultra-Fast Reference Switching.................................................................................................... 32
7.6.5
External Reference Switching Mode ............................................................................................ 32
7.6.6
Output Clock Phase Continuity During Reference Switching ...................................................... 33
7.7
DPLL A
RCHITECTURE AND
C
ONFIGURATION
................................................................................33
7.7.1
T0 DPLL State Machine ............................................................................................................... 33
7.7.2
T4 DPLL State Machine ............................................................................................................... 36
7.7.3
Bandwidth..................................................................................................................................... 37
7.7.4
Damping Factor............................................................................................................................ 38
7.7.5
Phase Detectors........................................................................................................................... 38
7.7.6
Loss of Phase Lock Detection...................................................................................................... 39
7.7.7
Phase Monitor and Phase Build-Out............................................................................................ 40
7.7.8
Input to Output Phase Adjustment ............................................................................................... 41
7.7.9
Phase Recalibration ..................................................................................................................... 41
7.7.10
Frequency and Phase Measurement ........................................................................................... 41
7.7.11
Input Wander and Jitter Tolerance ............................................................................................... 42
DS3100 Stratum 3/3E Timing Card IC
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7.7.12
Jitter and Wander Transfer........................................................................................................... 42
7.7.13
Output Jitter and Wander ............................................................................................................. 43
7.8
O
UTPUT
C
LOCK
C
ONFIGURATION
.................................................................................................44
7.8.1
Signal Format Configuration......................................................................................................... 45
7.8.2
Frequency Configuration .............................................................................................................. 45
7.9
E
QUIPMENT
R
EDUNDANCY
C
ONFIGURATION
.................................................................................54
7.9.1
Master-Slave Pin Feature............................................................................................................. 55
7.9.2
Master-Slave Output Clock Phase Alignment .............................................................................. 55
7.9.3
Master-Slave Frame and Multi-Frame Alignment with the SYNC2K Pin ..................................... 56
7.10
M
ULTIPROTOCOL
BITS T
RANSCEIVERS
........................................................................................58
7.10.1
Master Clock Connections ........................................................................................................... 59
7.10.2
Receiver Clock Connections ........................................................................................................ 59
7.10.3
Transmitter Clock Connections .................................................................................................... 61
7.10.4
Line Interface Unit ........................................................................................................................ 62
7.10.5
DS1 Synchronization Interface..................................................................................................... 68
7.10.6
E1 Synchronization Interface ....................................................................................................... 70
7.10.7
G.703 2048kHz Synchronization Interface................................................................................... 72
7.10.8
G.703 Appendix II 6312kHz Japanese Synchronization Interface............................................... 73
7.11
C
OMPOSITE
C
LOCK
R
ECEIVERS AND
T
RANSMITTER
......................................................................74
7.11.1
IC1 and IC2 Receivers ................................................................................................................. 75
7.11.2
OC8 Transmitter ........................................................................................................................... 75
7.12
M
ICROPROCESSOR
I
NTERFACES
..................................................................................................77
7.12.1
Parallel Interface Modes............................................................................................................... 77
7.12.2
SPI Interface Mode....................................................................................................................... 77
7.13
R
ESET
L
OGIC
..............................................................................................................................79
7.14
P
OWER
-S
UPPLY
C
ONSIDERATIONS
..............................................................................................80
7.15
I
NITIALIZATION
.............................................................................................................................80
8.
REGISTER DESCRIPTIONS ...............................................................................................81
8.1
S
TATUS
B
ITS
...............................................................................................................................81
8.2
C
ONFIGURATION
F
IELDS
..............................................................................................................81
8.3
M
ULTIREGISTER
F
IELDS
...............................................................................................................81
8.4
C
ORE
R
EGISTER
D
EFINITIONS
......................................................................................................82
8.5
BITS T
RANSCEIVER
R
EGISTER
D
EFINITIONS
..............................................................................147
9.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................198
9.1
JTAG D
ESCRIPTION
..................................................................................................................198
9.2
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
...........................................................199
9.3
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
....................................................................201
9.4
JTAG T
EST
R
EGISTERS
............................................................................................................202
10.
ELECTRICAL CHARACTERISTICS..................................................................................203
10.1
DC C
HARACTERISTICS
..............................................................................................................203
10.2
I
NPUT
C
LOCK
T
IMING
.................................................................................................................207
10.3
O
UTPUT
C
LOCK
T
IMING
.............................................................................................................207
10.4
BITS T
RANSCEIVER
T
IMING
.......................................................................................................208
10.5
P
ARALLEL
I
NTERFACE
T
IMING
....................................................................................................210
10.6
SPI I
NTERFACE
T
IMING
..............................................................................................................213
10.7
JTAG I
NTERFACE
T
IMING
..........................................................................................................214
11.
PIN ASSIGNMENTS ..........................................................................................................215
12.
PACKAGE INFORMATION ...............................................................................................221
12.1
256-P
IN
CSBGA (17
MM X
17
MM
) (56-G6017-001)....................................................................221
13.
THERMAL INFORMATION................................................................................................222
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14.
GLOSSARY .......................................................................................................................223
15.
ACRONYMS AND ABBREVIATIONS ...............................................................................224
16.
TRADEMARK ACKNOWLEDGEMENTS ..........................................................................224
17.
DATA SHEET REVISION HISTORY..................................................................................225
DS3100 Stratum 3/3E Timing Card IC
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LIST OF FIGURES
Figure 2-1. DS3100 Block Diagram............................................................................................................................. 8
Figure 3-1. Typical Application Example ..................................................................................................................... 9
Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 34
Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 37
Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 43
Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 44
Figure 7-5. DPLL Block Diagram ............................................................................................................................... 46
Figure 7-6. OC10 8kHz Options ................................................................................................................................ 54
Figure 7-7. BITS Transceiver Block Diagram ............................................................................................................ 58
Figure 7-8. BITS Transceiver Master Clock PLL Block Diagram .............................................................................. 59
Figure 7-9. BITS Transmitter Clock Mux Block Diagram........................................................................................... 60
Figure 7-10. BITS Transceiver External Components............................................................................................... 62
Figure 7-11. Jitter Tolerance, DS1 Mode .................................................................................................................. 63
Figure 7-12. Jitter Tolerance, E1 and 2048kHz Modes............................................................................................. 64
Figure 7-13. Transmit Pulse Template, DS1 Mode ................................................................................................... 66
Figure 7-14. Transmit Pulse Template, E1 Mode...................................................................................................... 66
Figure 7-15. Transmit Pulse Template, 2048kHz Mode............................................................................................ 67
Figure 7-16. FAS/Si/RAI/Sa Source Logic................................................................................................................. 72
Figure 7-17. GR-378 Composite Clock Pulse Mask.................................................................................................. 76
Figure 7-18. SPI Clock Polarity and Phase Options.................................................................................................. 78
Figure 7-19. SPI Bus Transactions............................................................................................................................ 79
Figure 9-1. JTAG Block Diagram............................................................................................................................. 198
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 200
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 204
Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 205
Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 206
Figure 10-4. BITS Receiver Timing Diagram........................................................................................................... 208
Figure 10-5. BITS Transmitter Timing Diagram....................................................................................................... 209
Figure 10-6. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 211
Figure 10-7. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 212
Figure 10-8. SPI Interface Timing Diagram ............................................................................................................. 213
Figure 10-9. JTAG Timing Diagram......................................................................................................................... 214
Figure 11-1. DS3100 Pin Assignment--Left Half .................................................................................................... 219
Figure 11-2. DS3100 Pin Assignment--Right Half.................................................................................................. 220
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