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REV: 071
703
GENERAL DESCRIPTION
The DS3144 design kit is an easy-to-use evaluation
board for the DS3144 quad DS3/E3 framer. It is
intended to be used as a daughter card with the
DK101 motherboard or the DK2000 motherboard.
The DS3144DK comes complete with a DS3144
quad framer, DS3154 quad LIU, transformers,
termination resistors, network connectors, and
motherboard connectors. Interface to the
DK101/DK2000 and Dallas' ChipView software give
point-and-click access to configuration and status
registers from a personal computer. On-board LEDs
indicate loss-of-signal, out-of-frame, and interrupt
status. An on-board FPGA contains mux logic to
connect framer ports to one another or to the
DK2000 in a variety of configurations.
DESIGN KIT CONTENTS
DS3144DK Board
Download from
www.maxim-ic.com/DS3144DK
:
DS3144DK Data Sheet
ChipView Software
FEATURES
Demonstrates Key Functions of DS3144 Quad
DS3/E3 Framer
Includes DS3154 Quad LIU, Transformers, BNC
Connectors, and Termination Passives for
Communication with Test Equipment over Coax
Compatible with DK101 and DK2000 Demo Kit
Motherboards
DK101/DK2000 Interface and ChipView Software
Provide Point-and-Click Access to the DS3144
Register Set
All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
Memory-Mapped FPGA Provides Flexible
Clock/Data/Sync Connections Among Framer
Ports and DK2000 Motherboard
LEDs for Out-of-Frame, Loss-of-Signal, and
Interrupt
Easy-to-Read Silk Screen Labels Identify the
Signals Associated with all Connectors, Jumpers,
and LEDs
ORDERING INFORMATION
PART DESCRIPTION
DS3144DK
DS3144 Design Kit Daughter Card
DS3144DK
Quad DS3/E3 Framer
Design Kit Daughter Card
www.maxim-ic.com
DS3144 DS3/E3 Framer Design Kit Daughter Card
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COMPONENT LIST
DESIGNATION QTY
DESCRIPTION SUPPLIER
PART
C1, C2, C15
3
0.1
mF 10%, 16V ceramic capacitors (0805)
Panasonic ECJ-2VB1C104K
C3C9, C11C14,
C16, C20, C22,
C23, C25C32
23
0.1
mF 10%, 16V ceramic capacitors (0603)
Phycomp 06032R104K7B20D
C10, C17, C18, C24
4
1
mF 10%, 16V ceramic capacitors (1206)
Panasonic ECJ-3YB1C105K
C19, C21
2
10
mF 20%, 10V ceramic capacitors (1206)
Panasonic ECJ-3YB1A106M
DS1, DS3DS10
9
LED, red, SMD
Panasonic
LN1251C
DS2
1
LED, green, SMD
Panasonic
LN1351C
J1
1
10-pin connector, dual-row vertical Digi-Key
S2012-05-ND
J2J5
4
20-pin headers, dual-row vertical
Samtec
HDR-TSW-110-14-T-D
J6J11
6
5-pin BNC connectors, right-angle vertical
Cambridge
CP-BNCPC-004
J12, J13
2
5-pin BNC connectors, right-angle
Kruvand
UCBJR220
J14, J15
2
50-pin connectors, dual-row vertical
Samtec
TFM-125-02-S-D-LC
R1R5, R7R18,
R23, R28R59
49
30
W 5%, 1/16W resistors (0603)
Panasonic ERJ-3GEYJ300V
R6 1
470
W 5%, 1/10W resistor (0805)
Panasonic ERJ-6GEYJ471V
R19R22, R69R72
8
332
W 1%, 1/10W resistors (0805)
Panasonic ERJ-6ENF3320V
R24 1
10k
W 5%, 1/10W resistor (0805)
Panasonic ERJ-6GEYJ103V
R25, R26
2
330
W 5% 1/10W MF resistors (0805)
Panasonic ERA-6YEB331V
R27 1
Not
populated
--
--
R60 1
10k
W 5%, 1/10W resistor (0805)
Panasonic ERJ-6ENF1002V
R61R68 8
100
W 1/16W 5% resistors (0603)
Panasonic ERJ-3GEYJ101V
T1
1
XFMR, XMIT/RCV, 1 to 2, SMT 32-pin
Pulse Engineering T3049
U1 1
Serial configuration EEPROM for Xilinx, 65kB 8-
pin DIP. Socketed (not populated)
Atmel
AT17LV65EUA and
61499-30831007000-ND
U2 1
1M PROM for FPGA
44-pin TQFP (not populated)
Xilinx XC18V01VQ44C_U
U3 1
8-Pin
mMAX
V
OUT
= 2.5V or Adj
Maxim MAX1792EUA25
U4 1
Xilinx Spartan
2.5V FPGA, 20mm X 20mm 144-pin TQFP
Xilinx XC2S50-5TQ144C
U5 1
Quad DS3/E3 framer
144-pin BGA, 0C to +70C
Dallas
Semiconductor
DS3144
U6 1
Quad DS3/E3/STS-1 LIU
144-pin BGA
Dallas
Semiconductor
DS3154
Y1
1
3.3V, 34.368MHz crystal clock oscillator
SaRonix
NTH089AA3-34.368
BOARD FLOORPLAN
P
o
rt
1
B
NCs
DS3154
LIU
Quad
Trans
f
o
rm
er
DS3144
FRAMER
FPGA
+
Config
Prom
LEDs: RLOSn and INT
TEST POINTS
TICLKn
TDATn
TDENn
TSOFn
TOHENn
TOHn
TMEI
ROCLKn
RDATn
RDENn
RSOFn
RECU
34.
668
OS
C
JT
A
G
I/F
LEDs: ROOFn, FPGAok
FPGA
P
o
rt
2
B
NCs
P
o
rt
3
B
NCs
P
o
rt
4
B
NCs
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LINE-SIDE CONNECTIONS
The DS3144DK implements the transmit (Tx) and receive (Rx) line interface networks recommended in the
DS3154 data sheet. The BNC connectors are labeled TX1 through TX4 and RX1 through RX4. Note that the
purpose of the DS3144DK is to evaluate the DS3144 framer, not the DS3154 LIU. The DS3144DK is not an
impedance-matched board and therefore has not been designed to have transmit waveforms with optimal template
fit. To evaluate the analog performance of the DS3154, request a DS3154DK demo kit.
INTERFACE CONNECTORS
Two 50-pin connectors (J14, J15) on the bottom of the DS3144DK daughter card provide the processor interface,
DS3 clock, and power supply from the DK2000 and DK101 motherboards. These connectors also provide a
bidirectional clock/data/sync connection with the DK2000.
CONNECTION TO A COMPUTER
Refer to the DK101 and DK2000 data sheets for information. After power is applied, if the DS3144DK is working
correctly, the FPGA status LED (green) is lit, the INT LED (red) on the DS3144DK is not lit, and the RLOS and
ROOF LEDs (red) may or may not be lit.
QUICK SETUP (REGISTER VIEW)
1) Connect the DS3144DK daughter card to the DK101 motherboard or the DK2000 motherboard.
2) Connect the motherboard to a PC and a power supply as described in the motherboard data sheet.
3) Install and run the ChipView software, as described in the motherboard data sheet.
4) ChipView offers a choice between Register View, Demo, and Terminal Mode. Select Register View.
5) In the Definition File Assignment window, select the file DS3144DC_FPGA.def. This definition file will, in turn,
load DS3154DC.def, DS3144_1_DC.def, DS3144_2_DC.def, DS3144_3_DC.def, and DS3144_4_DC.def.
6) Next the Register View Screen appears, showing the register names, acronyms, and values for the DS3144,
DS3154, and the FPGA. Select among the register views using the pulldown menu box on the right.
Several register initialization (.INI) files are available for the DS3144DK. Initialization files are loaded by selecting
the menu option File
Register .INI FileLoad .INI File.
7) Load the .INI file DS3144_1_txPRBS215-1_Cbit.ini.
8) Switch to the DS3154 register view (DS3154DC.def) and set TCR1 = 0 and RCR1 = 0 on the DS3154 (this
clears the transmit tri-state and receive tri-state bits that are set on power-up in the DS3154).
9) Loopback port 1 by either (a) connecting a length of coax cable between the TX1 BNC and the RX1 BNC, or
(b) setting the GCR1:LLB (local loopback) bit in the DS3154.
10) Switch to the DS3144 port 1 register view (DS3144_1_DC.def). Toggle BCR1:TC high then low to begin
transmitting a 2
15
- 1 PRBS pattern. Toggle BCR1:RESYNC high then low to resynchronize the BERT receiver.
11) At this point the following may be observed:
Port 1 RLOS and ROOF LEDs are not lit, meaning the port 1 framer has acquired frame sync. This can
also be observed in the port 1 T3E3SR status register.
The port 1 BSR:SYNC bit is set, indicating the BERT receiver is receiving the 2
15
- 1 PRBS pattern.
This is a very basic setup designed to build familiarity with the DS3144DK. Many other configurations are possible.
Consult the DS3144 data sheet and the remainder of this data sheet for further information.
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MEMORY MAP
DK101 daughter card address space begins at 0x81000000.
DK2000 daughter card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets in
Table 1
below are relative to the beginning of the daughter card address space.
Table 1. Daughter Card Address Map
DS3/E3
PORT NUMBER
DS3144 OFFSET
DS3154 OFFSET
FPGA OFFSET
1
0x1300 to 0x13FF
0x2030 to 0x203F
0x0010 to 0x001F
2
0x1000 to 0x10FF
0x2010 to 0x201F
0x0020 to 0x002F
3
0x1100 to 0x11FF
0x2020 to 0x202F
0x0030 to 0x003F
4
0x1200 to 0x12FF
0x2000 to 0x200F
0x0040 to 0x004F
All offsets in
Table 2
below are relative to the daughter card address space plus the DS3/E3 port offset in Table 1.
Table 2. DS3144DK FPGA Register Map
OFFSET REGISTER TYPE
DESCRIPTION
0x0000 BID
Read-Only
Board
ID
0x0002 XBIDH
Read-Only
High Nibble Extended Board ID
0x0003 XBIDM
Read-Only
Middle Nibble Extended Board ID
0x0004 XBIDL
Read-Only
Low Nibble Extended Board ID
0x0005 BREV
Read-Only
Board Fab Revision
0x0006 AREV
Read-Only
Board Assembly Revision
0x0007 PREV
Read-Only
PLD Revision
0x000A
PCTC_SR
Control
PCM_TXCLK Source
0x000B PCTS_SR Control
PCM_TSYNC
Source
0x000C PCRX_SR Control
PCM_RXD
Source
0x000D PCRC_SR Control
PCM_RXCLK
Source
0x000E PCRS_SR Control
PCM_RSYNC
Source
0x0010
0x0020
0x0030
0x0040
TDAT_SR
Control
DS3144 TDAT Source
0x0011
0x0021
0x0031
0x0041
TICK_SR
Control
DS3144 TICLK Source
0x0012
0x0022
0x0032
0x0042
TSOF_SR
Control
DS3144 TSOF Source
Registers in the FPGA can be easily modified using the ChipView software and the definition file named
DS3144DC_FPGA.def. Registers 0x00 through 0x07 (excluding register 0x01, which has no function on the
DS3144DK) are read-only and are programmed at the factory to document board identification and revision
information. The remaining registers in the FPGA control the connection of the DS3144's equipment-side framer
pins. With these control registers, the framers within the DS3144 can be looped back on themselves externally,
connected to each other back-to-back, or connected to the DK2000 motherboard.
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In
Table 2
and the control register descriptions below, PCM_TXCLK, PCM_TXD, and PCM_TSYNC are
clock/data/sync lines over which the DS3144 can transmit a DS3/E3 data stream to the DK2000 motherboard or
other daughter cards plugged into the DK2000. PCM_RXCLK, PCM_RXD, and PCM_RSYNC are clock/data/sync
lines over which the DS3144DK can receive a DS3/E3 data stream from the DK2000 or a daughter card plugged
into the DK2000. See the DS3144DK schematics for additional details.
Note that the DS3/E3 port numbers of the DS3144DK (as silk-screened on the board) do not match the DS3144
port numbers and the DS3154 port numbers.
Table 3
details the mapping of device port numbers to board port
numbers. This mapping is reflected in the address ranges shown in
Table 1
.
Table 3. Relationship of Silk-Screened Port Numbers to IC Ports Numbers
SILK-SCREENED PORT NUMBER
ON BNCs AND RLOS/ROOF LEDs
DS3144 PORT
DS3154 PORT
1 4
4
2 1
2
3 2
3
4 3
1
From this it can be seen that, for example, the BNCs and LEDs for DS3144DK port 4 are associated with port 3 of
the DS3144 and port 1 of the DS3154.
CONTROL REGISTERS
Register Name:
PCTC_SR
Register Description:
PCM_TXCLK Source
Register Address Offset:
0x0A
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- --
PCS2
PCS1
PCS0
Default -- -- -- -- -- 0 0 0
Bits 2 to 0: PCM_TXCLK Source (PCS[2:0])
000 = Tri-state PCM_TXCLK
001 = Drive PCM_TXCLK with TDEN/TGCLK1
010 = Drive PCM_TXCLK with TDEN/TGCLK2
011 = Drive PCM_TXCLK with TDEN/TGCLK3
100 = Drive PCM_TXCLK with TDEN/TGCLK4
Register Name:
PCTS_SR
Register Description:
PCM_TSYNC Source
Register Address Offset:
0x0B
Bit
# 7 6 5 4 3 2 1 0
Name -- -- -- -- --
PSS2
PSS1
PSS0
Default -- -- -- -- -- 0 0 0
Bits 2 to 0: PCM_TSYNC Source (PSS[2:0])
000 = Tri-state PCM_TSYNC
001 = Drive PCM_TSYNC with TSOF1
010 = Drive PCM_TSYNC with TSOF2
011 = Drive PCM_TSYNC with TSOF3
100 = Drive PCM_TSYNC with TSOF4
Note: Only use non-zero settings of PSS[2:0] when the TSOFx pin is configured as an output by setting
MC3:TSOFC = 1 in the corresponding DS3144 framer.
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