ChipFind - документация

Электронный компонент: DS3170LN

Скачать:  PDF   ZIP

Document Outline


1 of 233
REV: 101404
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata
.



GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS
Access Concentrators
Routers and Switches
Multiservice Access
Platforms (MSAPs)
SONET/SDH ADM
SONET/SDH Muxes
Multiservice Protocol
Platform (MSPPs)
PBXs Test
Equipment
Digital Cross Connect
PDH Multiplexer/
Demultiplexer
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS3170
0C to +70C
100 CSBGA (11mm x
11mm, 1mm pitch)
DS3170L
0C to +70C
100 LQFP (14mm x
14mm, 1.4mm pitch)
DS3170N
-40C to +85C
100 CSBGA (11mm x
11mm, 1mm pitch)
DS3170LN
-40C to +85C
100 LQFP (14mm x
14mm, 1.4mm pitch)
FUNCTIONAL DIAGRAM
DS3170
DS3/E3 LINE
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES
Single-Chip Transceiver for DS3 and E3
Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
Uses 1:2 Transformers on Both Tx and Rx
On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
Software Compatible with DS3171DS3174 SCT
Product Family
8-/16-Bit Parallel and Slave SPI Serial (10Mbps)
Microprocessor Interface
Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
100-Pin Small 11mm (1mm) CSBGA and 14mm
(1.4mm) LQFP Package Options
Industrial Temperature Operation: -40C to +85C
IEEE1149.1 JTAG Test Port
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceiver
www.maxim-ic.com
DS3170 DS3/E3 Single-Chip Transceiver
2 of 233
DETAILED DESCRIPTION
The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has
independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and
data input. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard
pulse-shape waveforms onto 75
W coaxial cable and can be bypassed for direct clock and data output. The jitter
attenuator can be put in the transmit or receive data path when the LIU is enabled. Built-in DS3/E3 framers transmit
and receive data in properly formatted C-bit DS3, M23 DS3, G.751 E3 or G.832 E3 data streams. Functions not
used are powered down to reduce system power requirements. The DS3170 conforms to the telecommunications
standards listed in Section
3.2
.
1 BLOCK DIAGRAMS
Figure 1-1
shows the external components required at the LIU interface for proper operation.
Figure 1-2
shows the
functional block diagram of the one channel DS3/E3 SCT.
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170
1:2ct
1:2ct
Transmit
Receive
TXP
TXN
RXP
RXN
0.01uF
3.3V
Power
Plane
Ground
Plane
VDD
DS3/E3 LIU Interface
0.1uF
1uF
330
W
(1%)
330
W
(1%)
0.01uF
0.1uF
1uF
0.01uF
0.1uF
1uF
VDD
VDD
VSS
VSS
VSS
DS3170 DS3/E3 Single-Chip Transceiver
3 of 233
Figure 1-2. Block Diagram
TSOFO/TDEN
RLCLK
RXP
RXN
TPOS/TDAT
TNEG
TLCLK
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
D
[
15:
0]
A[
8:
1
]
ALE
CS
RD
/
DS
WR
/R
/
W
Serial or Parallel
uP Inteface
JTD
O
JT
C
L
K
JTM
S
JTD
I
JTR
S
T
HDLC
FEAC
TXP
TXN
LL
B
DL
B
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
RO
H
ROHCLK ROHSO
F
TO
H
TO
H
C
LK
TO
H
S
O
F
RSER
RCLKO/RGCLK
RSOFO/RDEN
DS3/E3
Receive
LIU
TAIS
TUA1
TO
H
E
N
Clock Rate
Adapter
RE
FCLK
MO
DE
IN
T
GP
I
O
[8
:1
]
WI
D
T
H
RDY
TCLKO/TGCLK
PL
B
AL
B
UA1
GEN
RPOS/RDAT
RNEG/RCLV
RST
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
Serial Interface Mode:
SPI (SCLK, MOSI, and MISO)
A[
0
]
/
B
SW
A
P
SPI
TCLKI
TSER
TSOFI
TX
BERT
RX
BERT
DS3170
DS3170 DS3/E3 Single-Chip Transceiver
4 of 233
TABLE OF CONTENTS
1
BLOCK DIAGRAMS
2
2
APPLICATIONS
12
3
FEATURE DETAILS
13
3.1
G
LOBAL
F
EATURES
........................................................................................................................................ 13
3.2
R
ECEIVE
DS3/E3 LIU F
EATURES
.................................................................................................................. 13
3.3
J
ITTER
A
TTENUATOR
F
EATURES
..................................................................................................................... 13
3.4
R
ECEIVE
DS3/E3 F
RAMER
F
EATURES
........................................................................................................... 13
3.5
T
RANSMIT
DS3/E3 F
ORMATTER
F
EATURES
.................................................................................................... 14
3.6
T
RANSMIT
DS3/E3
LIU F
EATURES
................................................................................................................. 14
3.7
C
LOCK
R
ATE
A
DAPTER
F
EATURES
................................................................................................................. 14
3.8
HDLC C
ONTROLLER
F
EATURES
..................................................................................................................... 14
3.9
FEAC C
ONTROLLER
F
EATURES
..................................................................................................................... 14
3.10
T
RAIL
T
RACE
B
UFFER
F
EATURES
................................................................................................................... 15
3.11
B
IT
E
RROR
-R
ATE
T
ESTER
(BERT) F
EATURES
................................................................................................ 15
3.12
L
OOPBACK
F
EATURES
................................................................................................................................... 15
3.13
M
ICROPROCESSOR
I
NTERFACE
F
EATURES
..................................................................................................... 15
3.14
S
LAVE
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) F
EATURES
................................................................................ 15
3.15
T
EST
F
EATURES
............................................................................................................................................ 15
4
STANDARDS COMPLIANCE
16
5
ACRONYMS AND GLOSSARY
17
6
MAJOR OPERATIONAL MODES
18
6.1
DS3/E3 F
RAMED
LIU M
ODE
.......................................................................................................................... 18
6.2
DS3/E3 U
NFRAMED
LIU M
ODE
..................................................................................................................... 20
6.3
DS3/E3 F
RAMED
POS/NEG M
ODE
............................................................................................................... 21
6.4
DS3/E3 U
NFRAMED
POS/NEG M
ODE
.......................................................................................................... 22
6.5
DS3/E3 F
RAMED
UNI M
ODE
......................................................................................................................... 23
6.6
DS3/E3 U
NFRAMED
UNI M
ODE
..................................................................................................................... 24
7
PIN DESCRIPTIONS
25
7.1
S
HORT
P
IN
D
ESCRIPTIONS
............................................................................................................................. 25
7.2
D
ETAILED
P
IN
D
ESCRIPTIONS
......................................................................................................................... 27
7.3
P
IN
F
UNCTIONAL
T
IMING
................................................................................................................................ 37
7.3.1
Line IO.................................................................................................................................................. 37
7.3.2
DS3/E3 Framing Overhead Functional Timing .................................................................................... 40
7.3.3
DS3/E3 Serial Data Interface............................................................................................................... 41
7.3.4
Microprocessor Interface Functional Timing ........................................................................................ 43
7.3.5
JTAG Functional Timing....................................................................................................................... 50
8
INITIALIZATION AND CONFIGURATION
51
8.1
M
ONITORING AND
D
EBUGGING
....................................................................................................................... 52
9
FUNCTIONAL DESCRIPTION
53
9.1
P
ROCESSOR
B
US
I
NTERFACE
......................................................................................................................... 53
9.1.1
SPI Serial Port Mode............................................................................................................................ 53
9.1.2
8/16 Bit Bus Widths.............................................................................................................................. 53
9.1.3
Ready Signal (
RDY
) ............................................................................................................................. 53
9.1.4
Byte Swap Modes ................................................................................................................................ 53
9.1.5
Read-Write/Data Strobe Modes........................................................................................................... 53
9.1.6
Clear on Read/Clear on Write Modes .................................................................................................. 53
9.1.7
Interrupt and Pin Modes....................................................................................................................... 54
9.1.8
Interrupt Structure ................................................................................................................................ 54
9.2
C
LOCKS
........................................................................................................................................................ 55
9.2.1
Line Clock Modes................................................................................................................................. 55
9.2.2
Sources of Clock Output Pin Signals ................................................................................................... 57
9.2.3
Line IO Pin Timing Source Selection ................................................................................................... 59
9.2.4
Clock Structures On Signal IO Pins ..................................................................................................... 62
DS3170 DS3/E3 Single-Chip Transceiver
5 of 233
9.2.5
Gapped Clocks..................................................................................................................................... 63
9.3
R
ESET AND
P
OWER
-D
OWN
............................................................................................................................ 63
9.4
G
LOBAL
R
ESOURCES
..................................................................................................................................... 66
9.4.1
Clock Rate Adapter (CLAD)................................................................................................................. 66
9.4.2
8 kHz Reference Generation ............................................................................................................... 66
9.4.3
One Second Reference Generation..................................................................................................... 67
9.4.4
General-Purpose IO Pins ..................................................................................................................... 68
9.4.5
Performance Monitor Counter Update Details ..................................................................................... 69
9.4.6
Transmit Manual Error Insertion .......................................................................................................... 70
9.5
P
ORT
R
ESOURCES
........................................................................................................................................ 71
9.5.1
Loopbacks............................................................................................................................................ 71
9.5.2
Loss Of Signal Propagation ................................................................................................................. 73
9.5.3
AIS Logic .............................................................................................................................................. 73
9.5.4
Loop Timing Mode ............................................................................................................................... 75
9.5.5
HDLC Overhead Controller .................................................................................................................. 75
9.5.6
Trail Trace ............................................................................................................................................ 75
9.5.7
BERT.................................................................................................................................................... 75
9.5.8
System Port Pins.................................................................................................................................. 76
9.5.9
Framing Modes .................................................................................................................................... 77
9.5.10
Line Interface Modes............................................................................................................................ 77
9.6
DS3/E3 F
RAMER
/ F
ORMATTER
..................................................................................................................... 79
9.6.1
General Description ............................................................................................................................. 79
9.6.2
Features ............................................................................................................................................... 79
9.6.3
Transmit Formatter............................................................................................................................... 80
9.6.4
Receive Framer.................................................................................................................................... 80
9.6.5
C-bit DS3 Framer/Formatter ................................................................................................................ 84
9.6.6
M23 DS3 Framer/Formatter ................................................................................................................. 87
9.6.7
G.751 E3 Framer/Formatter................................................................................................................. 89
9.6.8
G.832 E3 Framer/Formatter................................................................................................................. 91
9.7
HDLC O
VERHEAD
C
ONTROLLER
.................................................................................................................... 96
9.7.1
General Description ............................................................................................................................. 96
9.7.2
Features ............................................................................................................................................... 97
9.7.3
Transmit FIFO ...................................................................................................................................... 97
9.7.4
Transmit HDLC Overhead Processor .................................................................................................. 98
9.7.5
Receive HDLC Overhead Processor ................................................................................................... 98
9.7.6
Receive FIFO ....................................................................................................................................... 99
9.8
T
RAIL
T
RACE
C
ONTROLLER
............................................................................................................................ 99
9.8.1
General Description ............................................................................................................................. 99
9.8.2
Features ............................................................................................................................................. 100
9.8.3
Functional Description........................................................................................................................ 100
9.8.4
Transmit Data Storage ....................................................................................................................... 101
9.8.5
Transmit Trace ID Processor ............................................................................................................. 101
9.8.6
Transmit Trail Trace Processing ........................................................................................................ 101
9.8.7
Receive Trace ID Processor .............................................................................................................. 101
9.8.8
Receive Trail Trace Processing ......................................................................................................... 101
9.8.9
Receive Data Storage ........................................................................................................................ 102
9.9
FEAC C
ONTROLLER
................................................................................................................................... 102
9.9.1
General Description ........................................................................................................................... 102
9.9.2
Features ............................................................................................................................................. 103
9.9.3
Functional Description........................................................................................................................ 103
9.10
L
INE
E
NCODER
/D
ECODER
............................................................................................................................ 104
9.10.1
General Description ........................................................................................................................... 104
9.10.2
Features ............................................................................................................................................. 105
9.10.3
B3ZS/HDB3 Encoder ......................................................................................................................... 105
9.10.4
Transmit Line Interface ...................................................................................................................... 105
9.10.5
Receive Line Interface ....................................................................................................................... 106
9.10.6
B3ZS/HDB3 Decoder ......................................................................................................................... 106
9.11
BERT......................................................................................................................................................... 108
9.11.1
General Description ........................................................................................................................... 108