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General Description
The MAX1060/MAX1064 low-power, 10-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2s), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
V
LOGIC
pin that allows them to interface directly with a
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (V
DD
= V
LOGIC
) at a
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1060/MAX1064 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10A at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1060 has
eight input channels and the MAX1064 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1060 is available in a 28-pin QSOP package,
while the MAX1064 comes in a 24-pin QSOP. For pin-
compatible +3V, 10-bit versions, refer to the MAX1061/
MAX1063 data sheet.
Applications
Industrial Control Systems
Data Logging
Energy Management
Patient Monitoring
Data-Acquisition Systems
Touch Screens
Features
o 10-Bit Resolution, 0.5 LSB Linearity
o +5V Single-Supply Operation
o User-Adjustable Logic Level (+2.7V to +5.5V)
o Internal +2.5V Reference
o Software-Configurable Analog Input Multiplexer
8-Channel Single Ended/
4-Channel Pseudo-Differential (MAX1060)
4-Channel Single Ended/
2-Channel Pseudo-Differential (MAX1064)
o Software-Configurable Unipolar/Bipolar Analog
Inputs
o Low Current
2.5mA (400ksps)
1.0mA (100ksps)
400A (10ksps)
2A (Shutdown)
o Internal 6MHz Full-Power Bandwidth Track/Hold
o Byte-Wide Parallel (8 + 2) Interface
o Small Footprint
28-Pin QSOP (MAX1060)
24-Pin QSOP (MAX1064)
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
________________________________________________________________ Maxim Integrated Products
1
19-2723; Rev 0; 04/03
PART
MAX1060ACEI
0C to +70C
TEMP RANGE
PIN-PACKAGE
28 QSOP
Ordering Information
Pin Configurations
0.5
INL
(LSB)
MAX1060BCEI
0C to +70C
1
28 QSOP
MAX1060BEEI
MAX1060AEEI
-40C to +85C
1
-40C to +85C
0.5
28 QSOP
28 QSOP
Ordering Information continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
V
LOGIC
V
DD
REF
REFADJ
GND
COM
CH0
CH1
CH2
CH3
CS
CLK
WR
RD
INT
D0/D8
D1/D9
D2
D3
D4
D5
D6
D7
HBEN
QSOP
MAX1064
TOP VIEW
Pin Configurations continued at end of data sheet.
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= V
LOGIC
= +5V 10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7F capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
External acquisition or external clock mode
Internal acquisition/internal clock mode
MAX106_A
External acquisition/internal clock mode
External clock mode
-3dB rolloff
SINAD > 56dB
f
IN
= 175kHz, V
IN
= 2.5V
P-P
(Note 4)
f
IN1
= 49kHz, f
IN2
= 52kHz
MAX106_B
No missing codes over temperature
(Note 3)
CONDITIONS
ns
25
Aperture Delay
ns
400
t
ACQ
T/H Acquisition Time
s
3.2
3.6
4
2.5
3.0
3.5
2.1
t
CONV
Conversion Time (Note 5)
MHz
6
Full-Power Bandwidth
kHz
350
Full-Linear Bandwidth
dB
-78
Channel-to-Channel Crosstalk
dB
76
IMD
Intermodulation Distortion
dB
72
SFDR
Spurious-Free Dynamic Range
dB
-72
Total Harmonic Distortion
(Including 5th-Order Harmonic)
THD
0.5
INL
Relative Accuracy (Note 2)
Bits
10
RES
Resolution
dB
60
SINAD
Signal-to-Noise Plus Distortion
LSB
0.1
Channel-to-Channel Offset
Matching
ppm/C
2.0
Gain Temperature Coefficient
LSB
1
LSB
1
DNL
Differential Nonlinearity
LSB
2
Offset Error
LSB
2
Gain Error
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internal acquisition/internal clock mode
External acquisition or external clock mode
<200
ps
<50
Aperture Jitter
MHz
0.1
7.6
f
CLK
External Clock Frequency
%
30
70
Duty Cycle
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (f
IN(sine wave)
= 50kHz, V
IN
= 2.5V
P-P
, 400ksps, external f
CLK
= 7.6MHz, bipolar input mode)
CONVERSION RATE
V
DD
to GND ..............................................................-0.3V to +6V
V
LOGIC
to GND.........................................................-0.3V to +6V
CH0CH7, COM to GND ............................-0.3V to (V
DD
+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0D9, INT)
to GND ..............................................-0.3V to (V
LOGIC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
24-Pin QSOP (derate 9.5mW/C above +70C)...........762mW
28-Pin QSOP (derate 8.0mW/C above +70C)...........667mW
Operating Temperature Ranges
MAX1060_C_ _/MAX1064_C_ _ ......................... 0C to +70C
MAX1060_E_ _/MAX1064_E_ _ .......................-40C to +85C
Storage Temperature Range .............................-65C to +150C
Lead Temperature (soldering, 10s) .................................+300C
V
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V 10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7F capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25C.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
0 to 0.5mA output load (Note 7)
To power down the internal reference
For small adjustments
On-/off-leakage current, V
IN
= 0 or V
DD
Unipolar, V
COM
= 0
V
1.0
V
DD
+
50mV
V
REF
REF Input Voltage Range
F
4.7
10
Capacitive Bypass at REF
F
0.01
1
Capacitive Bypass at REFADJ
mV/mA
0.2
Load Regulation
V
V
DD
- 1.0
REFADJ High Threshold
mV
100
REFADJ Input Range
20
ppm/C
TC
REF
REF Temperature Coefficient
mA
15
REF Short-Circuit Current
V
2.49
2.5
2.51
REF Output Voltage
pF
12
C
IN
Input Capacitance
A
0.01
1
Multiplexer Leakage Current
V
Analog Input Voltage Range,
Single Ended and Differential
(Note 6)
0
V
REF
V
IN
CS = V
DD
I
SOURCE
= 1mA
I
SINK
= 1.6mA
V
IN
= 0 or V
DD
V
LOGIC
= 4.5V or 2.7V
V
LOGIC
= 4.5V
A
0.1
1
I
LEAKAGE
Tri-State Leakage Current
V
V
LOGIC
- 0.5
V
OH
Output Voltage High
V
0.4
V
OL
Output Voltage Low
pF
15
C
IN
Input Capacitance
A
0.1
1
I
IN
Input Leakage Current
mV
200
V
HYS
Input Hysteresis
V
0.8
V
IL
Input Voltage Low
V
4.0
CS = V
DD
pF
15
C
OUT
Tri-State Output Capacitance
Bipolar, V
COM
= V
REF
/ 2
-V
REF
/ 2
+V
REF
/ 2
V
LOGIC
= 2.7V
2.0
V
IH
Input Voltage High
T
A
= 0C to +70C
V
REF
= 2.5V, f
SAMPLE
= 400ksps
200
300
Shutdown mode
A
2
I
REF
Shutdown REF Input Current
ANALOG INPUTS
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REF
DIGITAL INPUTS AND OUTPUTS
Operating mode,
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= V
LOGIC
= +5V 10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7F capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25C.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Standby mode
Operating mode,
f
SAMPLE
= 400ksps
1.0
1.2
mA
2.5
2.9
2.9
3.4
I
DD
Positive Supply Current
V
4.5
5.5
V
DD
Analog Supply Voltage
200
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V 10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7F capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25C.)
V
LOGIC
Current
I
LOGIC
C
L
= 20pF
2
10
A
Power-Supply Rejection
PSR
V
DD
= 5V 10%, full-scale input
0.3
0.9
mV
f
SAMPLE
= 400ksps
Nonconverting
V
2.7
V
DD
+
0.3
V
LOGIC
Digital Supply Voltage
WR to CLK Fall Setup Time
t
CWS
40
ns
ns
CLK Pulse Width High
ns
CLK Period
t
CH
40
t
CP
132
CLK Pulse Width Low
t
CL
40
ns
Data Valid to WR Rise Time
t
DS
40
ns
WR Rise to Data Valid Hold Time
t
DH
0
ns
CLK Fall to WR Hold Time
t
CWH
40
ns
CS to CLK or WR Setup Time
t
CSWS
60
ns
CLK or WR to CS Hold Time
t
CSWH
0
ns
CS Pulse Width
t
CS
100
ns
WR Pulse Width
t
WR
60
ns
(Note 8)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Shutdown mode
2
10
0.5
0.8
POWER REQUIREMENTS
A
External reference
Internal reference
External reference
Internal reference
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
5
Note 1: Tested at V
DD
= +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
DD
.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V 10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7F capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25C.)
3k
3k
DOUT
DOUT
V
LOGIC
a) HIGH-Z TO V
OH
AND V
OL
TO V
OH
b) HIGH-Z TO V
OL
AND V
OH
TO V
OL
C
LOAD
20pF
C
LOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times
t
TR
10
40
ns
C
LOAD
= 20pF, Figure 1
RD Rise to Output Disable
RD Fall to Output Data Valid
t
DO
10
50
ns
RD Fall to INT High Delay
t
INT1
50
ns
CS Fall to Output Data Valid
t
DO2
100
ns
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
t
TC
10
60
ns
C
LOAD
= 20pF, Figure 1
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
CS Rise to Output Disable
HBEN Rise to Output Data Valid
t
DO1
10
50
ns
C
LOAD
= 20pF, Figure 1
HBEN Fall to Output Data Valid
t
DO1
10
80
ns
C
LOAD
= 20pF, Figure 1
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