_______________General Description
The MAX1151 is a parallel flash analog-to-digital con-
verter (ADC) capable of digitizing full-scale (0V to -2V)
inputs into 8-bit digital words at an update rate of
750Msps. The ECL-compatible outputs are demuxed
into two separate output banks, each with differential
data-ready outputs to ease the task of data capture.
The MAX1151's wide input bandwidth and low capaci-
tance eliminate the need for external track/hold amplifi-
ers for most applications. A proprietary decoding
scheme reduces metastable errors to 1LSB. This device
operates from a single -5.2V supply, with a nominal
power dissipation of 5.5W.
____________________________Features
o
1:2 Demuxed ECL-Compatible Outputs
o
Wide Input Bandwidth: 900MHz
o
Low Input Capacitance: 15pF
o
Metastable Errors Reduced to 1LSB
o
Single -5.2V Supply
________________________Applications
Digital Oscilloscopes
Data Acquisition
Transient-Capture Applications
Radar, EW, ECM
Direct RF/IF Downconversion
MAX1151
8-Bit, 750Msps Flash ADC
________________________________________________________________
Maxim Integrated Products
1
2
63
64
1
127
128
152
151
254
255
VFB
VRT
ANALOG
INPUT
PREAMP COMPARATOR
VRM
256-BIT TO 8-BIT DECODER
WITH MET
AST
ABLE ERROR CORRECTION
D8
(OVR)
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
1:2 DEMUL
TIPLEXER
D8B
D7B
D5B
D2B
D1B
D0B
D8A
D7A
D5A
D2A
D1A
D0A
BANK B
BANK A
NDRB (NOT DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
NDRA (NOT DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
ECL OUTPUT BUFFERS AND LA
TCHES
DEMUX
CLOCK BUFFER
CLOCK
BUFFER
CLK
NCLK
MAX1151
_________________________________________________________Functional Diagram
19-1170; Rev 0; 12/96
EVALUATION KIT
AVAILABLE
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
PART
MAX1151AIZS
MAX1151BIZS
-20C to +85C
-20C to +85C
TEMP. RANGE
PIN-PACKAGE
80 MQUAD
80 MQUAD
______________Ordering Information
Pin Configuration appears on last page.
MAX1151
8-Bit, 750Msps Flash ADC
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages
Negative Supply Voltage (V
EE
to GND) .............-7.0V to +0.5V
Ground Voltage Differential .................................-0.5V to +0.5V
Input Voltages
Analog Input Voltage .............................................+0.5V to V
EE
Reference Input Voltage ........................................+0.5V to V
EE
Digital Input Voltage ..............................................+0.5V to V
EE
Reference Current (V
RT
to V
RB
) ........................................35mA
Digital Output Current ...........................................0mA to -28mA
Operating Temperature Range ...........................-20C to +85C
Case Temperature ...........................................................+125C
Junction Temperature ......................................................+150C
Lead Temperature (soldering, 10sec). ............................+300C
Storage Temperature Range .............................-65C to +150C
IV
IV
I
V
V
I
I
V
I
IV
V
V
I
I
V
TEST
LEVEL
ns
1.25
1.75
2.25
Clock to Data Delay
ns
0.9
1.4
1.9
CLK to DATA READY Delay
ps
250
Acquisition Time
ps
2
Aperture Jitter
MHz
750
Maximum Sample Rate
MHz
30
Reference Bandwidth
60
80
Ladder Resistance
mV
-30
30
Offset Error V
RT
MHz
900
Input Bandwidth
LSB
-0.85
0.95
f
CLK
= 100kHz
Differential Nonlinearity
LSB
-1.0
1.0
f
CLK
= 100kHz
Bits
8
Resolution
Integral Nonlinearity
pF
15
Over full input range
k
15
Input Resistance
Guaranteed
No Missing Codes
V
V
RB
V
RT
Input Voltage Range
mA
0.75
2.0
V
IN
= 0V
Input Bias Current
UNITS
MAX1151A
MIN
TYP
MAX
CONDITIONS
PARAMETER
1.25
1.75
2.25
0.9
1.4
1.9
250
2
750
30
60
80
-30
30
900
-0.95
1.5
-1.5
1.5
8
15
15
Guaranteed
V
RB
V
RT
0.75
2.0
MAX1151B
MIN
TYP
MAX
ELECTRICAL CHARACTERISTICS
(V
EE
= -5.2V, V
RB
= -2.00V, V
RM
= -1.00V, V
RT
= 0.00V, f
CLK
= 750MHz, duty cycle = 50%, typical thermal impedance (
JC
) = 4C/W,
T
j
= T
C
= T
A
= +25C.) (Note 1)
Input Capacitance
Small signal
IV
mV
-30
30
Offset Error V
RB
-30
30
V
V/ns
5
Input Slew Rate
5
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT
TIMING CHARACTERISTICS
Large signal
V
500
500
MAX1151
8-Bit, 750Msps Flash ADC
_______________________________________________________________________________________
3
f
IN
= 250MHz
I
I
IV
V
I
I
I
I
I
I
I
I
I
TEST
LEVEL
A
1.05
1.2
Supply Current (I
EE
)
V
-4.95
-5.2
-5.45
Supply Voltage (V
EE
)
2.4
V
-1.8
-1.5
Logic "0" Voltage
V
-1.1
-0.9
Logic "1" Voltage
ns
0.67
0.5
Clock Pulse Width High
(t
PWH
)
44
dB
46
f
IN
= 50MHz
Signal-to-Noise Ratio
(without harmonics)
V
-1.8
-1.5
Input Low Voltage
(CLK, NCLK)
Input High Voltage
(CLK, NCLK)
V
-1.1
-0.7
dBc
-45
f
IN
= 50MHz
Total Harmonic Distortion
-37
f
IN
= 250MHz
dB
Signal-to-Noise and
Distortion
43
f
IN
= 50MHz
UNITS
MAX1151A
MIN
TYP
MAX
CONDITIONS
PARAMETER
1.05
1.2
-4.95
-5.2
-5.45
2.4
-1.8
-1.5
-1.1
-0.9
0.67
0.5
42
44
-1.8
-1.5
-1.1
-0.7
-43
-35
41
MAX1151B
MIN
TYP
MAX
I
I
dB
48
f
IN
= 50MHz
Spurious-Free Dynamic
Range
40
f
IN
= 250MHz
44
36
V
A
2
Clock Synchronous
Input Currents
2
Clock Pulse Width Low
(t
PWL
)
I
0.67
0.5
0.67
0.5
ns
I
W
5.5
6.25
Power Dissipation
5.5
6.25
POWER-SUPPLY REQUIREMENTS
DIGITAL OUTPUTS
DIGITAL INPUTS
DYNAMIC PERFORMANCE
ELECTRICAL CHARACTERISTICS (continued)
(V
EE
= -5.2V, V
RB
= -2.00V, V
RM
= -1.00V, V
RT
= 0.00V, f
CLK
= 750MHz, duty cycle = 50%, typical thermal impedance (
JC
) = 4C/W,
T
j
= T
C
= T
A
= +25C.) (Note 1)
Note 1:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality Assurance inspection. Unless otherwise noted, all tests are pulsed tests; therefore,
T
j
= T
C
= T
A
.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25C, and sample tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25C. Parameter is guaranteed over specified temperature range.
34
36
I
f
IN
= 250MHz
MAX1151
8-Bit, 750Msps Flash ADC
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
NAME
FUNCTION
1, 2, 3
D2B, D3B, D4B
Data Output Bank, Bits 2, 3, and 4
4, 5, 19, 20, 22, 23, 27, 28, 38, 39,
40, 46, 47, 49, 60, 67, 79
V
EE
Negative Supply, nominally -5.2V
PIN
6
D5B
Data Output Bank B, Bit 5
7, 9, 11, 54, 56, 58,
69, 71, 73, 75, 77
DGND
Digital Ground
13, 14, 31, 34, 41, 63, 64
N.C.
No Connection. Not internally connected.
12
D8B
Data Output Bank B, Bit 8 (OVR)
10
D7B
Data Output Bank B, Bit 7 (MSB)
8
D6B
Data Output Bank B, Bit 6
35
VRM
Reference-Voltage Middle, nominally -1V
32, 33
VIN
Analog Input Voltage. Can be either voltage or sense.
24
VRBS
Reference-Voltage Sense Bottom
21
VRBF
Reference-Voltage Force Bottom
15-18, 25, 26, 29, 30, 36,
37, 44, 45, 51, 52
AGND
Analog Ground
50
CLK
Clock Input
48
NCLK
Inverse Clock Input
43
VRTS
Reference-Voltage Sense Top
42
VRTF
Reference-Voltage Force Top
59, 61, 62, 65, 66, 68
D1AD6A
Data Output Bank A, Bits 16
57
D0A
Data Output Bank A, Bit 0 (LSB)
55
NDRA
Not Data Ready Bank A
53
DRA
Data Ready Bank A
72
D8A
Data Output Bank A, Bit 8 (OVR)
70
D7A
Data Output Bank A, Bit 7 (MSB)
80
D1B
Data Output Bank B, Bit 1
78
D0B
Data Output Bank B, Bit 0 (LSB)
76
DRB
Data Ready Bank B
74
NDRB
Not Data Ready Bank B
_______________Detailed Description
The MAX1151 is one of the fastest monolithic, 8-bit, paral-
lel, flash analog-to-digital converters (ADCs) available
today. The nominal conversion rate is 750Msps, and the
analog bandwidth is in excess of 900MHz. A major
advance over previous flash converters is the inclusion of
255 input preamplifiers between the reference ladder and
input comparators (see
Functional Diagram). This not
only reduces clock transient kickback to the input and
reference ladder but also reduces the effect of the input
signal's dynamic state on the input comparators' latching
characteristics. The preamplifiers act as buffers to stabi-
lize the input capacitance so that it remains constant over
different input voltage and frequency ranges, making the
part easier to drive than previous flash converters. The
preamplifiers also add a gain of +2 to the input signal, so
that each comparator has a wider overdrive or threshold
range to trip into or out of the active state. This gain
reduces metastable states that can cause errors at the
output.
The MAX1151 has true differential analog and digital
data paths from the preamplifiers to the output buffers
(current-mode logic) for reducing potential missing
codes while rejecting common-mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The device's output drive capability can
provide full ECL swings into 50
loads.
Typical Interface Circuit
The circuit of Figure 1 shows a method of achieving the
least error by correcting for integral linearity, input-
induced distortion, and power-supply/ground noise. This
is achieved with the use of external reference-ladder tap
connections, an input buffer, and supply decoupling.
Contact the factory for the MAX1150/MAX1151 evalua-
tion kit manual, which contains more details on interfac-
ing the MAX1151. The function of each pin and external
connections to other components are described in the fol-
lowing sections.
VEE, AGND, DGND
V
EE
is the supply pin with AGND as ground for the
device. The power-supply pins should be bypassed as
close to the device as possible with at least a 0.01F
ceramic capacitor. A 1F tantalum can also be used for
low-frequency suppression. DGND is the ground for the
ECL outputs, and should be referenced to the output
pulldown voltage and appropriately bypassed, as shown
in Figure 1.
VIN (Analog Input)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog
input sense, while the other is used for input force. This is
convenient for testing the source signal to see if there is
sufficient drive capability. The pins can also be tied to-
gether and driven by the same source. The MAX1151 is
superior to similar devices due to a preamplifier stage
before the comparators. This makes the device easier to
drive because it has constant capacitance and induces
less slew-rate distortion.
CLK, NCLK (Clock Inputs)
The clock inputs are designed to be driven differentially
with ECL levels. The duty cycle of the clock should be
kept at 50%, to avoid causing larger second harmonics.
If this is not important to the intended application, duty
cycles other than 50% may be used.
D0 to D8, DR, NDR (A and B)
The digital outputs can drive 50
to ECL levels when
pulled down to -2V. When pulled down to -5.2V, the out-
puts can drive 130
to 1k
loads. All digital outputs are
gray code, with the coding as shown in Table 1.
Table 1. Output Coding
VRBF, VRBS, VRTF, VRTS, VRM
(Reference Inputs)
There are two reference inputs and one external refer-
ence voltage tap. These are -2V (VRB force and sense),
mid-tap (VRM), and AGND (VRT force and sense). The
reference pins and tap can be driven by op amps (as
shown in Figure 1), or VRM can be bypassed for limited
temperature operation. These voltage inputs can be by-
passed to AGND for further noise suppression, if
desired.
Thermal Management
The typical thermal impedance (
CA
) for the MQUAD
package has been measured at
CA
= 17C/W, in still
air with no heatsink.
To ensure rated performance, we highly recommend
using this device with a heatsink that can provide ade-
quate air flow. We have found that a Thermalloy 17846
heatsink with a minimum air flow of 1 meter/second
(200 linear feet per minute) provides adequate thermal
performance under laboratory tests. Application-specif-
ic conditions should be taken into account to ensure
that the device is properly heat sinked.
MAX1151
8-Bit, 750Msps Flash ADC
_______________________________________________________________________________________
5
V
IN
(V)
D8
D7 . . . D0
0
-0.5
-1.0
-1.5
-2.0
1
0
0
0
0
10000000
10000001
10000011
10100001
10100000
11100000
11000001
11000000
01000000
01100001
01100000
00100000
00000011
00000001
00000000
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