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General Description
The MAX1190 is a 3.3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1190 is
optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumentation,
and digital communications. This ADC operates from a
single 2.8V to 3.6V supply, consuming only 492mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 57dB at an input frequency of 60MHz and a sampling
rate of 120Msps. The T/H driven input stages incorporate
400MHz (-3dB) input amplifiers. The converters can also
be operated with single-ended inputs. In addition to low
operating power, the MAX1190 features a 3mA sleep
mode, as well as a 1A power-down mode to conserve
power during idle periods.
An internal 2.048V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure
allows the use of this internal or an externally applied ref-
erence, if desired, for applications requiring increased
accuracy or a different input voltage range.
The MAX1190 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two's
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1190 is available in a 7mm
7mm, 48-pin TQFP-EP package, and is specified for the
extended industrial (-40C to +85C) temperature range.
Pin-compatible lower speed versions of the MAX1190 are
also available. Refer to the MAX1180MAX1184 data
sheets for 105Msps/80Msps/65Msps/40Msps. In addition
to these speed grades, this family includes two multi-
plexed output versions (MAX1185/MAX1186 for
20Msps/40Msps), for which digital data is presented
time-interleaved and on a single, parallel 10-bit output
port.
For lower speed, pin-compatible, 8-bit versions of the
MAX1190, refer to the MAX1195MAX1198 data sheets.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Features
o Single 3.3V Operation
o Excellent Dynamic Performance
57dB SINAD at f
IN
= 60MHz
64dBc SFDR at f
IN
= 60MHz
o -71dBc Interchannel Crosstalk at f
IN
= 60MHz
o Low Power
492mW (Normal Operation)
10mW (Sleep Mode)
3.3W (Shutdown Mode)
o 0.08dB Gain and 0.8 Phase Matching
o Wide 1V
P-P
Differential Analog Input Voltage
Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o User-Selectable Output Format--Two's Complement
or Offset Binary
o Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit
Versions Available
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
________________________________________________________________ Maxim Integrated Products
1
Ordering Information
19-2524; Rev 0; 7/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX1190ECM
-40
C to +85C
48 TQFP-EP*
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP-EP
GND
V
DD
GND
V
DD
T/B
SLEEP
PD
OE
D9B
D8B
D7B
D6B
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
MAX1190
Pin Configuration
*EP = Exposed paddle.
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V; OV
DD
= 2V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k
resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
+25C guaranteed by production test, <+25C guaranteed by design and characterization;
typical values are at T
A
= +25C.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (V
DD
+ 0.3V)
OE, PD, SLEEP, T/B,
D9AD0A, D9BD0B to OGND ...........-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
48-Pin TQFP (derate 12.5mW/C above +70C)........1000mW
Operating Temperature Range ...........................-40C to +85C
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
f
IN
= 7.47MHz
0.75
3
LSB
Differential Nonlinearity
DNL
f
IN
= 7.47MHz, no missing codes
guaranteed
-1
0.4
+1.5
LSB
Offset Error
<
1
1.8
%FS
Gain Error
0
2
%FS
ANALOG INPUT
Differential Input Voltage Range
V
DIFF
Differential or single-ended inputs
1.0
V
Common-Mode Input Voltage
Range
V
CM
V
DD
/ 2
0.5
V
Input Resistance
R
IN
Switched capacitor load
20
k
Input Capacitance
C
IN
5
pF
CONVERSION RATE
Maximum Clock Frequency
f
CLK
120
MHz
Data Latency
5
Clock
Cycles
DYNAMIC CHARACTERISTICS (f
CLK
= 120MHz, 4096-point FFT)
f
INA or B
= 20.01MHz at -0.5dB FS,
T
A
= +25C
55
58.5
f
INA or B
= 30.09MHz at -0.5dB FS
58.2
Signal-to-Noise Ratio
SNR
f
INA or B
= 59.74MHz at -0.5dB FS
58
dB
f
INA or B
= 20.01MHz at -0.5dB FS,
T
A
= +25C
54.5
57.5
f
INA or B
= 30.09MHz at -0.5dB FS
57
Signal-to-Noise and Distortion
SINAD
f
INA or B
= 59.74MHz at -0.5dB FS
57
dB
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________
3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
INA or B
= 20.01MHz at -0.5dB FS,
T
A
= +25C
58
67
f
INA or B
= 30.09MHz at -0.5dB FS
67
Spurious-Free Dynamic Range
SFDR
f
INA or B
= 59.74MHz at -0.5dB FS
64
dBc
f
INA or B
= 20.01MHz at -0.5dB FS,
T
A
= +25C
-67
f
INA or B
= 30.09MHz at -0.5dB FS
-67
Third-Harmonic
Distortion
HD3
f
INA or B
= 59.74MHz at -0.5dB FS
-64
dBc
Intermodulation Distortion
(First Five Odd-Order IMDs)
IMD
f
IN1(A or B)
= 43.393MHz at -6.5dB FS,
f
IN2(A or B)
= 48.9017MHz at -6.5dB FS
(Note 1)
-73
dBc
Third-Order Intermodulation
Distortion
IM3
f
IN1(A or B)
= 43.393MHz at -6.5dB FS,
f
IN2(A or B)
= 48.9017MHz at -6.5dB FS
(Note 1)
-83
dBc
f
INA or B
= 20.01MHz at -0.5dB FS,
T
A
= +25C
-65
-58
f
INA or B
= 30.09MHz at -0.5dB FS
-65
Total Harmonic Distortion
(First Four Harmonics)
THD
f
INA or B
= 59.74MHz at -0.5dB FS
-63
dBc
Small-Signal Bandwidth
Input at -20dB FS, differential inputs
500
MHz
Full-Power Bandwidth
FPBW
Input at -0.5dB FS, differential inputs
400
MHz
Aperture Delay
t
AD
1
ns
Aperture Jitter
t
AJ
2
ps
RMS
Overdrive Recovery Time
For 1.5
full-scale input
2
ns
INTERNAL REFERENCE
Reference Output Voltage
V
REFOUT
2.048
3%
V
Load Regulation
1.25
mV/mA
Reference Temperature
Coefficient
TC
REF
60
ppm/
C
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
Positive Reference Output
Voltage
V
REFP
(Note 2)
2.162
V
Negative Reference Output
Voltage
V
REFN
(Note 2)
1.138
V
Common-Mode Level
V
COM
(Note 2)
1.651
V
Differential Reference Output
Voltage Range
V
REF
V
REF
= V
REFP
- V
REFN
0.95
1.024
1.09
V
REFIN Resistance
R
REFIN
>50
M
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k
resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
+25C guaranteed by production test, <+25C guaranteed by design and characterization;
typical values are at T
A
= +25C.)
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
I
SOURCE
5
mA
Maximum REFP, COM Sink
Current
I
SINK
-250
A
Maximum REFN Source Current
I
SOURCE
250
A
Maximum REFN Sink Current
I
SINK
-5
mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
R
REFP
,
R
REFN
Measured between REFP and COM, and
REFN and COM
3.4
k
Differential Reference Input
Voltage Range
V
REF
V
REF
= V
REFP
- V
REFN
1.024
10%
V
COM Input Voltage Range
V
COM
V
DD
/ 2
10%
V
REFP Input Voltage
V
REFP
V
COM
+
V
REF
/ 2
V
REFN Input Voltage
V
REFN
V
COM
-
V
REF
/ 2
V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8
V
DD
Input High Threshold
V
IH
PD, OE, SLEEP, T/B
0.8
OV
DD
V
CLK
0.2
V
DD
Input Low Threshold
V
IL
PD, OE, SLEEP, T/B
0.2
OV
DD
V
Input Hysteresis
V
HYST
0.1
V
V
IH
= V
DD
(CLK)
5
I
IH
V
IH
= OV
DD
(PD, OE, SLEEP, T/B)
5
Input Leakage
I
IL
V
IL
= 0
5
A
Input Capacitance
C
IN
5
pF
DIGITAL OUTPUTS (D9AD0A, D9BD0B)
Output Voltage Low
V
OL
I
SINK
= -200A
0.2
V
Output Voltage High
V
OH
I
SOURCE
= 200A
OV
DD
-
0.2
V
Three-State Leakage Current
I
LEAK
OE = OV
DD
10
A
Three-State Output Capacitance
C
OUT
OE = OV
DD
5
pF
POWER REQUIREMENTS
Analog Supply Voltage Range
V
DD
2.8
3.3
3.6
V
Output Supply Voltage Range
OV
DD
1.7
2.5
3.6
V
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k
resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
+25C guaranteed by production test, <+25C guaranteed by design and characterization;
typical values are at T
A
= +25C.)
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________
5
Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1F (min) or 1F (typ) capacitor.
Note 3: Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating, f
INA and B
= 20.01MHz at
-0.5dB FS
149
185
Sleep mode
3
mA
Analog Supply Current
I
VDD
Shutdown, clock idle, PD = OE = OV
DD
1
15
A
Operating, f
INA and B
= 20.01MHz at -0.5dB
FS; see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
16
mA
Sleep mode
100
Output Supply Current
I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
2
10
A
Operating, f
INA and B
= 20.01MHz at
-0.5dB FS
492
611
mW
Sleep mode
10
mW
Analog Power Dissipation
PDISS
Shutdown, clock idle, PD = OE = OV
DD
3.3
50
W
Offset, V
DD
5%
3.4
mV/V
Power-Supply Rejection Ratio
PSRR
Gain, V
DD
5%
0.81
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
DO
C
L
= 20pF (Note 3)
4.8
7.4
ns
OE Fall to Output Enable Time
t
ENABLE
4.7
ns
OE Rise to Output Disable Time
t
DISABLE
1.2
ns
CLK Pulse Width High
t
CH
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
4.17
ns
CLK Pulse Width Low
t
CL
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
4.17
ns
Wake up from sleep mode (Note 4)
0.65
Wake-Up Time
t
WAKE
Wake up from shutdown mode (Note 4)
1.2
s
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
INA or B
= 20.01MHz at -0.5dB FS
-71
dBc
Gain Matching
f
INA or B
= 20.01MHz at -0.5dB FS (Note 5)
0.08
0.2
dB
Phase Matching
f
INA or B
= 20.01MHz at -0.5dB FS (Note 6)
0.8
Degrees
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k
resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
+25C guaranteed by production test, <+25C guaranteed by design and characterization;
typical values are at T
A
= +25C.)
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