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General Description
The MAX9206/MAX9208 deserializers transform a high-
speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri-
alizers such as the MAX9205/MAX9207, which gener-
ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PC board layout, and reduces
board size.
The MAX9206/MAX9208 receive serial data at
400Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.
A power-down mode reduces typical supply current to
less than 600A. Upon power-up (applying power or
driving PWRDN high), the MAX9206/MAX9208 estab-
lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high-
impedance state without losing lock.
The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40
C to
+85
C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.
Applications
Features
o Stand-Alone Deserializer (vs. SERDES) Ideal for
Unidirectional Links
o Automatic Clock Recovery
o Allow Hot Insertion and Synchronization Without
System Interruption
o BLVDS Serial Input Rated for Point-to-Point and
Bus Applications
o Fast Pseudorandom Lock
o Wide Reference Clock Input Range
16MHz to 40MHz (MAX9206)
40MHz to 60MHz (MAX9208)
o High 720ps (p-p) Jitter Tolerance (MAX9206)
o Low 30mA Supply Current (MAX9206 at 16MHz)
o 10-Bit Parallel LVCMOS/LVTTL Output
o Up to 600Mbps Throughput (MAX9208)
o Programmable Output Strobe Edge
o Pin Compatible to DS92LV1212A and
DS92LV1224
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
________________________________________________________________ Maxim Integrated Products
1
19-2130; Rev 0; 8/01
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Ordering Information
PART
TEMP.
RANGE
REF CLOCK
RANGE (MHz)
PIN-
PACKAGE
MAX9206EAI
-40
C to +85C
16 to 40
28 SSOP
MAX9208EAI
-40
C to +85C
40 to 60
28 SSOP
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PC BOARD OR
TWISTED PAIR
TCLK
PLL
PLL
EN
REN
PWRDN
INPUT LATCH
PARALLEL-TO-SERIAL
OUTPUT LATCH
SERIAL-TO-PARALLEL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
RCLK
LOCK
SYNC 1
SYNC 2
OUT+
OUT-
RI+
RI-
100
100
TCLK_R/F
RCLK_R/F
REFCLK
ROUT_
IN_
10
10
BUS
LVDS
MAX9205
MAX9207
MAX9206
MAX9208
Typical Operating Circuit
Cellular Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
CC
, DV
CC
to AGND, DGND .................................-0.3V to +4V
RI+, RI- to AGND, DGND .........................................-0.3V to +4V
All Other Pins to DGND ..............................-0.3V to DV
CC
+ 0.3V
ROUT_ Short-Circuit Duration (Note 1) ......................Continuous
Continuous Power Dissipation (T
A
= +70
C)
28-Pin SSOP (derate 9.5mW/
C above +70C) ..........762mW
Operating Temperature Range ...........................-40
C to +85C
Junction Temperature ......................................................+150
C
Storage Temperature Range .............................-65
C to +150C
ESD Rating (Human Body Model, RI+, RI-) .........................8kV
Lead Temperature (soldering, 10s) .................................+300
C
DC ELECTRICAL CHARACTERISTICS
(AV
CC
= DV
CC
= +3.0V to +3.6V, differential input voltage
|
V
ID
|
= 0.1V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to 2.4V
-
|
V
ID
/2
|
, T
A
= -40
C to +85C, unless otherwise noted. Typical values are at AV
CC
= DV
CC
= +3.3V, V
CM
= 1.1V,
|
V
ID
|
= 0.2V,
T
A
= +25
C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
16MHz
30
45
MAX9206
40MHz
57
75
40MHz
55
75
Supply Current
I
CC
C
L
= 15pF,
worst-case
pattern,
Figure 1
MAX9208
60MHz
80
100
mA
Power-Down Supply Current
I
CCX
PWRDWN = low
1
mA
LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/
F, PWRDN)
High-Level Input Voltage
V
IH
2.0
V
CC
V
Low-Level Input Voltage
V
IL
0
0.8
V
Input Current
I
IN
V
IN
= 0, AV
CC
, or DV
CC
-15
15
A
LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK,
LOCK)
High-Level Output Voltage
V
OH
I
OH
= -5mA
2.2
2.9
V
CC
V
Low-Level Output Voltage
V
OL
I
OL
= 5mA
0
0.33
0.5
V
Output Short-Circuit Current
I
OS
V
ROUT_
= 0
-15
-38
-85
mA
Output High-Impedance Current
I
OZ
PWRDN = low, V
ROUT_
= V
RCLK
= V
LOCK
= 0, AV
CC
, or DV
CC
-1
1
A
BLVDS SERIAL INPUT (RI+, RI-)
Differential Input High Threshold
V
TH
9
100
mV
Differential Input Low Threshold
V
TL
-100
-9
mV
0.1V
|V
ID
|
0.45V
-64
64
Input Current
I
RI+
, I
RI-
0.45V
< |V
ID
|
0.6V
-82
82
A
0.1V
|V
ID
|
0.45V, AV
CC
= DV
CC
= 0
-64
64
Power-Off Input Current
I
RI+OFF
,
I
RI-OFF
0.45V
< |V
ID
|
0.6V, AV
CC
= DV
CC
= 0
-82
82
A
Input Resistor 1
R
IN1
AV
CC
= DV
CC
= 3.6V or 0, Figure 2
4
k
Input Resistor 2
R
IN2
AV
CC
= DV
CC
= 3.6V or 0, Figure 2
150
k
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(AV
CC
= DV
CC
= +3.0V to +3.6V, C
L
= 15pF, differential input voltage
|
V
ID
|
= 0.15V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to
2.4V -
|
V
ID
/2
|
, T
A
= -40
C to +85C, unless otherwise noted. Typical values are at AV
CC
= DV
CC
= +3.3V, V
CM
= +1.1V,
|
V
ID
|
= 0.2V,
T
A
= +25
C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)
MAX9206
16
40
REFCLK Frequency
f
RFF
MAX9208
40
60
MHz
REFCLK Frequency Variation
RFFV
-200
200
ppm
MAX9206
25
62.5
REFCLK Period
t
RFCP
MAX9208
16.666
25
ns
REFCLK Duty Cycle
RFDC
30
50
70
%
REFCLK Input Transition Time
t
RFTT
3
6
ns
SWITCHING CHARACTERISTICS
MAX9206
25
62.5
Recovered Clock (RCLK) Period
(Note 6)
t
RCP
MAX9208
16.666
25
ns
Low-to-High Transition Time
t
CLH
Figure 3
1.5
3
ns
High-to-Low Transition Time
t
CHL
Figure 3
2
3
ns
MAX9206, 40MHz
1.75 x t
RC P
+ 2
1.75 x t
RC P
+ 3.3
1.75 x t
RC P
+ 6.5
Deserializer Delay
t
DD
Figure 4
MAX9208, 60MHz
1.75 x t
RC P
+ 1.1
1.75 x t
RC P
+ 3.3
1.75 x t
RC P
+ 5.6
ns
ROUT_ Data Valid Before RCLK
t
ROS
Figure 5
0.4 x t
RCP
0.5 x t
RC P
ns
ROUT_ Data Valid After RCLK
t
ROH
Figure 5
0.4 x t
RCP
0.5 x t
RC P
ns
RCLK Duty Cycle
t
RDC
43
50
57
%
OUTPUT High-to-High
Impedance Delay
t
HZR
C
L
= 5pF, Figure 6
8
ns
OUTPUT Low-to-High
Impedance Delay
t
LZR
C
L
= 5pF, Figure 6
8
ns
OUTPUT High-Impedance to
High-State Delay
t
ZHR
C
L
= 5pF, Figure 6
6
ns
OUTPUT High-Impedance to
Low-State Delay
t
ZLR
C
L
= 5pF, Figure 6
6
ns
PLL Lock Time (from
PWRDN
Transition High)
t
DSR1
Sync patterns at input; supply and
REFCLK stable; measured from
PWRDN transition high to LOCK
transition low; Figure 7
(2048 + 42)
x t
RFCP
ns
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
4
_______________________________________________________________________________________
Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground
except V
TH
, V
TL
, and V
ID
, which are differential input voltages.
Note 3: DC parameters are production tested at T
A
= +25C and guaranteed by design and characterization over operating temper-
ature range.
Note 4: AC parameters guaranteed by design and characterization.
Note 5: C
L
includes scope probe and test jig capacitance.
Note 6: t
RCP
is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-
cy of TCLK must be within 400ppm of the REFCLK frequency.
AC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= DV
CC
= +3.0V to +3.6V, C
L
= 15pF, differential input voltage
|
V
ID
|
= 0.15V to 1.2V, common-mode voltage V
CM
=
|
V
ID
/2
|
to
2.4V -
|
V
ID
/2
|
, T
A
= -40
C to +85C, unless otherwise noted. Typical values are at AV
CC
= DV
CC
= +3.3V, V
CM
= +1.1V,
|
V
ID
|
= 0.2V,
T
A
= +25
C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PLL Lock Time (from Start of
Sync Patterns)
t
DSR2
PLL locked to stable REFCLK; supply
stable; static input; measured from start
of sync patterns at input to
LOCK
transition low; Figure 8
42 x t
RFCP
ns
LOCK High-Z to High-State
Delay
t
ZHLK
Figure 7
30
ns
16MHz
1300
MAX9206
40MHz
720
40MHz
720
Input Jitter Tolerance
t
JT
Figure 9
MAX9208
60MHz
320
ps
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
Pin Description
PIN
NAME
FUNCTION
1, 12, 13
AGND
Analog Ground
2
RCLK_R/
F
Strobe Edge Select for Recovered Clock (RCLK). LVTTL/LVCMOS level input. Drive RCLK_ R/
F high
to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/
F low to strobe ROUT_ on the falling
edge of RCLK.
3
REFCLK
Reference Clock for PLL. LVTTL/LVCMOS level input.
4, 11
AV
CC
Analog Power Supply. Bypass AV
CC
with a 0.1F and a 0.001F capacitor to AGND.
5
RI+
Serial Data Input. Noninverting BLVDS differential input.
6
RI-
Serial Data Input. Inverting BLVDS differential input.
7
PWRDN
Power Down. LVTTL/LVCMOS level input. Drive
PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
8
REN
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance.
LOCK remains active, indicating the status of the serial input.
9
RCLK
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
10
LOCK
Lock Indicator. LVTTL/LVCMOS level output.
LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
14, 20,
22
DGND
Digital Ground
1519,
2428
ROUT9
ROUT0
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after
LOCK goes low.
21, 23
DV
CC
Digital Power Supply. Bypass DV
CC
with a 0.1F and a 0.001F capacitor to DGND.
Figure 1. Worst-Case ICC Test Pattern
0
0
END
BIT
9
8
7
6
5
4
3
1
0
START
BIT
END
BIT
9
7
6
5
4
3
2
1
2
1
8
2
START
BIT
T
DD
RCLK_R/F = HIGH
START
BIT
RI
RCLK
ODD
ROUT
EVEN
ROUT
Test Circuits/Timing Diagrams
_______________________________________________________________________________________
5
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