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_______________General Description
Maxim's MX7575/MX7576 are high-speed (5s/10s),
microprocessor (P) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/s slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2V
REF
.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit Ps through standard
CS and RD control sig-
nals. These signals control conversion start and data
access. A
BUSY signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a P data bus or system l/O port.
Maxim also makes the
MAX165
, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the
MAX166
is recommended.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
____________________________Features
o
Fast Conversion Time:
5s (MX7575)
10s (MX7576)
o
Built-In Track/Hold Function (MX7575)
o
Low Total Unadjusted Error (1LSB max)
o
50kHz Full-Power Signal Bandwidth (MX7575)
o
Single +5V Supply Operation
o
8-Bit P Interface
o
100ns Data-Access Time
o
Low Power: 15mW
o
Small-Footprint Packages
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
________________________________________________________________
Maxim Integrated Products
1
DAC
COMP
LATCH AND
THREE-STATE
OUTPUT DRIVERS
SAR
TRACK/
HOLD
CLOCK
OSCILLATOR
CONTROL
LOGIC
AIN
AGND
REF
CLK
CS
RD
V
DD
BUSY
DGND
TP
16
18
4
9
6
14
D7
.
.
D0
15
17
5
1
2
3
MX7575
Functional Diagrams continued at end of data sheet.
_______________Functional Diagrams
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
V
DD
REF
AIN
AGND
D0 (LSB)
D1
D2
D3
D4
CS
RD
TP (MODE)
BUSY
CLK
D7 (MSB)
D6
D5
DGND
TOP VIEW
10
9
DIP/SO
MX7575
MX7576
( ) ARE FOR MX7576 ONLY.
Pin Configurations continued at end of data sheet.
_________________Pin Configurations
19-0876; Rev 1; 5/96
PART
MX7575
JN
MX7575KN
MX7575JCWN
0C to +70C
0C to +70C
0C to +70C
TEMP. RANGE
PIN-PACKAGE
18 Plastic DIP
18 Plastic DIP
18 Wide SO
______________Ordering Information
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability.
MX7575KCWN
0C to +70C
18 Wide SO
MX7575JP
0C to +70C
20 PLCC
MX7575KP
0C to +70C
20 PLCC
INL
(LSB)
1
1/2
1
1/2
1
1/2
MX7575J/D
0C to +70C
Dice*
1
MX7575AQ
-25C to +85C
18 CERDIP**
MX7575BQ
-25C to +85C
18 CERDIP**
1
1/2
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= +5V; V
REF
= 1.23V; AGND = DGND = 0V; f
CLK
= 4MHz external for MX7575; f
CLK
= 2MHz external for MX7576;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to AGND...............................................................-0.3V, +7V
V
DD
to DGND ..............................................................-0.3V, +7V
AGND to DGND ...............................................-0.3V, V
DD
+ 0.3V
Digital Input Voltage to DGND
(
CS, RD, TP, MODE) ......................................-0.3V, V
DD
+ 0.3V
Digital Output Voltage to DGND
(
BUSY, D0D7) ..............................................-0.3V, V
DD
+ 0.3V
CLK Input Voltage to DGND ............................-0.3V, V
DD
+ 0.3V
REF to AGND ...................................................-0.3V, V
DD
+ 0.3V
AIN to AGND....................................................-0.3V, V
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70C)
Plastic DIP (derate 11.11mW/C above +70C) ...............889mW
Wide SO (derate 9.52mW/C above +70C)..................762mW
CERDIP (derate 10.53mW/C above +70C) .................842mW
PLCC (derate 10.00mW/C above +70C) ....................800mW
Operating Temperature Ranges
MX757_J/K ............................................................0C to +70C
MX757_A/B ........................................................-25C to +85C
MX757_JE/KE ....................................................-40C to +85C
MX757_S/T.......................................................-55C to +125C
Storage Temperature Range .............................-65C to +160C
Lead Temperature (soldering,10sec) ..............................+300C
V
IN
= 0V or V
DD
10
I
IN
Input Current
A
1
V
2.4
V
INH
Input High Voltage
V
0.8
V
INL
Input Low Voltage
A
500
I
REF
Reference Current
V
1.23
V
REF
Reference Voltage
dB
45
SNR
Signal-to-Noise Ratio (Note 2)
V/s
0.386
Slew Rate, Tracking
M
10
DC Input Impedance
V
0
2V
REF
Voltage Range
1
Bits
8
Resolution
ppm/C
5
Offset Tempco
LSB
1/2
Offset Error (Note 1)
ppm/C
5
Full-Scale Tempco
LSB
1
Full-Scale Error
LSB
2
TUE
Total Unadjusted Error
1/2
LSB
1
INL
Relative Accuracy
Bits
8
No-Missing-Codes Resolution
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
T
A
= T
MIN
to T
MAX
T
A
= +25C
MX757_K/B/T
5% variation for specified performance
MX7575, V
IN
= 2.46V
p-p
at 10kHz, Figure 13
MX7575
MX757_J/A/S
MX757_K/B/T
MX757_J/A/S
1LSB = 2V
REF
/256
CONDITIONS
pF
10
C
IN
Input Capacitance (Note 2)
ACCURACY
ANALOG INPUT
REFERENCE INPUT
LOGIC INPUTS
CS
,
RD
, MODE
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
_______________________________________________________________________________________
3
Note 1:
Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2:
Sample tested at +25C to ensure compliance.
Note 3:
Accuracy may degrade at conversion times other than those specified.
Note 4:
Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575
CS = RD = BUSY = high;
For MX7576
CS = RD = BUSY = MODE = high.
Using recommended
clock components:
R
CLK
= 100k
,
C
CLK
= 100pF;
T
A
= +25C
V
OUT
= 0V to V
DD
, D0D7
V
IN
= 0V
V
IN
= V
DD
4.75V < V
DD
< 5.25V
LSB
1/4
Power-Supply Rejection
mW
15
Power Dissipation
mA
7
I
DD
Supply Current
3
6
V
5
V
DD
Supply Voltage
s
10
30
Conversion Time with
Internal Clock
5
15
s
10
Conversion Time with
External Clock
5
pF
10
Floating State Output
Capacitance (Note 2)
A
10
Floating State Leakage Current
V
2.4
V
INH
Input High Voltage
V
0.8
V
INL
Input Low Voltage
1
V
4.0
V
OH
Output High Voltage
V
0.4
V
OL
Output Low Voltage
700
I
INL
A
800
Input Low Current
700
I
INH
A
800
Input High Current
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
MX757_S/T
MX757_J/A/K/B
5% for specified performance
MX7576
MX7575
MX7576: f
CLK
= 2MHz
T
A
= +25C
I
SOURCE
= 40A
MX7575: f
CLK
= 4MHz
I
SINK
= 1.6mA
MX757_J/A/K/B
MX757_S/T
MX757_J/A/K/B
D0D7
MX757_S/T
T
A
= T
MIN
to T
MAX
CONDITIONS
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V; V
REF
= 1.23V; AGND = DGND = 0V; f
CLK
= 4MHz external for MX7575; f
CLK
= 2MHz external for MX7576;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
CLOCK
LOGIC OUTPUTS (D0D7,
BUSY
)
CONVERSION TIME (Note 3)
POWER REQUIREMENTS (Note 4)
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
DIP/SO
NAME
FUNCTION
1
CS
Chip Select Input.
CS must be low for the device to be selected or to recognize the RD input.
PIN
2
RD
Read Input.
RD must be low to access data. RD is also used to start conversions. See the
Microprocessor Interface section.
TP
(MX7575)
Test Point. Connect to V
DD
.
7, 8
D6, D5
Three-State Data Outputs, bits 6 and 5
6
D7
Three-State Data Output, bit 7 (MSB)
5
CLK
External Clock Input/Internal Oscillator Pin for frequency setting RC components.
4
BUSY
BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the
end of a conversion.
9
DGND
Digital Ground
T
A
= +25C
T
A
= T
MIN
to T
MAX
ALL
J/K/A/B
S/T
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CS to RD Setup Time
t
1
0
0
0
ns
RD to BUSY Propagation Time
t
2
100
100
120
ns
Data-Access Time after
RD
t
3
(Note 6)
100
100
120
ns
RD Pulse Width
t
4
100
100
120
ns
CS to RD Hold Time
t
5
0
0
0
ns
Data-Access Time after
BUSY
t
6
(Note 6)
80
80
100
ns
Data-Hold Time
t
7
(Note 7)
10
80
10
80
10
100
ns
BUSY to CS Delay
t
8
0
0
0
ns
TIMING CHARACTERISTICS (Note 5)
(V
DD
= +5V, V
REF
= 1.23V, AGND = DGND = 0V.)
Note 5:
Timing specifications are sample tested at +25C to ensure compliance. All input control signals are specified with
t
r
= t
f
= 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6:
t
3
and t
6
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7:
t
7
is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
PLCC
2
3
4
8, 9
7
6
5
10
3
MODE
(MX7576)
Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
tied high for the synchronous conversion mode and the ROM interface mode.
14
D0
Three-State Data Output, bit 0 (LSB)
1013
D4D1
Three-State Data Outputs, bits 41
15
AGND
Analog Ground
16
1215
17
18
V
DD
Power-Supply Voltage. +5V nominal.
17
REF
Reference Input. +1.23V nominal.
--
N.C.
No Connect
20
19
1, 11
16
AIN
Analog Input. 0V to 2V
REF
input range.
18
Figure 1. Load Circuits for Data-Access Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see
Functional
Diagrams). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see
MX7575
Track/Hold and MX7576 Analog Input sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the
BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (P) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor Interface
The
CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode,
CS
and
RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
Ps that can be forced into a wait state. In the ROM
interface mode, however, the P is not forced into a wait
state. A conversion is started by taking
CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the P executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to V
DD
to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from V
DD
if TP is left open or tied to a voltage other than
V
DD
.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with Ps that have a wait-
state capability of at least 10s (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking
CS and RD
low). The
BUSY signal (which is connected to the P
READY input) then goes low and forces the P into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after
RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion,
BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the P com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the P is not forced into a wait state for an
excessive amount of time. Faster versions of many Ps,
MX7575/MX7576
CMOS, P-Compatible, 5s/10s, 8-Bit ADCs
_______________________________________________________________________________________
5
D_
D_
100pF
DGND
DGND
+5V
100pF
3k
3k
a) HIGH-Z TO V
OH
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
b) HIGH-Z TO V
OL
D_
D_
10pF
DGND
DGND
+5V
10pF
3k
3k
a) V
OH
TO HIGH-Z
b) V
OL
TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
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