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_______________General Description
The MXD1000 silicon delay line offers five equally
spaced taps with delays ranging from 4ns to 500ns and
a nominal accuracy of 2ns or 5%, whichever is
greater. Relative to hybrid solutions, this device offers
enhanced performance and higher reliability, and
reduces overall cost. Each tap can drive up to ten 74LS
loads.
The MXD1000 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin MAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1000 and other delay line products.
________________________Applications
Clock Synchronization
Digital Systems
____________________________Features
o
Improved Second Source to DS1000
o
Available in Space-Saving 8-Pin MAX Package
o
20mA Supply Current (vs. Dallas' 35mA)
o
Low Cost
o
Delay Tolerance of 2ns or 5%, whichever is
Greater
o
TTL/CMOS-Compatible Logic
o
Leading- and Trailing-Edge Accuracy
o
Custom Delays Available
MXD1000
5-Tap Silicon Delay Line
________________________________________________________________
Maxim Integrated Products
1
TAP3
TAP5
GND
1
2
8
7
V
CC
TAP1
TAP2
TAP4
IN
DIP/SO/
MAX
TOP VIEW
3
4
6
5
MXD1000
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
CC
N.C.
TAP1
N.C.
TAP2
N.C.
N.C.
IN
MXD1000
TAP3
N.C.
TAP5
GND
TAP4
N.C.
DIP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN
V
CC
N.C.
N.C.
TAP1
N.C.
TAP3
N.C.
TAP5
MXD1000
SO
N.C.
N.C.
TAP4
TAP2
N.C.
N.C.
GND
__________________________________________________________Pin Configurations
19-1310; Rev 0; 10/97
PART
MXD1000C/D__
MXD1000PA__
MXD1000PD__
-40C to +85C
-40C to +85C
0C to +70C
TEMP. RANGE
PIN-PACKAGE
Dice*
8 Plastic DIP
14 Plastic DIP
______________Ordering Information
*
Dice are tested at T
A
= +25C.
Note:
To complete the ordering information, fill in the blank
with the part number extension from the Part Number and Delay
Times table (located at the end of this data sheet) to indicate
the desired delay per output.
Functional Diagram appears at end of data sheet.
MXD1000SA__
MXD1000SE__
MXD1000UA__
-40C to +85C
-40C to +85C
-40C to +85C
8 SO
16 Narrow SO
8 MAX
MXD1000
5-Tap Silicon Delay Line
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
CC
= +5.0V 5%, T
A
= -40C to +85C, unless otherwise noted. Typical values are at T
A
= +25C.) (Note 2)
TIMING CHARACTERISTICS
(V
CC
= +5.0V 5%, T
A
= +25C, unless otherwise noted.)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:
Contact factory for ordering information.
Note 2:
Specifications to -40C are guaranteed by design, not production tested.
Note 3:
All voltages referenced to GND.
Note 4:
Measured with output open.
Note 5:
I
CC
is a function of frequency and TAP5 delay. Only an MXD1000_ _25 operating with a 40ns period and V
CC
= +5.25V will have
an I
CC
= 75mA. For example, an MXD1000_ _100 will never exceed 30mA. See Supply Current vs. Input Frequency in
Typical
Operating Characteristics.
Note 6:
Guaranteed by design.
Note 7:
Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling,
etc.). The device will remain functional with pulse widths down to 20% of TAP5 delay, and input periods as short as 2(t
WI
).
Note 8:
Typical initial tolerances are with respect to the nominal value at +25C and V
CC
= 5V.
Note 9:
Typical temperature tolerance is with respect to the initial delay value over a temperature range of -40C to +85C.
Note 10:
The delay will also vary with supply voltage, typically by less than 4% over the supply range of V
CC
= +4.75V to +5.25V.
Note 11:
All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP1 slows down, all other
taps will also slow down; i.e., TAP3 can never be faster than TAP2.
V
CC
to GND ..............................................................-0.5V to +6V
All Other Pins..............................................-0.5V to (V
CC
+ 0.5V)
Short-Circuit Output Current (1sec) ....................................50mA
Continuous Power Dissipation (T
A
= +70C)
8-Pin Plastic DIP (derate 9.1mW/C above +70C) .......727mW
14-Pin Plastic DIP (derate 10.0mW/C above +70C) ...800mW
8-Pin SO (derate 5.9mW/C above +70C)....................471mW
16-Pin Narrow SO (derate 8.7mW/C above +70C) .....696mW
8-Pin MAX (derate 4.1mW/C above +70C) ...............330mW
Operating Temperature Range ...........................-40C to +85C
Storage Temperature Range .............................-65C to +160C
Lead Temperature (soldering, 10sec) .............................+300C
(Note 3)
(Note 3)
(Note 3)
T
A
= +25C (Note 6)
0V
V
IN
V
CC
V
CC
= 5.25V, period = minimum (Notes 4, 5)
V
CC
= 4.75V, V
OH
= 4.0V
V
CC
= 4.75V, V
OL
= 0.5V
CONDITIONS
V
0.8
V
IL
Input Voltage Low
V
2.2
V
IH
V
4.75
5.00
5.25
V
CC
Supply Voltage
Input Voltage High
pF
5
10
C
IN
Input Capacitance
A
-1
1
I
L
Input Leakage Current
mA
20
75
I
CC
Active Current
mA
-1
I
OH
Output Current High
mA
12
I
OL
Output Current Low
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
(Notes 1, 812)
(Notes 1, 812)
(Note 7)
(Note 7)
CONDITIONS
ns
See
Part Number and
Delay Times table
t
PHL
Input-to-Tap Delay
(trailing edge)
ns
See
Part Number and
Delay Times table
t
PLH
ns
40% of TAP5
t
PLH
t
WI
Input Pulse Width
Input-to-Tap Delay
(leading edge)
ms
100
t
PU
Power-Up Time
ns
4(t
WI
)
Period
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
MXD1000
5-Tap Silicon Delay Line
_______________________________________________________________________________________
3
__________________________________________Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25C, unless otherwise noted.)
-2.0
-1.0
-1.5
0
-0.5
1.5
1.0
0.5
2.0
-40
0
-20
20
40
60
80
100
MXD1000_ _75
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1000 TOC01
TEMPERATURE (C)
% CHANGE IN DELAY (TAP2)
t
PLH
RELATIVE TO NOMINAL (+25C)
t
PHL
t
PHL
t
PLH
-2.0
-1.0
-1.5
0
-0.5
1.5
1.0
0.5
2.0
-40
0
-20
20
40
60
80
100
MXD1000_ _100 TO MXD1000_ _200
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1000 TOC2
TEMPERATURE (C)
% CHANGE IN DELAY (TAP2)
t
PHL
RELATIVE TO NOMINAL (+25C)
t
PHL
t
PLH
t
PLH
-2.0
-1.0
-1.5
0
-0.5
1.5
1.0
0.5
2.0
-40
0
-20
20
40
60
80
100
MXD1000_ _250 TO MXD1000_ _500
PERCENT CHANGE IN DELAY
vs. TEMPERATURE
MXD1000 TOC03
TEMPERATURE (C)
% CHANGE IN DELAY (TAP2)
t
PHL
RELATIVE TO NOMINAL (+25C)
t
PLH
t
PLH
t
PHL
20
8
10
12
14
16
18
0.001
0.01
0.1
1
10
100
ACTIVE CURRENT
vs. FREQUENCY
MXD1000-04
FREQUENCY (MHz)
ACTIVE CURRENT (mA)
MXD1000_ _50
MXD1000_ _75
MXD1000_ _200
MXD1000_ _500
50% DUTY CYCLE
MXD1000
5-Tap Silicon Delay Line
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
1
1
Signal Input
14-PIN DIP
FUNCTION
8-PIN
DIP/SO/MAX
NAME
16-PIN SO
2
4
40% of specified maximum delay
4
1
IN
TAP2
3
PIN
6
80% of specified maximum delay
4
7
Device Ground
8
6
TAP4
GND
5
8
100% of maximum specified delay
6
10
60% of specified maximum delay
11
9
TAP5
TAP3
7
12
20% of specified maximum delay
8
14
Power-Supply Input
16
13
TAP1
V
CC
--
2, 3, 5, 9, 11,
13
No Connection. Not internally connected.
2, 3, 5, 7, 10,
12, 14, 15
N.C.
Note:
Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________Definitions of Terms
Period:
The time elapsed between the first pulse's
leading edge and the following pulse's leading edge.
Pulse Width (t
WI
):
The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
Input Rise Time (t
RISE
):
The time elapsed between
the 20% and 80% points on the input pulse's leading
edge.
Input Fall Time (t
FALL
):
The time elapsed between
the 80% and 20% points on the input pulse's trailing
edge.
Time Delay, Rising (t
PLH
):
The time elapsed between
the 1.5V level on the input pulse's leading edge and the
corresponding output pulse's leading edge.
Time Delay, Falling (t
PHL
):
The time elapsed between
the 1.5V level on the input pulse's trailing edge and the
corresponding output pulse's trailing edge.
____________________Test Conditions
Ambient Temperature:
+25C 3C
Supply Voltage (V
CC
):
+5V 0.1V
Input Pulse:
High = 3.0V 0.1V
Low = 0.0V 0.1V
Source Impedance:
50
max
Rise and Fall Times:
3.0ns max
Pulse Width:
500ns max (1ns for -500)
Period:
1s (2ns for -500)
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
__________Applications Information
Supply and Temperature
Effects on Delay
Variations in supply voltage may affect the MXD1000's
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temper-
ature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.
Capacitance and Loading
Effects on Delay
The output load can affect the tap delays. Larger
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.
Board Layout Considerations/Decoupling
The device should be driven with a source that can
deliver the required current for proper operation. A
0.1F ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capaci-
tance.
MXD1000
5-Tap Silicon Delay Line
_______________________________________________________________________________________
5
V
IL
V
IH
PERIOD
t
RISE
IN
OUT
0.6V
0.6V
2.4V
2.4V
1.5V
1.5V
1.5V
1.5V
1.5V
t
FALL
t
WI
t
PLH
t
PHL
20%
50
0.1F
V
CC
IN
(+5V)
20%
TIME
MEASUREMENT
UNIT
TAP1
TAP2
TAP3
TAP4
TAP5
74FO4
20%
20%
20%
MXD1000
Figure 1. Timing Diagram
Figure 2. Test Circuit
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